86 lines
3.3 KiB
VHDL
86 lines
3.3 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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use IEEE.numeric_std.all;
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entity operators is
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generic (
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g_and : std_logic_vector(1 downto 0) := "11" and "10";
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g_or : std_logic_vector(1 downto 0) := "11" or "10";
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g_nand : std_logic_vector(1 downto 0) := "11" nand "10";
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g_nor : std_logic_vector(1 downto 0) := "11" nor "10";
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g_xor : std_logic_vector(1 downto 0) := "11" xor "10";
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g_xnor : std_logic_vector(1 downto 0) := "11" xnor "10";
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g_not : std_logic_vector(1 downto 0) := not "10"
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);
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port (
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clk_i : in std_logic
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);
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end entity operators;
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architecture rtl of operators is
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constant c_and : std_logic_vector(1 downto 0) := "11" and "10";
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constant c_or : std_logic_vector(1 downto 0) := "11" or "10";
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constant c_nand : std_logic_vector(1 downto 0) := "11" nand "10";
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constant c_nor : std_logic_vector(1 downto 0) := "11" nor "10";
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constant c_xor : std_logic_vector(1 downto 0) := "11" xor "10";
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constant c_xnor : std_logic_vector(1 downto 0) := "11" xnor "10";
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constant c_not : std_logic_vector(1 downto 0) := not "10";
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signal s_op1 : std_logic_vector(1 downto 0);
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signal s_op2 : std_logic_vector(1 downto 0);
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signal s_res : std_logic_vector(1 downto 0);
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signal s_int : integer;
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signal s_sig : signed(7 downto 0);
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signal s_uns : unsigned(7 downto 0);
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begin
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test_i: process(clk_i)
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variable v_op1 : std_logic_vector(1 downto 0);
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variable v_op2 : std_logic_vector(1 downto 0);
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variable v_res : std_logic_vector(1 downto 0);
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begin
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if rising_edge(clk_i) then
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if
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(s_op1="11" and s_op2="00") or
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(s_op1="11" or s_op2="00") or
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(s_op1="11" nand s_op2="00") or
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(s_op1="11" nor s_op2="00") or
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(not (s_op1="11"))
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then
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s_res <= s_op1 and s_op2;
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s_res <= s_op1 or s_op2;
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v_res := v_op1 nand v_op2;
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v_res := v_op1 nor v_op2;
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s_res <= s_op1 xor s_op2;
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v_res := v_op1 xnor v_op2;
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s_res <= not s_op1;
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s_int <= abs(s_int);
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s_sig <= abs(s_sig);
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s_sig <= s_sig sll 2;
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s_sig <= s_sig srl to_integer(s_sig);
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s_uns <= s_uns sll to_integer(s_uns);
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s_uns <= s_uns srl 9;
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s_sig <= shift_left(s_sig,2);
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s_sig <= shift_right(s_sig,to_integer(s_sig));
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-- s_uns <= s_uns ror 3; -- Not yet implemented
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-- s_uns <= s_uns rol to_integer(s_uns); -- Not yet implemented
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-- s_uns <= rotate_right(s_uns,3); -- Not yet implemented
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-- s_uns <= rotate_left(s_uns,to_integer(s_uns)); -- Not yet implemented
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s_sig <= s_sig rem s_int;
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s_sig <= s_sig mod s_int;
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end if;
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if
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s_sig = signed(s_uns) or unsigned(s_sig) /= s_uns or s_sig < "101010101" or
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s_sig <= signed(s_uns) or unsigned(s_sig) > s_uns or s_sig >= "00000101"
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then
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s_sig <= s_sig + s_sig;
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s_sig <= s_sig - s_sig;
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s_sig <= s_sig * s_sig;
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s_sig <= s_sig / s_sig;
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s_sig <= s_sig(7 downto 4) & "10" & signed(s_uns(1 downto 0));
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s_int <= 2 ** 3;
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end if;
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end if;
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end process test_i;
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end architecture rtl;
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