18 lines
403 B
VHDL
18 lines
403 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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entity signextend is
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port(
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i : in std_logic_vector(15 downto 0);
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o : out std_logic_vector(31 downto 0)
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);
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end entity signextend;
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architecture behavior of signextend is
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begin
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o(31 downto 24) <= (others => '0');
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o(23 downto 16) <= (others => i(15));
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o(15 downto 0) <= i;
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end architecture behavior;
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