28 lines
434 B
VHDL
28 lines
434 B
VHDL
library IEEE;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity whileloop is port(
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A : in integer;
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Z : out std_logic_vector(3 downto 0)
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);
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end whileloop;
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architecture rtl of whileloop is
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begin
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process (A)
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variable I : integer range 0 to 4;
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begin
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Z <= "0000";
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I := 0;
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while (I <= 3) loop
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if (A = I) then
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Z(I) <= '1';
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end if;
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I := I + 1;
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end loop;
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end process;
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end rtl;
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