fix custom library

2025-03-09 15:39:23 +08:00 · 2025-03-09 15:39:23 +08:00 · 08dd312389
commit 08dd312389
parent 4cf74020d2
10 changed files with 1988 additions and 1396 deletions
--- a/README.md
+++ b/README.md
@ -4,9 +4,9 @@
 ## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development


-[Document (New)](https://nc-ai.cn/) | [中文文档 (New)](https://nc-ai.cn/zh/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
+[Document (New)](https://nc-ai.cn/) | [中文文档 (New)](https://nc-ai.cn/zh/) | [Bilibili Video](https://www.bilibili.com/video/BV1L19HYcEz6/?spm_id_from=333.1387.list.card_archive.click) | [Github](https://github.com/Digital-EDA/Digital-IDE)

-![](https://img.shields.io/badge/version-0.4.0-purple)
+![](https://img.shields.io/badge/version-0.4.2-purple)
 ![](https://img.shields.io/badge/Verilog-support-green)
 ![](https://img.shields.io/badge/VHDL-support-green)
 ![](https://img.shields.io/badge/SystemVerilog-support-green)
@ -31,7 +31,7 @@

 ![](./figures/netlist.png)

-## New 0.4.1
+## New 0.4.2
 - Added comprehensive support for VHDL & SV (file tree, LSP, etc.)
 - Added workspace icons for languages or generated files such as Verilog, VHDL, XDC, TCL, VVP, VCD, etc.
 - Added support for Vivado, ModelSim, and Verilator. Users can use these third-party tools for simulation and auto-correction by setting `function.lsp.linter.vhdl.diagnostor` (for VHDL) and `function.lsp.linter.vlog.diagnostor` (for Verilog).
@ -47,4 +47,7 @@
 - Fixed a bug where comments on `input` and `output` were not displayed correctly in the documentation.
 - Fixed a bug in the Icarus Verilog simulation feature where duplicate paths were included as compilation parameters.
 - Fixed a bug in the Icarus Verilog simulation feature where adding or removing <code>include</code> would cause simulation compilation to fail (the `instModPathStatus` property of the instance was not updated).
+- Fixed simulation issues with Icarus Verilog version 12
+- Fixed the issue of being unable to import Block Design (BD) during Vivado project generation
+- Fixed the issue where libraries in custom mode could not be imported into Vivado
 - Fixed other known bugs.
--- a/package-lock.json
+++ b/package-lock.json
--- a/package.json
+++ b/package.json
@ -4,7 +4,7 @@
    "description": "all in one vscode plugin for Verilog/VHDL development",
    "publisher": "sterben",
    "homepage": "https://digital-eda.github.io/DIDE-doc-Cn",
-    "version": "0.4.1",
+    "version": "0.4.2",
    "main": "./out/extension",
    "l10n": "./l10n",
    "icon": "images/icon.png",
@ -1256,6 +1256,7 @@
        "@types/pako": "^2.0.3",
        "@types/showdown": "^2.0.0",
        "@types/vscode": "^1.72.0",
+        "@types/xml2js": "^0.4.14",
        "@typescript-eslint/eslint-plugin": "^5.42.0",
        "@typescript-eslint/parser": "^5.42.0",
        "@vscode/test-electron": "^2.2.0",
@ -1270,15 +1271,16 @@
        "chokidar": "^4.0.1",
        "minimatch": "^10.0.1",
        "pako": "^2.1.0",
-        "puppeteer-core": "^19.4.1",
+        "puppeteer-core": "^24.4.0",
        "showdown": "^2.1.0",
-        "state-machine-cat": "^9.2.5",
+        "state-machine-cat": "^12.0.21",
        "tar": "^7.4.3",
        "temp": "^0.9.4",
        "vscode-jsonrpc": "^8.2.1",
        "vscode-languageclient": "^9.0.1",
        "vscode-textmate": "^9.0.0",
        "wavedrom": "^2.9.1",
+        "xml2js": "^0.6.2",
        "zlib": "^1.0.5"
    }
 }
--- a/scripts/command/make_package.py
+++ b/scripts/command/make_package.py
@ -64,7 +64,7 @@ def modify_vsix():
    os.remove(dist_path)

    # move public
-    # copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public'))
+    copy_dir('./out-js/function/dide-netlist', os.path.join(extract_folder, 'extension', 'out', 'function', 'dide-netlist'))

    # webview
    copy_dir('./resources/dide-netlist/view', os.path.join(extract_folder, 'extension', 'resources', 'dide-netlist', 'view'))
@ -95,12 +95,12 @@ def install_extension():
    os.system('code --install-extension ' + vsix_path)

 pipe = CommandPipe()
-pipe.add_command('uninstall original extension', 'code --uninstall-extension sterben.fpga-support')
+# pipe.add_command('uninstall original extension', 'code --uninstall-extension sterben.fpga-support')
 pipe.add_command('compile typescript', 'tsc -p ./ --outDir out-js')
 pipe.add_command('webpack', 'webpack --mode production')
 pipe.add_command('make vsix installer', 'vsce package')
 pipe.add_command('modify vsix installer', lambda : modify_vsix())
-pipe.add_command('remove out-js', lambda : remove_folder('out-js'))
+# pipe.add_command('remove out-js', lambda : remove_folder('out-js'))
 # pipe.add_command('remove out', lambda : remove_folder('out'))
 # pipe.add_command('install', lambda : install_extension())

--- a/src/function/sim/simulate.ts
+++ b/src/function/sim/simulate.ts
@ -307,17 +307,22 @@ export class IcarusSimulate extends Simulate {
        }

        const extaArgs = args.join(' ');
-        let command = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name}`;
-        if (extaArgs) {
-            command += ' ' + extaArgs;
-        }
+        let command = `${iverilogPath} ${argu}`;

        // const parent = fspath.dirname(path);
+        if (alldeps.length) {            
            command += ' ' + '-I';
            for (let index = 0; index < alldeps.length; index++) {
                const element = alldeps[index];
                command += ' ' + '"' + hdlPath.resolve(element, '..') + '"'; 
            }
+        }
+
+        command += ' ' + `-o ${outVvpPath} -s ${name}`;
+
+        if (extaArgs) {
+            command += ' ' + extaArgs;
+        }

        return command;
    }
--- a/src/global/prjInfo.ts
+++ b/src/global/prjInfo.ts
@ -587,7 +587,7 @@ class PrjInfo implements PrjInfoMeta {
    }

    public get libCustomPath(): AbsPath {
-        const libPath = vscode.workspace.getConfiguration().get('digital-ide.lib.custom.path', this._workspacePath);
+        const libPath = join(vscode.workspace.getConfiguration().get('digital-ide.lib.custom.path', this._workspacePath));
        if (!fs.existsSync(libPath)) {                      
            return '';
        }
--- a/src/global/util.ts
+++ b/src/global/util.ts
@ -97,7 +97,6 @@ export class WebviewCollection {
 	}
 }

-
 export function replacePlaceholders(template: string, ...args: string[]): string {
    return template.replace(/\$(\d+)/g, (match, p1) => {
        const index = parseInt(p1, 10) - 1;
--- a/src/hdlParser/core.ts
+++ b/src/hdlParser/core.ts
@ -312,6 +312,8 @@ class HdlParam {
                    return common.HdlFileProjectType.LocalLib;
                } else if (path.startsWith(prjInfo.remoteLibPath)) {
                    return common.HdlFileProjectType.RemoteLib;
+                } else if (path.startsWith(prjInfo.libCustomPath)) {
+                    return common.HdlFileProjectType.RemoteLib;
                } else {
                    return common.HdlFileProjectType.Unknown;
                }
--- a/src/manager/PL/efinity.ts
+++ b/src/manager/PL/efinity.ts
@ -1,9 +1,109 @@
 import * as vscode from 'vscode';
+import { ChildProcessWithoutNullStreams, exec, spawn } from 'child_process';
+import * as fspath from 'path';
+import * as fs from 'fs';

-export async function generateEfinityConfig() {
+import { AbsPath, opeParam, PrjInfo } from '../../global';
+import { hdlParam } from '../../hdlParser/core';
+import { hdlFile, hdlDir, hdlPath } from '../../hdlFs';
+import { PropertySchema } from '../../global/propertySchema';
+
+import { XilinxIP } from '../../global/enum';
+import { HardwareOutput, MainOutput, ReportType } from '../../global/outputChannel';
+import { debounce, getPIDsWithName, killProcess } from '../../global/util';
+import { t } from '../../i18n';
+import { HdlFileProjectType } from '../../hdlParser/common';
+
+import { parseString, Builder, processors } from 'xml2js';
+
+const syn = `  <efx:synthesis tool_name="efx_map">
+    <efx:param name="work_dir" value="work_syn" value_type="e_string"/>
+    <efx:param name="write_efx_verilog" value="on" value_type="e_bool"/>
+    <efx:param name="mode" value="speed" value_type="e_option"/>
+    <efx:param name="max_ram" value="-1" value_type="e_integer"/>
+    <efx:param name="max_mult" value="-1" value_type="e_integer"/>
+    <efx:param name="infer-clk-enable" value="3" value_type="e_option"/>
+    <efx:param name="infer-sync-set-reset" value="1" value_type="e_option"/>
+    <efx:param name="min-sr-fanout" value="0" value_type="e_integer"/>
+    <efx:param name="min-ce-fanout" value="0" value_type="e_integer"/>
+    <efx:param name="fanout-limit" value="0" value_type="e_integer"/>
+    <efx:param name="bram_output_regs_packing" value="1" value_type="e_option"/>
+    <efx:param name="retiming" value="1" value_type="e_option"/>
+    <efx:param name="seq_opt" value="1" value_type="e_option"/>
+    <efx:param name="blast_const_operand_adders" value="1" value_type="e_option"/>
+    <efx:param name="operator-sharing" value="0" value_type="e_option"/>
+    <efx:param name="optimize-adder-tree" value="0" value_type="e_option"/>
+    <efx:param name="seq-opt-sync-only" value="0" value_type="e_option"/>
+    <efx:param name="blackbox-error" value="1" value_type="e_option"/>
+    <efx:param name="allow-const-ram-index" value="0" value_type="e_option"/>
+    <efx:param name="hdl-compile-unit" value="1" value_type="e_option"/>
+    <efx:param name="create-onehot-fsms" value="0" value_type="e_option"/>
+    <efx:param name="dsp-mac-packing" value="1" value_type="e_option"/>
+    <efx:param name="dsp-output-regs-packing" value="1" value_type="e_option"/>
+    <efx:param name="dsp-input-regs-packing" value="1" value_type="e_option"/>
+    <efx:param name="pack-luts-to-comb4" value="0" value_type="e_option"/>
+    <efx:param name="mult-auto-pipeline" value="0" value_type="e_option"/>
+    <efx:param name="mult-decomp-retime" value="0" value_type="e_option"/>
+    <efx:param name="optimize-zero-init-rom" value="1" value_type="e_option"/>
+    <efx:param name="use-logic-for-small-mem" value="64" value_type="e_integer"/>
+    <efx:param name="use-logic-for-small-rom" value="64" value_type="e_integer"/>
+    <efx:param name="insert-carry-skip" value="0" value_type="e_option"/>
+  </efx:synthesis>`;
+
+const pnr = `  <efx:place_and_route tool_name="efx_pnr">
+    <efx:param name="work_dir" value="work_pnr" value_type="e_string"/>
+    <efx:param name="verbose" value="off" value_type="e_bool"/>
+    <efx:param name="load_delaym" value="on" value_type="e_bool"/>
+    <efx:param name="optimization_level" value="NULL" value_type="e_option"/>
+    <efx:param name="seed" value="1" value_type="e_integer"/>
+    <efx:param name="placer_effort_level" value="2" value_type="e_option"/>
+    <efx:param name="max_threads" value="-1" value_type="e_integer"/>
+    <efx:param name="print_critical_path" value="10" value_type="e_integer"/>
+    <efx:param name="beneficial_skew" value="on" value_type="e_option"/>
+  </efx:place_and_route>`;
+
+const bit = `  <efx:bitstream_generation tool_name="efx_pgm">
+    <efx:param name="mode" value="active" value_type="e_option"/>
+    <efx:param name="width" value="1" value_type="e_option"/>
+    <efx:param name="enable_roms" value="smart" value_type="e_option"/>
+    <efx:param name="spi_low_power_mode" value="on" value_type="e_bool"/>
+    <efx:param name="io_weak_pullup" value="on" value_type="e_bool"/>
+    <efx:param name="oscillator_clock_divider" value="DIV8" value_type="e_option"/>
+    <efx:param name="bitstream_compression" value="on" value_type="e_bool"/>
+    <efx:param name="enable_external_master_clock" value="off" value_type="e_bool"/>
+    <efx:param name="active_capture_clk_edge" value="negedge" value_type="e_option"/>
+    <efx:param name="jtag_usercode" value="0xFFFFFFFF" value_type="e_string"/>
+    <efx:param name="release_tri_then_reset" value="on" value_type="e_bool"/>
+    <efx:param name="four_byte_addressing" value="off" value_type="e_bool"/>
+    <efx:param name="generate_bit" value="on" value_type="e_bool"/>
+    <efx:param name="generate_bitbin" value="off" value_type="e_bool"/>
+    <efx:param name="generate_hex" value="on" value_type="e_bool"/>
+    <efx:param name="generate_hexbin" value="off" value_type="e_bool"/>
+    <efx:param name="cold_boot" value="off" value_type="e_bool"/>
+    <efx:param name="cascade" value="off" value_type="e_option"/>
+  </efx:bitstream_generation>`;
+
+const debug = `  <efx:debugger>
+    <efx:param name="work_dir" value="work_dbg" value_type="e_string"/>
+    <efx:param name="auto_instantiation" value="off" value_type="e_bool"/>
+    <efx:param name="profile" value="NONE" value_type="e_string"/>
+  </efx:debugger>`;
+
+const security = `  <efx:security>
+    <efx:param name="randomize_iv_value" value="on" value_type="e_bool"/>
+    <efx:param name="iv_value" value="" value_type="e_string"/>
+    <efx:param name="enable_bitstream_encrypt" value="off" value_type="e_bool"/>
+    <efx:param name="enable_bitstream_auth" value="off" value_type="e_bool"/>
+    <efx:param name="encryption_key_file" value="NONE" value_type="e_string"/>
+    <efx:param name="auth_key_file" value="NONE" value_type="e_string"/>
+  </efx:security>`;

-}

 export class EfinityOperation {
+    // config: Record<string, any>;
+    constructor() {
+
+    }
+
    
 }
--- a/src/manager/PL/xilinx.ts
+++ b/src/manager/PL/xilinx.ts
@ -121,7 +121,6 @@ class XilinxOperation {
        };
    }
    
-
    public get topMod(): TopMod {
        return {
            src : opeParam.firstSrcTopModule.name,
@ -137,7 +136,6 @@ class XilinxOperation {
        };
    }

-
    /**
     * xilinx下的launch运行，打开存在的工程或者再没有工程时进行新建
     * @param context
@ -396,6 +394,7 @@ class XilinxOperation {
        });

        // 导入非本地的设计源文件
+        console.log(hdlParam.getAllHdlFiles());
        for (const hdlFile of hdlParam.getAllHdlFiles()) {
            switch (hdlFile.projectType) {
                case HdlFileProjectType.Src: