fix simulate
This commit is contained in:
parent
10fa4b14b1
commit
4cf74020d2
@ -2,6 +2,8 @@
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.gitignore
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**/.gitignore
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.git
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.github
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doc
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**/*.map
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.eslintrc.json
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dist
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@ -13,7 +13,7 @@
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</div>
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## New in 0.4.0
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## Features
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**Rewritten Parser and Language Services in Rust**: Supports Verilog, VHDL, and SystemVerilog with faster performance and more stable services.
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@ -31,8 +31,8 @@
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## Features
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- Added comprehensive support for VHDL (file tree, LSP, etc.)
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## New 0.4.1
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- Added comprehensive support for VHDL & SV (file tree, LSP, etc.)
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- Added workspace icons for languages or generated files such as Verilog, VHDL, XDC, TCL, VVP, VCD, etc.
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- Added support for Vivado, ModelSim, and Verilator. Users can use these third-party tools for simulation and auto-correction by setting `function.lsp.linter.vhdl.diagnostor` (for VHDL) and `function.lsp.linter.vlog.diagnostor` (for Verilog).
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- Added LSP and syntax highlighting support for scripts like TCL, XDC, and VVP.
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51
README_CN.md
51
README_CN.md
@ -1,51 +0,0 @@
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<div align="center">
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<img src="./images/icon.png"/>
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## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development
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[Document (New)](https://nc-ai.cn/en/) | [中文文档 (New)](https://nc-ai.cn/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
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</div>
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## 0.4.0 新增内容
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**使用 Rust 重写全新的解析器与语言服务**：支持 verilog, vhdl, system verilog，性能更快，服务更加稳定。
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**修缮内容的文档化**：提供更加直接快速的，关于当前 HDL 文件的基本信息和依赖信息。支持 wavedrom 风格的注释并支持将其渲染成可视化的图表。
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**新增内容的 Vcd 渲染器**：增加顶部工具栏、系统信标等组件；支持左侧面板选定信号的拖拽、分组等功能、支持按住 shift 连续选中一片信号并进行增加和删除操作；支持基于系统信标建立相对坐标系；顶部工具栏支持选中信号的显示数字的进制转换，渲染模态切换，支持将信号渲染为模拟量。
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- 全新的 Netlist 渲染器
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## Feature
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- 增加对于 vhdl 的 全面支持（文件树、LSP等）
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- 增加 verilog, vhdl, xdc, tcl, vvp, vcd 等语言或生成文件的工作区图标
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- 增加对于 vivado, modelsim, verilator 的支持，用户可以通过设置 `function.lsp.linter.vhdl.diagnostor`(设置 vhdl) 和 `function.lsp.linter.vlog.diagnostor`(设置 verilog) 来使用这些第三方工具的仿真和自动纠错。
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- 增加对于 TCL, XDC, VVP 等脚本的 LSP 和 语法高亮 支持。
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## Change
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- 将插件的工作状态显示在 vscode 下侧的状态栏上，利于用户了解目前的设置状态
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- 状态栏右下角现在可以看到目前选择的linter以及是否正常工作了
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- 优化项目配置目录
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- 优化自动补全的性能
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## Bug 修复
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- 修复文档化 input, output 处注释无法正常显示到文档的 bug
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- 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug
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- 修复 iverilog 仿真功能中，将 <code>`include</code> 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性）
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- 修复其他已知 bug
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@ -1,120 +0,0 @@
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<mxfile host="65bd71144e">
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<diagram id="Jyg0ghsg0WSuYoSyPP-c" name="linter">
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<mxGraphModel dx="868" dy="626" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="827" pageHeight="1169" math="0" shadow="0">
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</diagram>
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</mxfile>
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"description": "all in one vscode plugin for Verilog/VHDL development",
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"publisher": "sterben",
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"homepage": "https://digital-eda.github.io/DIDE-doc-Cn",
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"version": "0.4.0",
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"version": "0.4.1",
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"main": "./out/extension",
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"l10n": "./l10n",
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"icon": "images/icon.png",
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"xc7a35tftg256-1",
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"xc7a35tcsg324-1",
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"xc7z035ffg676-2",
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"xc7z020clg484-1",
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"hello-world"
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"xc7z020clg484-1"
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]
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}
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},
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dide-netlist
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- view
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- index.html
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- css
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- js
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- ...
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dide-netlist
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- view
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- index.html
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- css
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- js
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- ...
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- static
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os.remove(dist_path)
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# move public
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copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public'))
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# copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public'))
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# webview
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copy_dir('./resources/dide-netlist/view', os.path.join(extract_folder, 'extension', 'resources', 'dide-netlist', 'view'))
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pipe.add_command('make vsix installer', 'vsce package')
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pipe.add_command('modify vsix installer', lambda : modify_vsix())
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pipe.add_command('remove out-js', lambda : remove_folder('out-js'))
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pipe.add_command('remove out', lambda : remove_folder('out'))
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pipe.add_command('install', lambda : install_extension())
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# pipe.add_command('remove out', lambda : remove_folder('out'))
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# pipe.add_command('install', lambda : install_extension())
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pipe.run()
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@ -2,13 +2,13 @@ import * as vscode from 'vscode';
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import * as path from 'path';
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import * as hdlDoc from './dide-doc';
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import { makeDocWebview } from './dide-doc/html';
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import * as sim from './sim';
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import * as treeView from './treeView';
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import { tclCompletionProvider } from './lsp/completion/tcl';
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import * as lspFormatter from '../../resources/formatter';
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import * as lspTranslator from '../../resources/translator';
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import * as tool from './tool';
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// special function
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@ -27,7 +27,7 @@ function registerDocumentation(context: vscode.ExtensionContext) {
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// 展示 webview
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item.panel.reveal(vscode.ViewColumn.Two);
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} else {
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const panel = await hdlDoc.makeDocWebview(uri, context);
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const panel = await makeDocWebview(uri, context);
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// TODO: 注册文件变动监听
|
||||
const fileChangeDisposer = vscode.window.onDidChangeActiveTextEditor(async event => {
|
||||
// const client = LspClient.DigitalIDE;
|
||||
@ -46,7 +46,7 @@ function registerDocumentation(context: vscode.ExtensionContext) {
|
||||
// }
|
||||
});
|
||||
hdlDoc.docManager.set(standardPath, { panel, fileChangeDisposer });
|
||||
panel.onDidDispose(event => {
|
||||
panel.onDidDispose(() => {
|
||||
hdlDoc.docManager.delete(standardPath);
|
||||
fileChangeDisposer.dispose();
|
||||
});
|
||||
|
||||
@ -51,8 +51,9 @@ function measureRequestTimecost(url: string, timeout: number = 5): Promise<numbe
|
||||
|
||||
export async function chooseBestDownloadSource(signature: string, version: string, timeout: number = 3000) {
|
||||
const links = [
|
||||
getGithubDownloadLink(signature, version),
|
||||
getGiteeDownloadLink(signature, version)
|
||||
// TODO: lsp update
|
||||
getGithubDownloadLink(signature, '0.4.0'),
|
||||
getGiteeDownloadLink(signature, '0.4.0')
|
||||
];
|
||||
const pools: Promise<number>[] = [];
|
||||
for (const link of links) {
|
||||
|
||||
@ -13,6 +13,7 @@ import { ModuleDataItem } from '../treeView/tree';
|
||||
import { defaultMacro, doFastApi } from '../../hdlParser/util';
|
||||
import { t } from '../../i18n';
|
||||
import { openWaveViewer } from '../dide-viewer';
|
||||
import { HdlDependence } from '../../hdlParser/common';
|
||||
|
||||
type Path = string;
|
||||
|
||||
@ -68,7 +69,7 @@ class Simulate {
|
||||
rst : '', // 设置的复位信号
|
||||
end : '', //
|
||||
wave : '', // wave存放的路径
|
||||
simulationHome : '', // sim运行的路径
|
||||
simulationHome : '', // sim运行的路径
|
||||
gtkwavePath : '', // gtkwave安装路径
|
||||
installPath : '', // 第三方仿真工具的安装路径
|
||||
iverilogPath: 'iverilog', // iverilog仿真器所在路径
|
||||
@ -100,7 +101,6 @@ class Simulate {
|
||||
simConfig.simulationHome = defaultSimulationDir;
|
||||
}
|
||||
|
||||
|
||||
if (!hdlFile.isDir(simConfig.simulationHome)) {
|
||||
MainOutput.report('create dir ' + simConfig.simulationHome, {
|
||||
level: ReportType.Info
|
||||
@ -239,7 +239,7 @@ export class IcarusSimulate extends Simulate {
|
||||
* @description 获取 iverilog 仿真的命令
|
||||
* @returns
|
||||
*/
|
||||
private getCommand(name: string, path: AbsPath, dependences: string[]): string | undefined {
|
||||
private getCommand(name: string, path: AbsPath, dependences?: HdlDependence): string | undefined {
|
||||
MainOutput.clear();
|
||||
|
||||
const simConfig = this.getConfig(path, 'iverilog');
|
||||
@ -263,7 +263,17 @@ export class IcarusSimulate extends Simulate {
|
||||
const simLibPaths = this.getSimLibArr(this.toolChain);
|
||||
|
||||
const macroIncludeArgs = this.makeMacroIncludeArguments(iverilogCompileOptions.includes);
|
||||
const dependenceArgs = this.makeDependenceArguments(dependences);
|
||||
let otherdeps: string[] = [];
|
||||
let alldeps: string[] = [];
|
||||
if (dependences) {
|
||||
otherdeps = dependences.others;
|
||||
alldeps = dependences.include;
|
||||
}
|
||||
else {
|
||||
otherdeps = [];
|
||||
alldeps = [];
|
||||
}
|
||||
const dependenceArgs = this.makeDependenceArguments(otherdeps);
|
||||
const thirdLibraryArgs = this.makeThirdLibraryArguments(simLibPaths);
|
||||
|
||||
const thirdLibraryFileArgs = thirdLibraryArgs.fileArgsString;
|
||||
@ -302,8 +312,12 @@ export class IcarusSimulate extends Simulate {
|
||||
command += ' ' + extaArgs;
|
||||
}
|
||||
|
||||
const parent = fspath.dirname(path);
|
||||
command += ' ' + '-I"' + parent + '"';
|
||||
// const parent = fspath.dirname(path);
|
||||
command += ' ' + '-I';
|
||||
for (let index = 0; index < alldeps.length; index++) {
|
||||
const element = alldeps[index];
|
||||
command += ' ' + '"' + hdlPath.resolve(element, '..') + '"';
|
||||
}
|
||||
|
||||
return command;
|
||||
}
|
||||
@ -361,7 +375,7 @@ export class IcarusSimulate extends Simulate {
|
||||
* @description 运行 iverilog xxx 的命令
|
||||
*/
|
||||
private runIverilog(simConfig: SimulateConfig, command: string, cwd: string, hdlModule: HdlModule) {
|
||||
child_process.exec(command, (error, stdout, stderr) => {
|
||||
child_process.exec(command, { cwd }, (error, stdout, stderr) => {
|
||||
if (error) {
|
||||
this.reportCommandError(command, stderr);
|
||||
return;
|
||||
@ -391,7 +405,7 @@ export class IcarusSimulate extends Simulate {
|
||||
}
|
||||
|
||||
/**
|
||||
* @description 陨星 vvp xxx 的命令
|
||||
* @description 运行 vvp xxx 的命令
|
||||
*/
|
||||
private runVvp(command: string, cwd: string) {
|
||||
child_process.exec(command, { cwd }, (error, stdout, stderr) => {
|
||||
@ -496,11 +510,10 @@ export class IcarusSimulate extends Simulate {
|
||||
// MainOutput.report(warningMsg, ReportType.Warn, true);
|
||||
// return;
|
||||
// }
|
||||
|
||||
const dependences = this.getAllOtherDependences(path, name);
|
||||
const dependences = hdlParam.getAllDependences(path, name);
|
||||
const simulationCommand = this.getCommand(name, path, dependences);
|
||||
if (simulationCommand) {
|
||||
const cwd = hdlPath.resolve(path, '..');
|
||||
const cwd = hdlPath.resolve(path, '..');
|
||||
this.exec(simulationCommand, cwd, hdlModule);
|
||||
} else {
|
||||
const errorMsg = 'Fail to generate command';
|
||||
|
||||
@ -75,7 +75,7 @@ class XilinxOperation {
|
||||
}
|
||||
|
||||
public get xbdPath(): AbsPath {
|
||||
return hdlPath.join(opeParam.extensionPath, 'lib', 'xilinx', 'bd');
|
||||
return hdlPath.join(opeParam.extensionPath, 'library', 'Factory', 'xilinx', 'bd');
|
||||
}
|
||||
|
||||
public get xilinxPath(): AbsPath {
|
||||
@ -355,19 +355,7 @@ class XilinxOperation {
|
||||
vscode.window.showErrorMessage(`cp ${bd} failed, can not find ${bdSrcPath}`);
|
||||
}
|
||||
}
|
||||
|
||||
const bdPaths = [
|
||||
hdlPath.join(this.HWPath, 'bd'),
|
||||
hdlPath.join(this.prjInfo.path, this.prjInfo.name + '.src', 'sources_1', 'bd')
|
||||
];
|
||||
|
||||
hdlFile.pickFileRecursive(bdPaths, filePath => {
|
||||
if (filePath.endsWith('.bd')) {
|
||||
scripts.push(`add_files ${filePath} -quiet`);
|
||||
scripts.push(`add_files ${fspath.dirname(filePath)}/hdl -quiet`);
|
||||
}
|
||||
});
|
||||
|
||||
if (bd) {
|
||||
const loadBdPath = hdlPath.join(this.HWPath, 'bd', bd, bdFile);
|
||||
scripts.push(`generate_target all [get_files ${loadBdPath}] -quiet`);
|
||||
@ -375,6 +363,18 @@ class XilinxOperation {
|
||||
scripts.push(`open_bd_design ${loadBdPath} -quiet`);
|
||||
}
|
||||
}
|
||||
|
||||
const bdPaths = [
|
||||
hdlPath.join(this.HWPath, 'bd'),
|
||||
hdlPath.join(this.prjInfo.path, this.prjInfo.name + '.src', 'sources_1', 'bd')
|
||||
];
|
||||
|
||||
hdlFile.pickFileRecursive(bdPaths, filePath => {
|
||||
if (filePath.endsWith('.bd')) {
|
||||
scripts.push(`add_files ${filePath} -quiet`);
|
||||
scripts.push(`add_files ${fspath.dirname(filePath)}/hdl -quiet`);
|
||||
}
|
||||
});
|
||||
|
||||
const mrefPath = hdlPath.join(this.HWPath, 'bd', 'mref');
|
||||
hdlFile.pickFileRecursive(mrefPath, filePath => {
|
||||
|
||||
@ -270,7 +270,6 @@ class PrjManage {
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
public async createFolderByDefault(rawPrjInfo: RawPrjInfo) {
|
||||
// create prj first
|
||||
const defaultPrjPath = hdlPath.join(opeParam.workspacePath, 'prj');
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user