add icon to all kinds of file

CHANGELOG.md

@@ -4,14 +4,111 @@ All notable changes to the "digital-ide" extension will be documented in this fi
 
 Check [Keep a Changelog](http://keepachangelog.com/) for recommendations on how to structure this file.
 
-## [Unreleased]
+## [0.3.2] - 2023-11-01
-
-- Initial release
-
-
-## [2023.11.1]
 
 Bug 修复
 - 修复文档化input, output处注释无法正常显示到文档的 bug
 - 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug
 - 修复 iverilog 仿真功能中，将 `include 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性）
+
+Feat
+- 增加对 XDC，TCL 等脚本的 LSP 支持
+- 增加 verilog, vhdl, xdc, tcl 等语言的图标
+- 增加对于 vivado 的支持，用户可以通过添加 vivado 路径的方式来使用 vivado 的仿真和自动纠错
+
+
+## [0.1.23] - 2022-12-24
+- Finish the css of documentation, see `./css/documentation.css` for detail.
+
+## [0.1.23] - 2022-12-23
+- Finish the function of documentation, webview display
+- Finish the function of documentation, support export markdown and html
+
+## [0.1.23] - 2022-12-22
+- Rename partial tokens of verilog, make highlighting more colorful
+
+## [0.1.23] - 2022-12-05
+- Tree View can display the module that has not solved the dependence
+- Finish the function of Instance and add icon for each solved module
+
+## [0.1.23] - 2022-12-02
+- Add unit test for most of logic
+
+## [0.1.23] - 2022-12-01
+- Finish reconstruction of HDLparam
+- Finish the implementation of tree view
+
+## [0.1.22] - 2022-01-20
+
+- Fix lib files do not display in tree view
+
+## [0.1.21] - 2022-01-20
+
+- Fix issue [#26](https://github.com/Bestduan/Digital-IDE/issues/26)
+- Rename as Digital-IDE
+- Fix generate property.json file
+
+## [0.1.20] - 2022-01-12
+
+- Fix issue [#32](https://github.com/Bestduan/Digital-IDE/issues/32)
+
+## [0.1.18] - 2021-09-12
+
+- delete generate tb file 
+- add function netlist show
+- Fix issue [#25](https://github.com/Bestduan/fpga_support_plug/issues/25)
+- Fix issue [#24](https://github.com/Bestduan/fpga_support_plug/issues/24)
+
+## [0.1.17] - 2021-09-04
+
+- Fix issue [#22](https://github.com/Bestduan/fpga_support_plug/issues/22)
+- Fix issue [#21](https://github.com/Bestduan/fpga_support_plug/issues/21)
+- Fix issue [#20](https://github.com/Bestduan/fpga_support_plug/issues/20)
+
+
+## [0.1.16] - 2021-07-26
+
+- Optimization of the kernel, fix High CPU usage
+- Fix some other known bugs
+- Add Formatter function
+
+## [0.1.15] - 2021-05-02
+
+- Fix some bugs and add instructions
+
+## [0.1.12] - 2021-04-28
+
+- Added simulation function, automatically pop up error message
+
+## [0.1.10] - 2020-04-16
+
+- Added simulation function, automatically pop up error message
+
+## [0.1.8] - 2020-03-30
+
+- Fixed the problem of repeatedly opening a new project and supported adding devices directly from the Makefile
+
+## [0.1.6] - 2020-03-19
+
+- Add support for IP design and bd design
+- Add module jump (`Alt + F12` or `F12`)
+- Change the startup shortcut key
+- Fix some bugs to enhance robustness
+
+## [0.1.4] - 2020-03-10
+
+- Address the BUG existing in 0.1.3
+
+## [0.1.2] - 2020-03-03
+
+- Add Xilinx IP of Soc's cortexM3
+- Provide an example for `m3_for_xilinx.bd`
+- Resolve the file structure conversion problem
+
+## [0.0.2] - 2020-02-28
+
+- Added testbench / instance function
+
+## [0.0.1] - 2020-02-15
+
+- Initial Release

config/bd.configuration.json

@@ -0,0 +1,29 @@
+{
+  "comments": {
+    "lineComment": "#"
+  },
+  "brackets": [
+    ["{", "}"],
+    ["[", "]"],
+    ["(", ")"]
+  ],
+  "autoClosingPairs": [
+    ["{", "}"],
+    ["[", "]"],
+    ["(", ")"],
+    ["\"", "\""]
+  ],
+  "surroundingPairs": [
+    ["{", "}"],
+    ["[", "]"],
+    ["(", ")"],
+    ["\"", "\""]
+  ],
+  "folding": {
+    "markers": {
+      "start": "{",
+      "end": "}"
+    }
+  },
+  "wordPattern": "(?:(?:[^\\s\\{\\$\\\"]+|(?:\\$(?:\\w+|\\{[^\\}]+\\})))+)"
+}

images/svg/dark/bd.svg

@@ -0,0 +1 @@
+<svg t="1700403751622" class="icon" viewBox="0 0 1024 1024" version="1.1" xmlns="http://www.w3.org/2000/svg" p-id="4863" width="200" height="200"><path d="M64 764.330667a85.333333 85.333333 0 0 1 0-120.661334L643.669333 64a85.333333 85.333333 0 0 1 120.661334 0L938.666667 238.336a85.333333 85.333333 0 0 1 0 120.661333L358.997333 938.666667a85.333333 85.333333 0 0 1-120.661333 0L64 764.330667z m640-640L124.330667 704 298.666667 878.336 878.336 298.666667 704 124.330667zM392.832 222.165333a42.666667 42.666667 0 0 0 0-60.330666L294.997333 64a85.333333 85.333333 0 0 0-120.661333 0L64 174.336a85.333333 85.333333 0 0 0 0 120.661333l97.834667 97.834667a42.666667 42.666667 0 0 0 60.330666-60.330667L124.330667 234.666667 234.666667 124.330667l97.834666 97.834666a42.666667 42.666667 0 0 0 60.330667 0z m387.669333 448l94.165334 94.165334V874.666667h-110.336l-94.165334-94.165334a42.666667 42.666667 0 0 0-60.330666 60.330667l94.165333 94.165333a85.333333 85.333333 0 0 0 60.330667 25.002667H874.666667a85.333333 85.333333 0 0 0 85.333333-85.333333v-110.336a85.333333 85.333333 0 0 0-25.002667-60.330667l-94.165333-94.165333a42.666667 42.666667 0 0 0-60.330667 60.330666z" fill="#d4237a" p-id="4864"></path><path d="M210.304 512a42.666667 42.666667 0 0 1 60.330667 0l60.330666 60.330667a42.666667 42.666667 0 0 1-60.330666 60.373333L210.346667 572.288a42.666667 42.666667 0 0 1 0-60.330667zM361.130667 361.130667a42.666667 42.666667 0 0 1 60.373333 0l60.330667 60.373333a42.666667 42.666667 0 0 1-60.330667 60.330667L361.130667 421.504a42.666667 42.666667 0 0 1 0-60.373333zM512 210.304a42.666667 42.666667 0 0 1 60.330667 0l60.330666 60.330667a42.666667 42.666667 0 0 1-60.330666 60.330666L512 270.634667a42.666667 42.666667 0 0 1 0-60.330667z" fill="#d4237a" p-id="4865"></path></svg>

images/svg/dark/systemverilog.backup.svg

@@ -0,0 +1 @@
+<svg version="1.1" viewBox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="m13 9h5.5l-5.5-5.5v5.5m-7-7h8l6 6v12a2 2 0 0 1 -2 2h-12c-1.11 0-2-.9-2-2v-16c0-1.11.89-2 2-2m9 16v-2h-9v2h9m3-4v-2h-12v2h12z" fill="#757575" style="fill:#757575"/><g transform="matrix(.57384 0 0 .57384 11.066 10.911)"><path d="m1.791 3.6914 10.209 17.619 10.209-17.533v-.085938h-3.9688l-6.1816 10.615-6.1523-10.615z" style="fill:#e97d57"/><path d="m5.9072 3.6914 6.1521 10.617 6.1809-10.617h-3.7228l-2.4337 4.1783-2.4226-4.1783z" style="fill:#35495e"/></g></svg>

images/svg/dark/systemverilog.svg

@@ -1 +1 @@
-<svg version="1.1" viewBox="0 0 24 24" xmlns="http://www.w3.org/2000/svg"><path d="m13 9h5.5l-5.5-5.5v5.5m-7-7h8l6 6v12a2 2 0 0 1 -2 2h-12c-1.11 0-2-.9-2-2v-16c0-1.11.89-2 2-2m9 16v-2h-9v2h9m3-4v-2h-12v2h12z" fill="#757575" style="fill:#757575"/><g transform="matrix(.57384 0 0 .57384 11.066 10.911)"><path d="m1.791 3.6914 10.209 17.619 10.209-17.533v-.085938h-3.9688l-6.1816 10.615-6.1523-10.615z" style="fill:#e97d57"/><path d="m5.9072 3.6914 6.1521 10.617 6.1809-10.617h-3.7228l-2.4337 4.1783-2.4226-4.1783z" style="fill:#35495e"/></g></svg>
+<?xml version="1.0" standalone="no"?><!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd"><svg t="1700394770615" class="icon" viewBox="0 0 1024 1024" version="1.1" xmlns="http://www.w3.org/2000/svg" p-id="1667" width="200" height="200" xmlns:xlink="http://www.w3.org/1999/xlink"><path d="M352 48c0-26.6-21.4-48-48-48s-48 21.4-48 48v80c-70.6 0-128 57.4-128 128H48c-26.6 0-48 21.4-48 48s21.4 48 48 48h80v112H48c-26.6 0-48 21.4-48 48s21.4 48 48 48h80v112H48c-26.6 0-48 21.4-48 48s21.4 48 48 48h80c0 70.6 57.4 128 128 128v80c0 26.6 21.4 48 48 48s48-21.4 48-48v-80h112v80c0 26.6 21.4 48 48 48s48-21.4 48-48v-80h112v80c0 26.6 21.4 48 48 48s48-21.4 48-48v-80c70.6 0 128-57.4 128-128h80c26.6 0 48-21.4 48-48s-21.4-48-48-48h-80v-112h80c26.6 0 48-21.4 48-48s-21.4-48-48-48h-80v-112h80c26.6 0 48-21.4 48-48s-21.4-48-48-48h-80c0-70.6-57.4-128-128-128V48c0-26.6-21.4-48-48-48s-48 21.4-48 48v80h-112V48c0-26.6-21.4-48-48-48s-48 21.4-48 48v80h-112V48z m-32 208h384c35.4 0 64 28.6 64 64v384c0 35.4-28.6 64-64 64H320c-35.4 0-64-28.6-64-64V320c0-35.4 28.6-64 64-64z m384 64H320v384h384V320z" p-id="1668" fill="#34D1B2"></path></svg>

images/svg/light/bd.svg

@@ -0,0 +1 @@
+<svg t="1700403751622" class="icon" viewBox="0 0 1024 1024" version="1.1" xmlns="http://www.w3.org/2000/svg" p-id="4863" width="200" height="200"><path d="M64 764.330667a85.333333 85.333333 0 0 1 0-120.661334L643.669333 64a85.333333 85.333333 0 0 1 120.661334 0L938.666667 238.336a85.333333 85.333333 0 0 1 0 120.661333L358.997333 938.666667a85.333333 85.333333 0 0 1-120.661333 0L64 764.330667z m640-640L124.330667 704 298.666667 878.336 878.336 298.666667 704 124.330667zM392.832 222.165333a42.666667 42.666667 0 0 0 0-60.330666L294.997333 64a85.333333 85.333333 0 0 0-120.661333 0L64 174.336a85.333333 85.333333 0 0 0 0 120.661333l97.834667 97.834667a42.666667 42.666667 0 0 0 60.330666-60.330667L124.330667 234.666667 234.666667 124.330667l97.834666 97.834666a42.666667 42.666667 0 0 0 60.330667 0z m387.669333 448l94.165334 94.165334V874.666667h-110.336l-94.165334-94.165334a42.666667 42.666667 0 0 0-60.330666 60.330667l94.165333 94.165333a85.333333 85.333333 0 0 0 60.330667 25.002667H874.666667a85.333333 85.333333 0 0 0 85.333333-85.333333v-110.336a85.333333 85.333333 0 0 0-25.002667-60.330667l-94.165333-94.165333a42.666667 42.666667 0 0 0-60.330667 60.330666z" fill="#d4237a" p-id="4864"></path><path d="M210.304 512a42.666667 42.666667 0 0 1 60.330667 0l60.330666 60.330667a42.666667 42.666667 0 0 1-60.330666 60.373333L210.346667 572.288a42.666667 42.666667 0 0 1 0-60.330667zM361.130667 361.130667a42.666667 42.666667 0 0 1 60.373333 0l60.330667 60.373333a42.666667 42.666667 0 0 1-60.330667 60.330667L361.130667 421.504a42.666667 42.666667 0 0 1 0-60.373333zM512 210.304a42.666667 42.666667 0 0 1 60.330667 0l60.330666 60.330667a42.666667 42.666667 0 0 1-60.330666 60.330666L512 270.634667a42.666667 42.666667 0 0 1 0-60.330667z" fill="#d4237a" p-id="4865"></path></svg>

images/svg/light/systemverilog.svg

@@ -0,0 +1 @@
+<?xml version="1.0" standalone="no"?><!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN" "http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd"><svg t="1700394770615" class="icon" viewBox="0 0 1024 1024" version="1.1" xmlns="http://www.w3.org/2000/svg" p-id="1667" width="200" height="200" xmlns:xlink="http://www.w3.org/1999/xlink"><path d="M352 48c0-26.6-21.4-48-48-48s-48 21.4-48 48v80c-70.6 0-128 57.4-128 128H48c-26.6 0-48 21.4-48 48s21.4 48 48 48h80v112H48c-26.6 0-48 21.4-48 48s21.4 48 48 48h80v112H48c-26.6 0-48 21.4-48 48s21.4 48 48 48h80c0 70.6 57.4 128 128 128v80c0 26.6 21.4 48 48 48s48-21.4 48-48v-80h112v80c0 26.6 21.4 48 48 48s48-21.4 48-48v-80h112v80c0 26.6 21.4 48 48 48s48-21.4 48-48v-80c70.6 0 128-57.4 128-128h80c26.6 0 48-21.4 48-48s-21.4-48-48-48h-80v-112h80c26.6 0 48-21.4 48-48s-21.4-48-48-48h-80v-112h80c26.6 0 48-21.4 48-48s-21.4-48-48-48h-80c0-70.6-57.4-128-128-128V48c0-26.6-21.4-48-48-48s-48 21.4-48 48v80h-112V48c0-26.6-21.4-48-48-48s-48 21.4-48 48v80h-112V48z m-32 208h384c35.4 0 64 28.6 64 64v384c0 35.4-28.6 64-64 64H320c-35.4 0-64-28.6-64-64V320c0-35.4 28.6-64 64-64z m384 64H320v384h384V320z" p-id="1668" fill="#34D1B2"></path></svg>

package.json

@@ -452,6 +452,10 @@
 				"title": "%digital-ide.lsp.tool.transformOldPropertyFile.title%",
 				"category": "Digital-IDE"
 			},
+            {
+                "command": "digital-ide.lsp.verilog.linter",
+                "title": "%digital-ide.lsp.verilog.linter.title%"
+            },
 			{
 				"command": "digital-ide.vhdl2vlog",
 				"title": "%digital-ide.vhdl2vlog.title%",
@@ -685,13 +689,22 @@
 					".xdc",
 					".fdc"
 				],
-				"configuration": "./config/tcl.configuration.json"
+				"configuration": "./config/tcl.configuration.json",
+                "icon": {
+                    "dark": "./images/svg/dark/tcl.svg",
+                    "light": "./images/svg/light/tcl.svg"
+                }
 			},
 			{
 				"id": "bd",
 				"extensions": [
 					".bd"
-				]
+				],
+                "configuration": "./config/bd.configuration.json",
+                "icon": {
+                    "dark": "./images/svg/dark/bd.svg",
+                    "light": "./images/svg/light/bd.svg"
+                }
 			},
 			{
 				"id": "vhdl",
@@ -705,7 +718,11 @@
 					".vho",
 					".vht"
 				],
-				"configuration": "./config/vhdl.configuration.json"
+				"configuration": "./config/vhdl.configuration.json",
+                "icon": {
+                    "dark": "./images/svg/dark/vhdl.svg",
+                    "light": "./images/svg/light/vhdl.svg"
+                }
 			},
 			{
 				"id": "verilog",
@@ -719,7 +736,11 @@
 					".vh",
 					".vl"
 				],
-				"configuration": "./config/verilog.configuration.json"
+				"configuration": "./config/verilog.configuration.json",
+                "icon": {
+                    "dark": "./images/svg/dark/verilog.svg",
+                    "light": "./images/svg/light/verilog.svg"
+                }
 			},
 			{
 				"id": "systemverilog",
@@ -731,7 +752,11 @@
 					".sv",
 					".SV"
 				],
-				"configuration": "./config/systemverilog.configuration.json"
+				"configuration": "./config/systemverilog.configuration.json",
+                "icon": {
+                    "dark": "./images/svg/dark/systemverilog.svg",
+                    "light": "./images/svg/light/systemverilog.svg"
+                }
 			},
 			{
 				"id": "arm",

snippets/tcl.json

@@ -135,8 +135,33 @@
 	"tk_messageBox": {
 		"prefix": "tk_messageBox",
 		"body": [
-			"tk_messageBox ${-message msg}"
+			"tk_messageBox ${0:message}"
 		],
 		"description": "Message Box"
+	},
+    "set_property": {
+		"prefix": "set_property",
+        "body": [
+            "set_property ${1:property_name} ${2:value}"
+        ],
+        "description": "set property"
+    },
+    "create_clock": {
+		"prefix": "create_clock",
+        "body": [
+            "create_clock ${1:signal_name} ${2:clock_name} ${3:frequency} ${4:uncertainty}"
+        ]
+    },
+    "set_initial_state": {
+        "prefix": "set_initial_state",
+        "body": [
+            "set_initial_5state ${1:initial_state}"
+        ]
+    },
+    "connect_port": {
+        "prefix": "connect_port",
+        "body": [
+            "connect_port ${1:source_port} ${2:sink_port}"
+        ]
     }
 }

src/function/index.ts

@@ -60,6 +60,7 @@ function registerLsp(context: vscode.ExtensionContext) {
     const vlogSelector: vscode.DocumentSelector = {scheme: 'file', language: 'verilog'};
     const svlogSelector: vscode.DocumentSelector = {scheme: 'file', language: 'systemverilog'};
     const vhdlSelector: vscode.DocumentSelector = {scheme: 'file', language: 'vhdl'};
+    const tclSelector: vscode.DocumentSelector = {scheme: 'file', language: 'tcl'};
 
     // formatter
     vscode.languages.registerDocumentFormattingEditProvider(vlogSelector, lspFormatter.hdlFormatterProvider);
@@ -79,10 +80,14 @@ function registerLsp(context: vscode.ExtensionContext) {
     vscode.languages.registerCompletionItemProvider(vlogSelector, lspCompletion.vlogCompletionProvider);
     vscode.languages.registerDocumentSemanticTokensProvider(vlogSelector, lspDocSemantic.vlogDocSenmanticProvider, lspDocSemantic.vlogLegend);
 
+    // tcl lsp
+    vscode.languages.registerCompletionItemProvider(tclSelector, lspCompletion.tclCompletionProvider);
+
     lspLinter.vlogLinter.initialise();
     lspCore.hdlSymbolStorage.initialise();
     
     // vhdl lsp
+    
 }
 
 

src/function/lsp/completion/index.ts

@@ -1,8 +1,10 @@
 import { vlogCompletionProvider, vlogIncludeCompletionProvider, vlogMacroCompletionProvider, vlogPositionPortProvider } from './vlog';
+import { tclCompletionProvider } from './tcl';
 
 export {
     vlogCompletionProvider,
     vlogIncludeCompletionProvider,
     vlogMacroCompletionProvider,
-    vlogPositionPortProvider
+    vlogPositionPortProvider,
+    tclCompletionProvider
 };

src/function/lsp/completion/tcl.ts

@@ -0,0 +1,42 @@
+import * as vscode from 'vscode';
+
+import { tclKeyword } from '../util/keyword';
+import { MainOutput } from '../../../global';
+
+
+class TCLCompletionProvider implements vscode.CompletionItemProvider {
+    keywordsCompletionItems: vscode.CompletionItem[] | undefined;
+    constructor() {
+        this.keywordsCompletionItems = this.provideKeywords();
+        MainOutput.report('lsp for tcl is ready');
+    }
+    public provideCompletionItems(document: vscode.TextDocument, position: vscode.Position, token: vscode.CancellationToken, context: vscode.CompletionContext): vscode.ProviderResult<vscode.CompletionItem[] | vscode.CompletionList<vscode.CompletionItem>> {        
+        try {
+            const items = this.provideKeywords();
+            return items;
+        } catch (err) {
+            console.log(err);
+        }
+    }
+
+    private provideKeywords(): vscode.CompletionItem[] {
+        if (this.keywordsCompletionItems === undefined) {
+            const keywords: vscode.CompletionItem[] = [];
+            for (const tcl of tclKeyword.keys()) {
+                const item = new vscode.CompletionItem(tcl);
+                item.kind = vscode.CompletionItemKind.Keyword;
+                keywords.push(item);
+            }
+            this.keywordsCompletionItems = keywords;
+            MainOutput.report('tcl lsp is ready');
+        }
+        
+        return this.keywordsCompletionItems;
+    }
+}
+
+const tclCompletionProvider = new TCLCompletionProvider();
+
+export {
+    tclCompletionProvider
+};

src/function/lsp/util/keyword.ts

@@ -123,9 +123,40 @@ const systemverilogKeyword = new Keywords([
 );
 
 
+const tclKeyword = new Keywords([
+    'create_clock',  
+    'set_clock_uncertainty',  
+    'create_reset',  
+    'set_initial_state',  
+    'create_sync',  
+    'create_source_sync',  
+    'create_launch_bar',  
+    'connect_port',  
+    'set_signal_type',  
+    'set_edge_detect',  
+    'set_delay',  
+    'create_generated_clock',  
+    'create_programmable_logic',  
+    'create_lookup_table',  
+    'create_shift_register',  
+    'create_counter',  
+    'create_multiplier',  
+    'create_divider',  
+    'create_comparator',  
+    'create_register',  
+    'create_flop',  
+    'connect_power_pin',  
+    'connect_ground_pin',
+    'set_property'
+],
+[],
+[]
+);
+
 
 export {
     vlogKeyword,
     vhdlKeyword,
-    systemverilogKeyword
+    systemverilogKeyword,
+    tclKeyword
 };