#add translator
This commit is contained in:
parent
10c73206a4
commit
190eb358ed
47
package.json
47
package.json
@ -419,7 +419,11 @@
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{
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{
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"command": "digital-ide.vhdl2vlog",
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"command": "digital-ide.vhdl2vlog",
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"title": "%digital-ide.vhdl2vlog.title%",
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"title": "%digital-ide.vhdl2vlog.title%",
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"category": "Digital-IDE"
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"category": "Digital-IDE",
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"icon": {
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"light": "images/svg/light/translate.svg",
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"dark": "images/svg/dark/translate.svg"
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}
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}
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}
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],
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],
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"menus": {
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"menus": {
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@ -477,8 +481,45 @@
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"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
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"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
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"command": "digital-ide.hdlDoc.showWebview",
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"command": "digital-ide.hdlDoc.showWebview",
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"group": "navigation@4"
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"group": "navigation@4"
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}
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},
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]
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{
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"when": "resourceLangId == vhdl",
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"command": "digital-ide.vhdl2vlog",
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"group": "navigation@5"
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}
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],
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"editor/context": [
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{
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"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
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"command": "digital-ide.pl.setSrcTop",
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"group": "navigation@1"
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},
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{
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"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
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"command": "digital-ide.pl.setSimTop",
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"group": "navigation@2"
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},
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{
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"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
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"command": "digital-ide.tool.instance",
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"group": "navigation@3"
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},
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{
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"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
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"command": "digital-ide.tool.testbench",
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"group": "navigation@4"
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},
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{
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"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
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"command": "digital-ide.tool.icarus.simulateFile",
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"group": "navigation@5"
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},
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{
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"when": "resourceLangId == vhdl",
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"command": "digital-ide.vhdl2vlog",
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"group": "navigation@8"
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}
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]
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},
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},
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"viewsContainers": {
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"viewsContainers": {
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"activitybar": [
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"activitybar": [
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@ -1,7 +1,21 @@
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/* eslint-disable @typescript-eslint/naming-convention */
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/* eslint-disable @typescript-eslint/naming-convention */
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const fs = require('fs');
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const fs = require('fs');
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const vscode = require('vscode');
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const vscode = require('vscode');
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const fspath = require('path');
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const vhd2vl = require("./vhd2vlog");
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const vhd2vl = require("./vhd2vlog");
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const formatter = require('../formatter');
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/**
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*
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* @param {string} path
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* @return {string}
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*/
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function getFileName(path) {
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const fileName = fspath.basename(path);
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const names = fileName.split('.');
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names.pop();
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return names.join('.');
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}
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/**
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/**
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*
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*
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@ -10,30 +24,42 @@ const vhd2vl = require("./vhd2vlog");
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*/
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*/
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async function vhdl2vlog(uri) {
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async function vhdl2vlog(uri) {
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const path = uri.fsPath.replace(/\\/g, '/');
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const path = uri.fsPath.replace(/\\/g, '/');
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const fileName = getFileName(path);
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const Module = await vhd2vl();
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const Module = await vhd2vl();
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const content = fs.readFileSync(path, "utf-8");
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let content = fs.readFileSync(path, "utf-8");
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const status = Module.ccall('vhdlParse', '', ['string'], [content]);
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const status = Module.ccall('vhdlParse', '', ['string'], [content]);
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if (!status) {
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if (!status) {
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content = Module.ccall('getVlog', 'string', ['string'], []);
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content = Module.ccall('getVlog', 'string', ['string'], []);
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vscode.window.showSaveDialog({
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// format
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filters: {
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content = await formatter.hdlFormatterProvider.vlogFormatter.format_from_code(content);
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verilog: ["v", "V", "vh", "vl"], // 文件类型过滤
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},
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const folderPath = fspath.dirname(path);
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}).then(fileInfos => {
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const defaultSaveUri = new vscode.Uri('file', '', folderPath + '/' + fileName + '.v', '', '');
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let path_full = fileInfos === null || fileInfos === void 0 ? void 0 : fileInfos.path;
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console.log(defaultSaveUri);
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if (path_full !== undefined) {
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const vscodeDialogConfig = {
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if (path_full[0] === '/' && require('os').platform() === 'win32') {
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title: 'save the verilog code',
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path_full = path_full.substring(1);
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defaultUri: defaultSaveUri,
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}
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verilog: ["v", "V", "vh", "vl"]
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fs.writeFileSync(path_full, content, "utf-8");
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};
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vscode.window.showInformationMessage("translate successfully");
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const fileInfos = await vscode.window.showSaveDialog(vscodeDialogConfig);
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const options = {
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preview: false,
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if (fileInfos && fileInfos.path) {
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viewColumn: vscode.ViewColumn.Two
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let savePath = fileInfos.path;
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};
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console.log(savePath);
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vscode.window.showTextDocument(vscode.Uri.file(path_full), options);
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if (savePath[0] === '/' && require('os').platform() === 'win32') {
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savePath = savePath.substring(1);
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}
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}
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});
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fs.writeFileSync(savePath, content, "utf-8");
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vscode.window.showInformationMessage("translate successfully");
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const options = {
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preview: false,
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viewColumn: vscode.ViewColumn.Two
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};
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vscode.window.showTextDocument(vscode.Uri.file(savePath), options);
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}
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} else {
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} else {
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const error = Module.ccall('getErr', 'string', ['string'], []);
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const error = Module.ccall('getErr', 'string', ['string'], []);
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vscode.window.showErrorMessage(error);
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vscode.window.showErrorMessage(error);
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16
src/test/user/src/hello.v
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16
src/test/user/src/hello.v
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@ -0,0 +1,16 @@
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// VHDL code for a 2-to-1 multiplexer
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module mux2to1(
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input wire a,
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input wire b,
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input wire sel,
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output wire outp
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);
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assign outp = sel == 1'b0 ? a : b;
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endmodule
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14
src/test/user/src/hello.vhd
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14
src/test/user/src/hello.vhd
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-- VHDL code for a 2-to-1 multiplexer
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library IEEE;
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use IEEE.std_logic_1164.all;
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entity mux2to1 is
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port(a, b : in std_logic;
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sel : in std_logic;
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outp : out std_logic);
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end mux2to1;
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architecture behavioral of mux2to1 is
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begin
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outp <= a when sel = '0' else b;
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end behavioral;
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