add vhdl std lib

.gitignore

@@ -16,4 +16,4 @@ resources/hdlParser/parser.js
 resources/hdlParser/parser.wasm
 resources/dide-viewer/view/*
 resources/dide-lsp/server/*
-resources/dide-lsp/static/*
+resources/dide-lsp/static/*

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_float_types.vhdl

@@ -0,0 +1,61 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this 
+-- source file may be used and distributed without restriction. 
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission 
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+--
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file 
+-- shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+--   Title      :  Fixed Point and Floating Point types package
+--
+--   Library   :  This package shall be compiled into a library 
+--                symbolically named IEEE. 
+--
+--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
+--
+--   Purpose   :  Definitions for use in fixed point and floating point
+--                arithmetic packages
+--
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+package fixed_float_types is
+
+  -- Types used for generics of fixed_generic_pkg
+  
+  type fixed_round_style_type is (fixed_round, fixed_truncate);
+  
+  type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
+
+  -- Type used for generics of float_generic_pkg
+
+  -- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
+  -- and FE_TOWARDZERO floating point rounding macros.
+
+  type round_type is (round_nearest,    -- Default, nearest LSB '0'
+                      round_inf,        -- Round toward positive infinity
+                      round_neginf,     -- Round toward negative infinity
+                      round_zero);      -- Round toward zero (truncate)
+
+end package fixed_float_types;

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/fixed_pkg.vhdl

@@ -0,0 +1,51 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this 
+-- source file may be used and distributed without restriction. 
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission 
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+--
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file 
+-- shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+--   Title     :  Fixed-point package (Instantiated package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This packages defines basic binary fixed point
+--             :  arithmetic functions
+--             :
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+library IEEE;
+
+package fixed_pkg is new IEEE.fixed_generic_pkg
+  generic map (
+    fixed_round_style    => IEEE.fixed_float_types.fixed_round,
+    fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
+    fixed_guard_bits     => 3,
+    no_warning           => false
+    );

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/float_pkg.vhdl

@@ -0,0 +1,55 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this 
+-- source file may be used and distributed without restriction. 
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission 
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+--
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file 
+-- shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+--   Title     :  Floating-point package (Instantiated package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This packages defines basic binary floating point
+--             :  arithmetic functions
+--             :
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+library ieee;
+
+package float_pkg is new IEEE.float_generic_pkg
+  generic map (
+    float_exponent_width => 8,    -- float32'high
+    float_fraction_width => 23,   -- -float32'low
+    float_round_style    => IEEE.fixed_float_types.round_nearest,  -- round nearest algorithm
+    float_denormalize    => true,  -- Use IEEE extended floating
+    float_check_error    => true,  -- Turn on NAN and overflow processing
+    float_guard_bits     => 3,     -- number of guard bits
+    no_warning           => false, -- show warnings
+    fixed_pkg            => IEEE.fixed_pkg
+    );

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/math_real.vhdl

@@ -0,0 +1,658 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this 
+-- source file may be used and distributed without restriction. 
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission 
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+--
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file 
+-- shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+--   Title     :  Standard VHDL Mathematical Packages
+--             :  (MATH_REAL package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  IEEE DASC VHDL Mathematical Packages Working Group
+--             :
+--   Purpose   :  This package defines a standard for designers to use in
+--             :  describing VHDL models that make use of common REAL
+--             :  constants and common REAL elementary mathematical
+--             :  functions.
+--             :
+--   Limitation:  The values generated by the functions in this package
+--             :  may vary from platform to platform, and the precision
+--             :  of results is only guaranteed to be the minimum required
+--             :  by IEEE Std 1076-2008.
+--             :
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+package MATH_REAL is
+  constant CopyRightNotice : STRING
+    := "Copyright 2008 IEEE. All rights reserved.";
+
+  --
+  -- Constant Definitions
+  --
+  constant MATH_E             : REAL := 2.71828_18284_59045_23536;
+                                        -- Value of e
+  constant MATH_1_OVER_E      : REAL := 0.36787_94411_71442_32160;
+                                        -- Value of 1/e
+  constant MATH_PI            : REAL := 3.14159_26535_89793_23846;
+                                        -- Value of pi
+  constant MATH_2_PI          : REAL := 6.28318_53071_79586_47693;
+                                        -- Value of 2*pi
+  constant MATH_1_OVER_PI     : REAL := 0.31830_98861_83790_67154;
+                                        -- Value of 1/pi
+  constant MATH_PI_OVER_2     : REAL := 1.57079_63267_94896_61923;
+                                        -- Value of pi/2
+  constant MATH_PI_OVER_3     : REAL := 1.04719_75511_96597_74615;
+                                        -- Value of pi/3
+  constant MATH_PI_OVER_4     : REAL := 0.78539_81633_97448_30962;
+                                        -- Value of pi/4
+  constant MATH_3_PI_OVER_2   : REAL := 4.71238_89803_84689_85769;
+                                        -- Value 3*pi/2
+  constant MATH_LOG_OF_2      : REAL := 0.69314_71805_59945_30942;
+                                        -- Natural log of 2
+  constant MATH_LOG_OF_10     : REAL := 2.30258_50929_94045_68402;
+                                        -- Natural log of 10
+  constant MATH_LOG2_OF_E     : REAL := 1.44269_50408_88963_4074;
+                                        -- Log base 2 of e
+  constant MATH_LOG10_OF_E    : REAL := 0.43429_44819_03251_82765;
+                                        -- Log base 10 of e
+  constant MATH_SQRT_2        : REAL := 1.41421_35623_73095_04880;
+                                        -- square root of 2
+  constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
+                                        -- square root of 1/2
+  constant MATH_SQRT_PI       : REAL := 1.77245_38509_05516_02730;
+                                        -- square root of pi
+  constant MATH_DEG_TO_RAD    : REAL := 0.01745_32925_19943_29577;
+  -- Conversion factor from degree to radian
+  constant MATH_RAD_TO_DEG    : REAL := 57.29577_95130_82320_87680;
+  -- Conversion factor from radian to degree
+
+  --
+  -- Function Declarations
+  --
+  function SIGN (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
+  -- Special values:
+  --         None
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         ABS(SIGN(X)) <= 1.0
+  -- Notes:
+  --         None
+
+  function CEIL (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns smallest INTEGER value (as REAL) not less than X
+  -- Special values:
+  --         None
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         CEIL(X) is mathematically unbounded
+  -- Notes:
+  --         a) Implementations have to support at least the domain
+  --                ABS(X) < REAL(INTEGER'HIGH)
+
+  function FLOOR (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns largest INTEGER value (as REAL) not greater than X
+  -- Special values:
+  --         FLOOR(0.0) = 0.0
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         FLOOR(X) is mathematically unbounded
+  -- Notes:
+  --         a) Implementations have to support at least the domain
+  --                ABS(X) < REAL(INTEGER'HIGH)
+
+  function ROUND (X : in REAL) return REAL;
+  -- Purpose:
+  --         Rounds X to the nearest integer value (as real). If X is
+  --         halfway between two integers, rounding is away from 0.0
+  -- Special values:
+  --         ROUND(0.0) = 0.0
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         ROUND(X) is mathematically unbounded
+  -- Notes:
+  --         a) Implementations have to support at least the domain
+  --                ABS(X) < REAL(INTEGER'HIGH)
+
+  function TRUNC (X : in REAL) return REAL;
+  -- Purpose:
+  --         Truncates X towards 0.0 and returns truncated value
+  -- Special values:
+  --         TRUNC(0.0) = 0.0
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         TRUNC(X) is mathematically unbounded
+  -- Notes:
+  --         a) Implementations have to support at least the domain
+  --                ABS(X) < REAL(INTEGER'HIGH)
+
+  function "MOD" (X, Y : in REAL) return REAL;
+  -- Purpose:
+  --         Returns floating point modulus of X/Y, with the same sign as
+  --         Y, and absolute value less than the absolute value of Y, and
+  --         for some INTEGER value N the result satisfies the relation
+  --         X = Y*N + MOD(X,Y)
+  -- Special values:
+  --         None
+  -- Domain:
+  --         X in REAL; Y in REAL and Y /= 0.0
+  -- Error conditions:
+  --         Error if Y = 0.0
+  -- Range:
+  --         ABS(MOD(X,Y)) < ABS(Y)
+  -- Notes:
+  --         None
+
+  function REALMAX (X, Y : in REAL) return REAL;
+  -- Purpose:
+  --         Returns the algebraically larger of X and Y
+  -- Special values:
+  --         REALMAX(X,Y) = X when X = Y
+  -- Domain:
+  --         X in REAL; Y in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         REALMAX(X,Y) is mathematically unbounded
+  -- Notes:
+  --         None
+
+  function REALMIN (X, Y : in REAL) return REAL;
+  -- Purpose:
+  --         Returns the algebraically smaller of X and Y
+  -- Special values:
+  --         REALMIN(X,Y) = X when X = Y
+  -- Domain:
+  --         X in REAL; Y in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         REALMIN(X,Y) is mathematically unbounded
+  -- Notes:
+  --         None
+
+  procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
+  -- Purpose:
+  --         Returns, in X, a pseudo-random number with uniform
+  --         distribution in the open interval (0.0, 1.0).
+  -- Special values:
+  --         None
+  -- Domain:
+  --         1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
+  -- Error conditions:
+  --         Error if SEED1 or SEED2 outside of valid domain
+  -- Range:
+  --         0.0 < X < 1.0
+  -- Notes:
+  --         a) The semantics for this function are described by the
+  --            algorithm published by Pierre L'Ecuyer in "Communications
+  --            of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
+  --            The algorithm is based on the combination of two
+  --            multiplicative linear congruential generators for 32-bit
+  --            platforms.
+  --
+  --         b) Before the first call to UNIFORM, the seed values
+  --            (SEED1, SEED2) have to be initialized to values in the range
+  --            [1, 2147483562] and [1, 2147483398] respectively.  The
+  --            seed values are modified after each call to UNIFORM.
+  --
+  --         c) This random number generator is portable for 32-bit
+  --            computers, and it has a period of ~2.30584*(10**18) for each
+  --            set of seed values.
+  --
+  --         d) For information on spectral tests for the algorithm, refer
+  --            to the L'Ecuyer article.
+
+  function SQRT (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns square root of X
+  -- Special values:
+  --         SQRT(0.0) = 0.0
+  --         SQRT(1.0) = 1.0
+  -- Domain:
+  --         X >= 0.0
+  -- Error conditions:
+  --         Error if X < 0.0
+  -- Range:
+  --         SQRT(X) >= 0.0
+  -- Notes:
+  --         a) The upper bound of the reachable range of SQRT is
+  --            approximately given by:
+  --                SQRT(X) <= SQRT(REAL'HIGH)
+
+  function CBRT (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns cube root of X
+  -- Special values:
+  --         CBRT(0.0) = 0.0
+  --         CBRT(1.0) = 1.0
+  --         CBRT(-1.0) = -1.0
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         CBRT(X) is mathematically unbounded
+  -- Notes:
+  --         a) The reachable range of CBRT is approximately given by:
+  --                ABS(CBRT(X)) <= CBRT(REAL'HIGH)
+
+  function "**" (X : in INTEGER; Y : in REAL) return REAL;
+  -- Purpose:
+  --         Returns Y power of X ==>  X**Y
+  -- Special values:
+  --         X**0.0 = 1.0; X /= 0
+  --         0**Y = 0.0; Y > 0.0
+  --         X**1.0 = REAL(X); X >= 0
+  --         1**Y = 1.0
+  -- Domain:
+  --         X > 0
+  --         X = 0 for Y > 0.0
+  --         X < 0 for Y = 0.0
+  -- Error conditions:
+  --         Error if X < 0 and Y /= 0.0
+  --         Error if X = 0 and Y <= 0.0
+  -- Range:
+  --         X**Y >= 0.0
+  -- Notes:
+  --         a) The upper bound of the reachable range for "**" is
+  --            approximately given by:
+  --                X**Y <= REAL'HIGH
+
+  function "**" (X : in REAL; Y : in REAL) return REAL;
+  -- Purpose:
+  --         Returns Y power of X ==>  X**Y
+  -- Special values:
+  --         X**0.0 = 1.0; X /= 0.0
+  --         0.0**Y = 0.0; Y > 0.0
+  --         X**1.0 = X; X >= 0.0
+  --         1.0**Y = 1.0
+  -- Domain:
+  --         X > 0.0
+  --         X = 0.0 for Y > 0.0
+  --         X < 0.0 for Y = 0.0
+  -- Error conditions:
+  --         Error if X < 0.0 and Y /= 0.0
+  --         Error if X = 0.0 and Y <= 0.0
+  -- Range:
+  --         X**Y >= 0.0
+  -- Notes:
+  --         a) The upper bound of the reachable range for "**" is
+  --            approximately given by:
+  --                X**Y <= REAL'HIGH
+
+  function EXP (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns e**X; where e = MATH_E
+  -- Special values:
+  --         EXP(0.0) = 1.0
+  --         EXP(1.0) = MATH_E
+  --         EXP(-1.0) = MATH_1_OVER_E
+  --         EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
+  -- Domain:
+  --         X in REAL such that EXP(X) <= REAL'HIGH
+  -- Error conditions:
+  --         Error if X > LOG(REAL'HIGH)
+  -- Range:
+  --         EXP(X) >= 0.0
+  -- Notes:
+  --         a) The usable domain of EXP is approximately given by:
+  --                X <= LOG(REAL'HIGH)
+
+  function LOG (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns natural logarithm of X
+  -- Special values:
+  --         LOG(1.0) = 0.0
+  --         LOG(MATH_E) = 1.0
+  -- Domain:
+  --         X > 0.0
+  -- Error conditions:
+  --         Error if X <= 0.0
+  -- Range:
+  --         LOG(X) is mathematically unbounded
+  -- Notes:
+  --         a) The reachable range of LOG is approximately given by:
+  --                LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
+
+  function LOG2 (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns logarithm base 2 of X
+  -- Special values:
+  --         LOG2(1.0) = 0.0
+  --         LOG2(2.0) = 1.0
+  -- Domain:
+  --         X > 0.0
+  -- Error conditions:
+  --         Error if X <= 0.0
+  -- Range:
+  --         LOG2(X) is mathematically unbounded
+  -- Notes:
+  --         a) The reachable range of LOG2 is approximately given by:
+  --                LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
+
+  function LOG10 (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns logarithm base 10 of X
+  -- Special values:
+  --         LOG10(1.0) = 0.0
+  --         LOG10(10.0) = 1.0
+  -- Domain:
+  --         X > 0.0
+  -- Error conditions:
+  --         Error if X <= 0.0
+  -- Range:
+  --         LOG10(X) is mathematically unbounded
+  -- Notes:
+  --         a) The reachable range of LOG10 is approximately given by:
+  --                LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
+
+  function LOG (X : in REAL; BASE : in REAL) return REAL;
+  -- Purpose:
+  --         Returns logarithm base BASE of X
+  -- Special values:
+  --         LOG(1.0, BASE) = 0.0
+  --         LOG(BASE, BASE) = 1.0
+  -- Domain:
+  --         X > 0.0
+  --         BASE > 0.0
+  --         BASE /= 1.0
+  -- Error conditions:
+  --         Error if X <= 0.0
+  --         Error if BASE <= 0.0
+  --         Error if BASE = 1.0
+  -- Range:
+  --         LOG(X, BASE) is mathematically unbounded
+  -- Notes:
+  --         a) When BASE > 1.0, the reachable range of LOG is
+  --            approximately given by:
+  --                LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
+  --         b) When 0.0 < BASE < 1.0, the reachable range of LOG is
+  --            approximately given by:
+  --                LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
+
+  function SIN (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns sine of X; X in radians
+  -- Special values:
+  --         SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+  --         SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
+  --                                                           INTEGER
+  --         SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
+  --                                                           INTEGER
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         ABS(SIN(X)) <= 1.0
+  -- Notes:
+  --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+  function COS (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns cosine of X; X in radians
+  -- Special values:
+  --         COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
+  --                                                            INTEGER
+  --         COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
+  --         COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         ABS(COS(X)) <= 1.0
+  -- Notes:
+  --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+  function TAN (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns tangent of X; X in radians
+  -- Special values:
+  --         TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
+  -- Domain:
+  --         X in REAL and
+  --         X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
+  -- Error conditions:
+  --         Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
+  --                                                           INTEGER
+  -- Range:
+  --         TAN(X) is mathematically unbounded
+  -- Notes:
+  --         a) For larger values of ABS(X), degraded accuracy is allowed.
+
+  function ARCSIN (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns inverse sine of X
+  -- Special values:
+  --         ARCSIN(0.0) = 0.0
+  --         ARCSIN(1.0) = MATH_PI_OVER_2
+  --         ARCSIN(-1.0) = -MATH_PI_OVER_2
+  -- Domain:
+  --         ABS(X) <= 1.0
+  -- Error conditions:
+  --         Error if ABS(X) > 1.0
+  -- Range:
+  --         ABS(ARCSIN(X) <= MATH_PI_OVER_2
+  -- Notes:
+  --         None
+
+  function ARCCOS (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns inverse cosine of X
+  -- Special values:
+  --         ARCCOS(1.0) = 0.0
+  --         ARCCOS(0.0) = MATH_PI_OVER_2
+  --         ARCCOS(-1.0) = MATH_PI
+  -- Domain:
+  --         ABS(X) <= 1.0
+  -- Error conditions:
+  --         Error if ABS(X) > 1.0
+  -- Range:
+  --         0.0 <= ARCCOS(X) <= MATH_PI
+  -- Notes:
+  --         None
+
+  function ARCTAN (Y : in REAL) return REAL;
+  -- Purpose:
+  --         Returns the value of the angle in radians of the point
+  --        (1.0, Y), which is in rectangular coordinates
+  -- Special values:
+  --         ARCTAN(0.0) = 0.0
+  -- Domain:
+  --         Y in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
+  -- Notes:
+  --         None
+
+  function ARCTAN (Y : in REAL; X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns the principal value of the angle in radians of
+  --         the point (X, Y), which is in rectangular coordinates
+  -- Special values:
+  --         ARCTAN(0.0, X) = 0.0 if X > 0.0
+  --         ARCTAN(0.0, X) = MATH_PI if X < 0.0
+  --         ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
+  --         ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
+  -- Domain:
+  --         Y in REAL
+  --         X in REAL, X /= 0.0 when Y = 0.0
+  -- Error conditions:
+  --         Error if X = 0.0 and Y = 0.0
+  -- Range:
+  --         -MATH_PI < ARCTAN(Y,X) <= MATH_PI
+  -- Notes:
+  --         None
+
+  function SINH (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns hyperbolic sine of X
+  -- Special values:
+  --         SINH(0.0) = 0.0
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         SINH(X) is mathematically unbounded
+  -- Notes:
+  --         a) The usable domain of SINH is approximately given by:
+  --                ABS(X) <= LOG(REAL'HIGH)
+
+
+  function COSH (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns hyperbolic cosine of X
+  -- Special values:
+  --         COSH(0.0) = 1.0
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         COSH(X) >= 1.0
+  -- Notes:
+  --         a) The usable domain of COSH is approximately given by:
+  --                ABS(X) <= LOG(REAL'HIGH)
+
+  function TANH (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns hyperbolic tangent of X
+  -- Special values:
+  --         TANH(0.0) = 0.0
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         ABS(TANH(X)) <= 1.0
+  -- Notes:
+  --         None
+
+  function ARCSINH (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns inverse hyperbolic sine of X
+  -- Special values:
+  --         ARCSINH(0.0) = 0.0
+  -- Domain:
+  --         X in REAL
+  -- Error conditions:
+  --         None
+  -- Range:
+  --         ARCSINH(X) is mathematically unbounded
+  -- Notes:
+  --         a) The reachable range of ARCSINH is approximately given by:
+  --                ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
+
+  function ARCCOSH (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns inverse hyperbolic cosine of X
+  -- Special values:
+  --         ARCCOSH(1.0) = 0.0
+  -- Domain:
+  --         X >= 1.0
+  -- Error conditions:
+  --         Error if X < 1.0
+  -- Range:
+  --         ARCCOSH(X) >= 0.0
+  -- Notes:
+  --         a) The upper bound of the reachable range of ARCCOSH is
+  --            approximately given by:   ARCCOSH(X) <= LOG(REAL'HIGH)
+
+  function ARCTANH (X : in REAL) return REAL;
+  -- Purpose:
+  --         Returns inverse hyperbolic tangent of X
+  -- Special values:
+  --         ARCTANH(0.0) = 0.0
+  -- Domain:
+  --         ABS(X) < 1.0
+  -- Error conditions:
+  --         Error if ABS(X) >= 1.0
+  -- Range:
+  --         ARCTANH(X) is mathematically unbounded
+  -- Notes:
+  --         a) The reachable range of ARCTANH is approximately given by:
+  --                ABS(ARCTANH(X)) < LOG(REAL'HIGH)
+    attribute foreign of MATH_REAL: package is "NO C code generation";
+    
+    attribute foreign of sign[real return real]:function is "ieee_math_real_sign";
+    attribute foreign of ceil[real return real]:function is "ieee_math_real_ceil";
+    attribute foreign of floor[real return real]:function is "ieee_math_real_floor";
+    attribute foreign of trunc[real return real]:function is "ieee_math_real_trunc";
+    attribute foreign of round[real return real]:function is "ieee_math_real_round";
+    attribute foreign of "MOD"[real, real return real]:function is "ieee_math_real_mod";
+    attribute foreign of realmax[real, real return real]:function is "ieee_math_real_realmax";
+    attribute foreign of realmin[real, real return real]:function is "ieee_math_real_realmin";
+    attribute foreign of uniform[positive, positive,real]:procedure is "ieee_math_real_uniform";
+    attribute foreign of sqrt[real return real]:function is "ieee_math_real_sqrt";
+    attribute foreign of cbrt[real return real]:function is "ieee_math_real_cbrt";
+    attribute foreign of "**"[integer, real return real]:function is "ieee_math_real_pow_int";
+    attribute foreign of "**"[real, real return real]:function is "ieee_math_real_pow_real";
+    attribute foreign of exp[real return real]:function is "ieee_math_real_exp";
+    attribute foreign of log[real return real]:function is "ieee_math_real_log";
+    attribute foreign of log2[real return real]:function is "ieee_math_real_log2";
+    attribute foreign of log10[real return real]:function is "ieee_math_real_log10";
+    attribute foreign of log[real, real return real]:function is "ieee_math_real_log_base";
+    attribute foreign of sin[real return real]:function is "ieee_math_real_sin";
+    attribute foreign of cos[real return real]:function is "ieee_math_real_cos";
+    attribute foreign of tan[real return real]:function is "ieee_math_real_tan";
+    attribute foreign of arcsin[real return real]:function is "ieee_math_real_arcsin";
+    attribute foreign of arccos[real return real]:function is "ieee_math_real_arccos";
+    attribute foreign of arctan[real return real]:function is "ieee_math_real_arctan";
+    attribute foreign of arctan[real,real return real]:function is "ieee_math_real_arctan2";
+    attribute foreign of sinh[real return real]:function is "ieee_math_real_sinh";
+    attribute foreign of cosh[real return real]:function is "ieee_math_real_cosh";
+    attribute foreign of tanh[real return real]:function is "ieee_math_real_tanh";
+    attribute foreign of arcsinh[real return real]:function is "ieee_math_real_arcsinh";
+    attribute foreign of arccosh[real return real]:function is "ieee_math_real_arccosh";
+    attribute foreign of arctanh[real return real]:function is "ieee_math_real_arctanh";
+
+end package MATH_REAL;

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit_unsigned-body.vhdl

@@ -0,0 +1,592 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this 
+-- source file may be used and distributed without restriction. 
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission 
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+--
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file 
+-- shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+--   Title     :  Standard VHDL Synthesis Packages
+--             :  (NUMERIC_BIT_UNSIGNED package body)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC, and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This package defines numeric types and arithmetic functions
+--             :  for use with synthesis tools. Values of type BIT_VECTOR
+--             :  are interpreted as unsigned numbers in vector form.
+--             :  The leftmost bit is treated as the most significant bit.
+--             :  This package contains overloaded arithmetic operators on
+--             :  the BIT_VECTOR type. The package also contains
+--             :  useful type conversions functions, clock detection
+--             :  functions, and other utility functions.
+--             :
+--             :  If any argument to a function is a null array, a null array
+--             :  is returned (exceptions, if any, are noted individually).
+--
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+library ieee;
+use ieee.numeric_bit.all;
+
+package body NUMERIC_BIT_UNSIGNED is
+
+  -- Id: A.3
+  function "+" (L, R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) + UNSIGNED(R));
+  end function "+";
+
+  -- Id: A.3R
+  function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) + R);
+  end function "+";
+
+  -- Id: A.3L
+  function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (L + UNSIGNED(R));
+  end function "+";
+
+  -- Id: A.5
+  function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) + R);
+  end function "+";
+
+  -- Id: A.6
+  function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (L + UNSIGNED(R));
+  end function "+";
+
+  --============================================================================
+
+  -- Id: A.9
+  function "-" (L, R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) - UNSIGNED(R));
+  end function "-";
+
+  -- Id: A.9R
+  function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) - R);
+  end function "-";
+
+  -- Id: A.9L
+  function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (L - UNSIGNED(R));
+  end function "-";
+
+  -- Id: A.11
+  function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) - R);
+  end function "-";
+
+  -- Id: A.12
+  function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (L - UNSIGNED(R));
+  end function "-";
+
+  --============================================================================
+
+  -- Id: A.15
+  function "*" (L, R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) * UNSIGNED(R));
+  end function "*";
+
+  -- Id: A.17
+  function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) * R);
+  end function "*";
+
+  -- Id: A.18
+  function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (L * UNSIGNED(R));
+  end function "*";
+
+  --============================================================================
+
+  -- Id: A.21
+  function "/" (L, R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) / UNSIGNED(R));
+  end function "/";
+
+  -- Id: A.23
+  function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) / R);
+  end function "/";
+
+  -- Id: A.24
+  function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (L / UNSIGNED(R));
+  end function "/";
+
+  --============================================================================
+
+  -- Id: A.27
+  function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
+  end function "rem";
+
+  -- Id: A.29
+  function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) rem R);
+  end function "rem";
+
+  -- Id: A.30
+  function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (L rem UNSIGNED(R));
+  end function "rem";
+
+  --============================================================================
+
+  -- Id: A.33
+  function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
+  end function "mod";
+
+  -- Id: A.35
+  function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(L) mod R);
+  end function "mod";
+
+  -- Id: A.36
+  function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (L mod UNSIGNED(R));
+  end function "mod";
+
+  --============================================================================
+  -- Id: A.39
+  function find_leftmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is
+  begin
+    return find_leftmost(UNSIGNED(ARG), Y);
+  end function find_leftmost;
+
+  -- Id: A.41
+  function find_rightmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is
+  begin
+    return find_rightmost(UNSIGNED(ARG), Y);
+  end function find_rightmost;
+
+  --============================================================================
+  -- Id: C.1
+  function ">" (L, R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) > UNSIGNED(R);
+  end function ">";
+
+  -- Id: C.3
+  function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return L > UNSIGNED(R);
+  end function ">";
+
+  -- Id: C.5
+  function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) > R;
+  end function ">";
+
+  --============================================================================
+  -- Id: C.7
+  function "<" (L, R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) < UNSIGNED(R);
+  end function "<";
+
+  -- Id: C.9
+  function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return L < UNSIGNED(R);
+  end function "<";
+
+  -- Id: C.11
+  function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) < R;
+  end function "<";
+
+  --============================================================================
+  -- Id: C.13
+  function "<=" (L, R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) <= UNSIGNED(R);
+  end function "<=";
+
+  -- Id: C.15
+  function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return L <= UNSIGNED(R);
+  end function "<=";
+
+  -- Id: C.17
+  function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) <= R;
+  end function "<=";
+
+  --============================================================================
+  -- Id: C.19
+  function ">=" (L, R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) >= UNSIGNED(R);
+  end function ">=";
+
+  -- Id: C.21
+  function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return L >= UNSIGNED(R);
+  end function ">=";
+
+  -- Id: C.23
+  function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) >= R;
+  end function ">=";
+
+  --============================================================================
+  -- Id: C.25
+  function "=" (L, R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) = UNSIGNED(R);
+  end function "=";
+
+  -- Id: C.27
+  function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return L = UNSIGNED(R);
+  end function "=";
+
+  -- Id: C.29
+  function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) = R;
+  end function "=";
+
+  --============================================================================
+  -- Id: C.31
+  function "/=" (L, R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) /= UNSIGNED(R);
+  end function "/=";
+
+  -- Id: C.33
+  function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
+  begin
+    return L /= UNSIGNED(R);
+  end function "/=";
+
+  -- Id: C.35
+  function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) /= R;
+  end function "/=";
+
+  --============================================================================
+  -- Id: C.37
+  function MINIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
+  end function MINIMUM;
+
+  -- Id: C.39
+  function MINIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (MINIMUM(L, UNSIGNED(R)));
+  end function MINIMUM;
+
+  -- Id: C.41
+  function MINIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (MINIMUM(UNSIGNED(L), R));
+  end function MINIMUM;
+
+  --============================================================================
+  -- Id: C.43
+  function MAXIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
+  end function MAXIMUM;
+
+  -- Id: C.45
+  function MAXIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (MAXIMUM(L, UNSIGNED(R)));
+  end function MAXIMUM;
+
+  -- Id: C.47
+  function MAXIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (MAXIMUM(UNSIGNED(L), R));
+  end function MAXIMUM;
+
+  --============================================================================
+
+  -- Id: C.49
+  function "?>" (L, R: BIT_VECTOR) return BIT is
+  begin
+    return UNSIGNED(L) ?> UNSIGNED(R);
+  end function "?>";
+
+  -- Id: C.51
+  function "?>" (L: NATURAL; R: BIT_VECTOR) return BIT is
+  begin
+    return L ?> UNSIGNED(R);
+  end function "?>";
+
+  -- Id: C.53
+  function "?>" (L: BIT_VECTOR; R: NATURAL) return BIT is
+  begin
+    return UNSIGNED(L) ?> R;
+  end function "?>";
+
+  --============================================================================
+
+  -- Id: C.55
+  function "?<" (L, R: BIT_VECTOR) return BIT is
+  begin
+    return UNSIGNED(L) ?< UNSIGNED(R);
+  end function "?<";
+
+  -- Id: C.57
+  function "?<" (L: NATURAL; R: BIT_VECTOR) return BIT is
+  begin
+    return L ?< UNSIGNED(R);
+  end function "?<";
+
+  -- Id: C.59
+  function "?<" (L: BIT_VECTOR; R: NATURAL) return BIT is
+  begin
+    return UNSIGNED(L) ?< R;
+  end function "?<";
+
+  --============================================================================
+
+  -- Id: C.61
+  function "?<=" (L, R: BIT_VECTOR) return BIT is
+  begin
+    return UNSIGNED(L) ?<= UNSIGNED(R);
+  end function "?<=";
+
+  -- Id: C.63
+  function "?<=" (L: NATURAL; R: BIT_VECTOR) return BIT is
+  begin
+    return L ?<= UNSIGNED(R);
+  end function "?<=";
+
+  -- Id: C.65
+  function "?<=" (L: BIT_VECTOR; R: NATURAL) return BIT is
+  begin
+    return UNSIGNED(L) ?<= R;
+  end function "?<=";
+
+  --============================================================================
+
+  -- Id: C.67
+  function "?>=" (L, R: BIT_VECTOR) return BIT is
+  begin
+    return UNSIGNED(L) ?>= UNSIGNED(R);
+  end function "?>=";
+
+  -- Id: C.69
+  function "?>=" (L: NATURAL; R: BIT_VECTOR) return BIT is
+  begin
+    return L ?>= UNSIGNED(R);
+  end function "?>=";
+
+  -- Id: C.71
+  function "?>=" (L: BIT_VECTOR; R: NATURAL) return BIT is
+  begin
+    return UNSIGNED(L) ?>= R;
+  end function "?>=";
+
+  --============================================================================
+
+  -- Id: C.73
+  function "?=" (L, R: BIT_VECTOR) return BIT is
+  begin
+    return UNSIGNED(L) ?= UNSIGNED(R);
+  end function "?=";
+
+  -- Id: C.75
+  function "?=" (L: NATURAL; R: BIT_VECTOR) return BIT is
+  begin
+    return L ?= UNSIGNED(R);
+  end function "?=";
+
+  -- Id: C.77
+  function "?=" (L: BIT_VECTOR; R: NATURAL) return BIT is
+  begin
+    return UNSIGNED(L) ?= R;
+  end function "?=";
+
+  --============================================================================
+
+  -- Id: C.79
+  function "?/=" (L, R: BIT_VECTOR) return BIT is
+  begin
+    return UNSIGNED(L) ?/= UNSIGNED(R);
+  end function "?/=";
+
+  -- Id: C.81
+  function "?/=" (L: NATURAL; R: BIT_VECTOR) return BIT is
+  begin
+    return L ?/= UNSIGNED(R);
+  end function "?/=";
+
+  -- Id: C.83
+  function "?/=" (L: BIT_VECTOR; R: NATURAL) return BIT is
+  begin
+    return UNSIGNED(L) ?/= R;
+  end function "?/=";
+
+  --============================================================================
+
+  -- Id: S.1
+  function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (shift_left (ARG   => UNSIGNED(ARG),
+                                   COUNT => COUNT));
+  end function SHIFT_LEFT;
+
+  -- Id: S.2
+  function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (shift_right (ARG   => UNSIGNED(ARG),
+                                    COUNT => COUNT));
+  end function SHIFT_RIGHT;
+
+  --============================================================================
+
+  -- Id: S.5
+  function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (rotate_left (ARG   => UNSIGNED(ARG),
+                                    COUNT => COUNT));
+  end function ROTATE_LEFT;
+
+  -- Id: S.6
+  function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (rotate_right (ARG   => UNSIGNED(ARG),
+                                     COUNT => COUNT));
+  end function ROTATE_RIGHT;
+
+  --============================================================================
+
+  -- Id: S.9
+  function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(ARG) sll COUNT);
+  end function "sll";
+
+  -- Id: S.11
+  function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(ARG) srl COUNT);
+  end function "srl";
+
+  -- Id: S.13
+  function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(ARG) rol COUNT);
+  end function "rol";
+
+  -- Id: S.15
+  function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(ARG) ror COUNT);
+  end function "ror";
+
+  -- Id: S.17
+  function "sla" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(ARG) sla COUNT);
+  end function "sla";
+
+  -- Id: S.19
+  function "sra" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (UNSIGNED(ARG) sra COUNT);
+  end function "sra";
+
+  --============================================================================
+
+  -- Id: R.2
+  function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (
+      resize (arg      => UNSIGNED(ARG),
+              NEW_SIZE => NEW_SIZE));
+  end function RESIZE;
+
+  function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (
+      RESIZE (ARG      => UNSIGNED(ARG),
+              NEW_SIZE => SIZE_RES'length));
+  end function RESIZE;
+
+  --============================================================================
+
+  -- Id: D.1
+  function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL is
+  begin
+    return TO_INTEGER (UNSIGNED(ARG));
+  end function TO_INTEGER;
+
+  -- Id: D.3
+  function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE));
+  end function To_BitVector;
+
+  function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
+    return BIT_VECTOR is
+  begin
+    return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE_RES'length));
+  end function To_BitVector;
+
+end package body NUMERIC_BIT_UNSIGNED;

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_bit_unsigned.vhdl

@@ -0,0 +1,623 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this 
+-- source file may be used and distributed without restriction. 
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission 
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+--
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file 
+-- shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+--   Title     :  Standard VHDL Synthesis Packages
+--             :  (NUMERIC_BIT_UNSIGNED package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC, and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This package defines numeric types and arithmetic functions
+--             :  for use with synthesis tools. Values of type BIT_VECTOR
+--             :  are interpreted as unsigned numbers in vector form.
+--             :  The leftmost bit is treated as the most significant bit.
+--             :  This package contains overloaded arithmetic operators on
+--             :  the BIT_VECTOR type. The package also contains
+--             :  useful type conversions functions, clock detection
+--             :  functions, and other utility functions.
+--             :
+--             :  If any argument to a function is a null array, a null array
+--             :  is returned (exceptions, if any, are noted individually).
+--
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+package NUMERIC_BIT_UNSIGNED is
+  constant CopyRightNotice : STRING :=
+    "Copyright 2008 IEEE. All rights reserved.";
+
+  -- Id: A.3
+  function "+" (L, R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
+  -- Result: Adds two UNSIGNED vectors that may be of different lengths.
+
+  -- Id: A.3R
+  function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
+  -- Result subtype: bit_vector(L'LENGTH-1 downto 0)
+  -- Result: Similar to A.3 where R is a one bit bit_vector
+
+  -- Id: A.3L
+  function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0)
+  -- Result: Similar to A.3 where L is a one bit UNSIGNED
+
+  -- Id: A.5
+  function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(L'LENGTH-1 downto 0).
+  -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
+
+  -- Id: A.6
+  function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0).
+  -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
+
+  --============================================================================
+
+  -- Id: A.9
+  function "-" (L, R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
+  -- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
+
+  -- Id: A.9R
+  function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
+  -- Result subtype: bit_vector(L'LENGTH-1 downto 0)
+  -- Result: Similar to A.9 where R is a one bit UNSIGNED
+
+  -- Id: A.9L
+  function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0)
+  -- Result: Similar to A.9 where L is a one bit UNSIGNED
+
+  -- Id: A.11
+  function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(L'LENGTH-1 downto 0).
+  -- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
+
+  -- Id: A.12
+  function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0).
+  -- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
+
+  --============================================================================
+
+  -- Id: A.15
+  function "*" (L, R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0).
+  -- Result: Performs the multiplication operation on two UNSIGNED vectors
+  --         that may possibly be of different lengths.
+
+  -- Id: A.17
+  function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0).
+  -- Result: Multiplies an UNSIGNED vector, L, with a non-negative
+  --         INTEGER, R. R is converted to an UNSIGNED vector of
+  --         SIZE L'LENGTH before multiplication.
+
+  -- Id: A.18
+  function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0).
+  -- Result: Multiplies an UNSIGNED vector, R, with a non-negative
+  --         INTEGER, L. L is converted to an UNSIGNED vector of
+  --         SIZE R'LENGTH before multiplication.
+
+  --============================================================================
+  --
+  -- NOTE: If second argument is zero for "/" operator, a severity level
+  --       of ERROR is issued.
+
+  -- Id: A.21
+  function "/" (L, R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(L'LENGTH-1 downto 0)
+  -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
+
+  -- Id: A.23
+  function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(L'LENGTH-1 downto 0)
+  -- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
+  --         If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
+
+  -- Id: A.24
+  function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0)
+  -- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
+  --         If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
+
+  --============================================================================
+  --
+  -- NOTE: If second argument is zero for "rem" operator, a severity level
+  --       of ERROR is issued.
+
+  -- Id: A.27
+  function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0)
+  -- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
+
+  -- Id: A.29
+  function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(L'LENGTH-1 downto 0)
+  -- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
+  --         non-negative INTEGER.
+  --         If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
+
+  -- Id: A.30
+  function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0)
+  -- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
+  --         non-negative INTEGER.
+  --         If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
+
+  --============================================================================
+  --
+  -- NOTE: If second argument is zero for "mod" operator, a severity level
+  --       of ERROR is issued.
+
+  -- Id: A.33
+  function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0)
+  -- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
+
+  -- Id: A.35
+  function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(L'LENGTH-1 downto 0)
+  -- Result: Computes "L mod R" where L is an UNSIGNED vector and R
+  --         is a non-negative INTEGER.
+  --         If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
+
+  -- Id: A.36
+  function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: bit_vector(R'LENGTH-1 downto 0)
+  -- Result: Computes "L mod R" where R is an UNSIGNED vector and L
+  --         is a non-negative INTEGER.
+  --         If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
+
+  --============================================================================
+  -- Id: A.39
+  function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
+  -- Result subtype: INTEGER
+  -- Result: Finds the leftmost occurrence of the value of Y in ARG.
+  --         Returns the index of the occurrence if it exists, or -1 otherwise.
+
+  -- Id: A.41
+  function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
+  -- Result subtype: INTEGER
+  -- Result: Finds the leftmost occurrence of the value of Y in ARG.
+  --         Returns the index of the occurrence if it exists, or -1 otherwise.
+
+  --============================================================================
+  -- Comparison Operators
+  --============================================================================
+  -- Id: C.1
+  function ">" (L, R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.3
+  function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L > R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.5
+  function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L > R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+  -- Id: C.7
+  function "<" (L, R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.9
+  function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L < R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.11
+  function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L < R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+  -- Id: C.13
+  function "<=" (L, R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.15
+  function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L <= R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.17
+  function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L <= R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+  -- Id: C.19
+  function ">=" (L, R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.21
+  function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L >= R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.23
+  function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L >= R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+  -- Id: C.25
+  function "=" (L, R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.27
+  function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L = R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.29
+  function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L = R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.31
+  function "/=" (L, R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.33
+  function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L /= R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.35
+  function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L /= R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.37
+  function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR
+  -- Result: Returns the lesser of two UNSIGNED vectors that may be
+  --         of different lengths.
+
+  -- Id: C.39
+  function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR
+  -- Result: Returns the lesser of a nonnegative INTEGER, L, and
+  --         an UNSIGNED vector, R.
+
+  -- Id: C.41
+  function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR
+  -- Result: Returns the lesser of an UNSIGNED vector, L, and
+  --         a nonnegative INTEGER, R.
+
+  --============================================================================
+
+  -- Id: C.43
+  function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR
+  -- Result: Returns the greater of two UNSIGNED vectors that may be
+  --         of different lengths.
+
+  -- Id: C.45
+  function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR
+  -- Result: Returns the greater of a nonnegative INTEGER, L, and
+  --         an UNSIGNED vector, R.
+
+  -- Id: C.47
+  function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR
+  -- Result: Returns the greater of an UNSIGNED vector, L, and
+  --         a nonnegative INTEGER, R.
+
+  --============================================================================
+  -- Id: C.49
+  function "?>" (L, R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.51
+  function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L > R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.53
+  function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L > R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.55
+  function "?<" (L, R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.57
+  function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L < R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.59
+  function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L < R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.61
+  function "?<=" (L, R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.63
+  function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L <= R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.65
+  function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L <= R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.67
+  function "?>=" (L, R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.69
+  function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L >= R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.71
+  function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L >= R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.73
+  function "?=" (L, R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.75
+  function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L = R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.77
+  function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L = R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.79
+  function "?/=" (L, R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.81
+  function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L /= R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.83
+  function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT;
+  -- Result subtype: BIT
+  -- Result: Computes "L /= R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+  -- Shift and Rotate Functions
+  --============================================================================
+
+  -- Id: S.1
+  function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
+  -- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
+  --         The vacated positions are filled with '0'.
+  --         The COUNT leftmost elements are lost.
+
+  -- Id: S.2
+  function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
+  -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
+  -- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
+  --         The vacated positions are filled with '0'.
+  --         The COUNT rightmost elements are lost.
+  --============================================================================
+
+  -- Id: S.5
+  function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
+  -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
+
+  -- Id: S.6
+  function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
+  -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
+
+
+  --============================================================================
+
+  ------------------------------------------------------------------------------
+  -- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
+  -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
+  ------------------------------------------------------------------------------
+  -- Id: S.9
+  function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: SHIFT_LEFT(ARG, COUNT)
+
+  ------------------------------------------------------------------------------
+  -- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
+  -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
+  ------------------------------------------------------------------------------
+  -- Id: S.11
+  function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: SHIFT_RIGHT(ARG, COUNT)
+
+  ------------------------------------------------------------------------------
+  -- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
+  -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
+  ------------------------------------------------------------------------------
+  -- Id: S.13
+  function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: ROTATE_LEFT(ARG, COUNT)
+
+  ------------------------------------------------------------------------------
+  -- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
+  -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
+  ------------------------------------------------------------------------------
+  -- Id: S.15
+  function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: ROTATE_RIGHT(ARG, COUNT)
+
+  ------------------------------------------------------------------------------
+  -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
+  -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
+  ------------------------------------------------------------------------------
+  -- Id: S.17
+  function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: SHIFT_LEFT(ARG, COUNT)
+
+  ------------------------------------------------------------------------------
+  -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
+  -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
+  ------------------------------------------------------------------------------
+  -- Id: S.19
+  function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: SHIFT_RIGHT(ARG, COUNT)
+
+
+  --============================================================================
+  --   RESIZE Functions
+  --============================================================================
+
+  -- Id: R.2
+  function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(NEW_SIZE-1 downto 0)
+  -- Result: Resizes the UNSIGNED vector ARG to the specified size.
+  --         To create a larger vector, the new [leftmost] bit positions
+  --         are filled with '0'. When truncating, the leftmost bits
+  --         are dropped.
+
+  function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR;
+  -- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0)
+
+  --============================================================================
+  -- Conversion Functions
+  --============================================================================
+
+  -- Id: D.1
+  function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL;
+  -- Result subtype: NATURAL. Value cannot be negative since parameter is an
+  --             UNSIGNED vector.
+  -- Result: Converts the UNSIGNED vector to an INTEGER.
+
+  -- Id: D.3
+  function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR;
+  -- Result subtype: bit_vector(SIZE-1 downto 0)
+  -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
+  --         the specified size.
+
+  function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
+    return BIT_VECTOR;
+  -- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
+
+-- begin LCS-2006-130
+  alias To_Bit_Vector is
+    To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
+  alias To_BV is
+    To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
+
+  alias To_Bit_Vector is
+    To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
+  alias To_BV is
+    To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
+
+end package NUMERIC_BIT_UNSIGNED;

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std_unsigned-body.vhdl

@@ -0,0 +1,595 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this 
+-- source file may be used and distributed without restriction. 
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission 
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+--
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file 
+-- shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+--   Title     :  Standard VHDL Synthesis Packages
+--             :  (NUMERIC_STD_UNSIGNED package body)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC, and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This package defines numeric types and arithmetic functions
+--             :  for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
+--             :  are interpreted as unsigned numbers in vector form.
+--             :  The leftmost bit is treated as the most significant bit.
+--             :  This package contains overloaded arithmetic operators on
+--             :  the STD_ULOGIC_VECTOR type. The package also contains
+--             :  useful type conversions functions, clock detection
+--             :  functions, and other utility functions.
+--             :
+--             :  If any argument to a function is a null array, a null array
+--             :  is returned (exceptions, if any, are noted individually).
+--
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+library ieee;
+use ieee.numeric_std.all;
+
+package body NUMERIC_STD_UNSIGNED is
+
+  -- Id: A.3
+  function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
+  end function "+";
+
+  -- Id: A.3R
+  function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
+  end function "+";
+
+  -- Id: A.3L
+  function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
+  end function "+";
+
+  -- Id: A.5
+  function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
+  end function "+";
+
+  -- Id: A.6
+  function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
+  end function "+";
+
+  --============================================================================
+
+  -- Id: A.9
+  function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
+  end function "-";
+
+  -- Id: A.9R
+  function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
+  end function "-";
+
+  -- Id: A.9L
+  function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
+  end function "-";
+
+  -- Id: A.11
+  function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
+  end function "-";
+
+  -- Id: A.12
+  function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
+  end function "-";
+
+  --============================================================================
+
+  -- Id: A.15
+  function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
+  end function "*";
+
+  -- Id: A.17
+  function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
+  end function "*";
+
+  -- Id: A.18
+  function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
+  end function "*";
+
+  --============================================================================
+
+  -- Id: A.21
+  function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
+  end function "/";
+
+  -- Id: A.23
+  function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
+  end function "/";
+
+  -- Id: A.24
+  function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
+  end function "/";
+
+  --============================================================================
+
+  -- Id: A.27
+  function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
+  end function "rem";
+
+  -- Id: A.29
+  function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
+  end function "rem";
+
+  -- Id: A.30
+  function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
+  end function "rem";
+
+  --============================================================================
+
+  -- Id: A.33
+  function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
+  end function "mod";
+
+  -- Id: A.35
+  function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
+  end function "mod";
+
+  -- Id: A.36
+  function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
+  end function "mod";
+
+  --============================================================================
+  -- Id: A.39
+  function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
+  begin
+    return find_leftmost(UNSIGNED(ARG), Y);
+  end function find_leftmost;
+
+  -- Id: A.41
+  function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
+  begin
+    return find_rightmost(UNSIGNED(ARG), Y);
+  end function find_rightmost;
+
+  --============================================================================
+
+  -- Id: C.1
+  function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) > UNSIGNED(R);
+  end function ">";
+
+  -- Id: C.3
+  function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return L > UNSIGNED(R);
+  end function ">";
+
+  -- Id: C.5
+  function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) > R;
+  end function ">";
+
+  --============================================================================
+
+  -- Id: C.7
+  function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) < UNSIGNED(R);
+  end function "<";
+
+  -- Id: C.9
+  function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return L < UNSIGNED(R);
+  end function "<";
+
+  -- Id: C.11
+  function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) < R;
+  end function "<";
+
+  --============================================================================
+
+  -- Id: C.13
+  function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) <= UNSIGNED(R);
+  end function "<=";
+
+  -- Id: C.15
+  function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return L <= UNSIGNED(R);
+  end function "<=";
+
+  -- Id: C.17
+  function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) <= R;
+  end function "<=";
+
+  --============================================================================
+
+  -- Id: C.19
+  function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) >= UNSIGNED(R);
+  end function ">=";
+
+  -- Id: C.21
+  function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return L >= UNSIGNED(R);
+  end function ">=";
+
+  -- Id: C.23
+  function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) >= R;
+  end function ">=";
+
+  --============================================================================
+
+  -- Id: C.25
+  function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) = UNSIGNED(R);
+  end function "=";
+
+  -- Id: C.27
+  function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return L = UNSIGNED(R);
+  end function "=";
+
+  -- Id: C.29
+  function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) = R;
+  end function "=";
+
+  --============================================================================
+
+  -- Id: C.31
+  function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return UNSIGNED(L) /= UNSIGNED(R);
+  end function "/=";
+
+  -- Id: C.33
+  function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
+  begin
+    return L /= UNSIGNED(R);
+  end function "/=";
+
+  -- Id: C.35
+  function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
+  begin
+    return UNSIGNED(L) /= R;
+  end function "/=";
+
+  --============================================================================
+
+  -- Id: C.37
+  function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
+  end function MINIMUM;
+
+  -- Id: C.39
+  function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
+  end function MINIMUM;
+
+  -- Id: C.41
+  function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
+  end function MINIMUM;
+
+  --============================================================================
+  -- Id: C.43
+  function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
+  end function MAXIMUM;
+
+  -- Id: C.45
+  function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
+  end function MAXIMUM;
+
+  -- Id: C.47
+  function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
+  end function MAXIMUM;
+
+  --============================================================================
+
+  -- Id: C.49
+  function "?>" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?> UNSIGNED(R);
+  end function "?>";
+
+  -- Id: C.51
+  function "?>" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return L ?> UNSIGNED(R);
+  end function "?>";
+
+  -- Id: C.53
+  function "?>" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?> R;
+  end function "?>";
+
+  --============================================================================
+
+  -- Id: C.55
+  function "?<" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?< UNSIGNED(R);
+  end function "?<";
+
+  -- Id: C.57
+  function "?<" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return L ?< UNSIGNED(R);
+  end function "?<";
+
+  -- Id: C.59
+  function "?<" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?< R;
+  end function "?<";
+
+  --============================================================================
+
+  -- Id: C.61
+  function "?<=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?<= UNSIGNED(R);
+  end function "?<=";
+
+  -- Id: C.63
+  function "?<=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return L ?<= UNSIGNED(R);
+  end function "?<=";
+
+  -- Id: C.65
+  function "?<=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?<= R;
+  end function "?<=";
+
+  --============================================================================
+
+  -- Id: C.67
+  function "?>=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?>= UNSIGNED(R);
+  end function "?>=";
+
+  -- Id: C.69
+  function "?>=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return L ?>= UNSIGNED(R);
+  end function "?>=";
+
+  -- Id: C.71
+  function "?>=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?>= R;
+  end function "?>=";
+
+  --============================================================================
+
+  -- Id: C.73
+  function "?=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?= UNSIGNED(R);
+  end function "?=";
+
+  -- Id: C.75
+  function "?=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return L ?= UNSIGNED(R);
+  end function "?=";
+
+  -- Id: C.77
+  function "?=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?= R;
+  end function "?=";
+
+  --============================================================================
+
+  -- Id: C.79
+  function "?/=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?/= UNSIGNED(R);
+  end function "?/=";
+
+  -- Id: C.81
+  function "?/=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
+  begin
+    return L ?/= UNSIGNED(R);
+  end function "?/=";
+
+  -- Id: C.83
+  function "?/=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
+  begin
+    return UNSIGNED(L) ?/= R;
+  end function "?/=";
+
+  --============================================================================
+
+  -- Id: S.1
+  function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return std_logic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
+  end function SHIFT_LEFT;
+
+  -- Id: S.2
+  function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return std_logic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
+  end function SHIFT_RIGHT;
+
+  --============================================================================
+
+  -- Id: S.5
+  function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return std_logic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
+  end function ROTATE_LEFT;
+
+  -- Id: S.6
+  function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return std_logic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
+  end function ROTATE_RIGHT;
+
+  --============================================================================
+
+  -- Id: S.17
+  function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
+  end function "sla";
+
+  -- Id: S.19
+  function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
+  end function "sra";
+
+  --============================================================================
+
+  -- Id: R.2
+  function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (
+      RESIZE (ARG      => UNSIGNED(ARG),
+              NEW_SIZE => NEW_SIZE));
+  end function RESIZE;
+
+  function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (
+      RESIZE (ARG     => UNSIGNED(ARG),
+              NEW_SIZE => SIZE_RES'length));
+  end function RESIZE;
+
+  --============================================================================
+
+  -- Id: D.1
+  function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
+  begin
+    return TO_INTEGER(UNSIGNED(ARG));
+  end function TO_INTEGER;
+
+  -- Id: D.3
+  function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
+  begin
+    return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG  => ARG,
+                                         SIZE => SIZE));
+  end function To_StdLogicVector;
+
+  -- Id: D.5
+  function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG  => ARG,
+                                         SIZE => SIZE));
+  end function To_StdULogicVector;
+
+  function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR)
+    return STD_LOGIC_VECTOR is
+  begin
+    return STD_LOGIC_VECTOR (TO_UNSIGNED (ARG  => ARG,
+                                          SIZE => SIZE_RES'length));
+  end function To_StdLogicVector;
+
+  function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
+    return STD_ULOGIC_VECTOR is
+  begin
+    return STD_ULOGIC_VECTOR (TO_UNSIGNED (ARG  => ARG,
+                                           SIZE => SIZE_RES'length));
+  end function To_StdULogicVector;
+
+end package body NUMERIC_STD_UNSIGNED;

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/numeric_std_unsigned.vhdl

@@ -0,0 +1,616 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this 
+-- source file may be used and distributed without restriction. 
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission 
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+--
+-- This source file is provided on an AS IS basis. The IEEE disclaims ANY 
+-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY 
+-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file 
+-- shall indemnify and hold IEEE harmless from any damages or liability 
+-- arising out of the use thereof.
+--
+--   Title     :  Standard VHDL Synthesis Packages
+--             :  (NUMERIC_STD_UNSIGNED package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC, and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This package defines numeric types and arithmetic functions
+--             :  for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
+--             :  are interpreted as unsigned numbers in vector form.
+--             :  The leftmost bit is treated as the most significant bit.
+--             :  This package contains overloaded arithmetic operators on
+--             :  the STD_ULOGIC_VECTOR type. The package also contains
+--             :  useful type conversions functions, clock detection
+--             :  functions, and other utility functions.
+--             :
+--             :  If any argument to a function is a null array, a null array
+--             :  is returned (exceptions, if any, are noted individually).
+--
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1220 $
+-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
+-- --------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+package NUMERIC_STD_UNSIGNED is
+  constant CopyRightNotice : STRING :=
+    "Copyright 2008 IEEE. All rights reserved.";
+
+  -- Id: A.3
+  function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
+  -- Result: Adds two UNSIGNED vectors that may be of different lengths.
+
+  -- Id: A.3R
+  function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
+  -- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
+
+  -- Id: A.3L
+  function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
+  -- Result: Similar to A.3 where L is a one bit UNSIGNED
+
+  -- Id: A.5
+  function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
+  -- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
+
+  -- Id: A.6
+  function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
+  -- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
+
+  --============================================================================
+
+  -- Id: A.9
+  function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
+  -- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
+
+  -- Id: A.9R
+  function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
+  -- Result: Similar to A.9 where R is a one bit UNSIGNED
+
+  -- Id: A.9L
+  function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
+  -- Result: Similar to A.9 where L is a one bit UNSIGNED
+
+  -- Id: A.11
+  function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
+  -- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
+
+  -- Id: A.12
+  function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
+  -- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
+
+  --============================================================================
+
+  -- Id: A.15
+  function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
+  -- Result: Performs the multiplication operation on two UNSIGNED vectors
+  --         that may possibly be of different lengths.
+
+  -- Id: A.17
+  function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
+  -- Result: Multiplies an UNSIGNED vector, L, with a non-negative
+  --         INTEGER, R. R is converted to an UNSIGNED vector of
+  --         SIZE L'LENGTH before multiplication.
+
+  -- Id: A.18
+  function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
+  -- Result: Multiplies an UNSIGNED vector, R, with a non-negative
+  --         INTEGER, L. L is converted to an UNSIGNED vector of
+  --         SIZE R'LENGTH before multiplication.
+
+  --============================================================================
+  --
+  -- NOTE: If second argument is zero for "/" operator, a severity level
+  --       of ERROR is issued.
+
+  -- Id: A.21
+  function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
+  -- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
+
+  -- Id: A.23
+  function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
+  -- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
+  --         If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
+
+  -- Id: A.24
+  function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
+  -- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
+  --         If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
+
+  --============================================================================
+  --
+  -- NOTE: If second argument is zero for "rem" operator, a severity level
+  --       of ERROR is issued.
+
+  -- Id: A.27
+  function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
+  -- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
+
+  -- Id: A.29
+  function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
+  -- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
+  --         non-negative INTEGER.
+  --         If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
+
+  -- Id: A.30
+  function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
+  -- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
+  --         non-negative INTEGER.
+  --         If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
+
+  --============================================================================
+  --
+  -- NOTE: If second argument is zero for "mod" operator, a severity level
+  --       of ERROR is issued.
+
+  -- Id: A.33
+  function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
+  -- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
+
+  -- Id: A.35
+  function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
+  -- Result: Computes "L mod R" where L is an UNSIGNED vector and R
+  --         is a non-negative INTEGER.
+  --         If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
+
+  -- Id: A.36
+  function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
+  -- Result: Computes "L mod R" where R is an UNSIGNED vector and L
+  --         is a non-negative INTEGER.
+  --         If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
+
+  --============================================================================
+  -- Id: A.39
+  function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
+  -- Result subtype: INTEGER
+  -- Result: Finds the leftmost occurrence of the value of Y in ARG.
+  --         Returns the index of the occurrence if it exists, or -1 otherwise.
+
+  -- Id: A.41
+  function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
+  -- Result subtype: INTEGER
+  -- Result: Finds the leftmost occurrence of the value of Y in ARG.
+  --         Returns the index of the occurrence if it exists, or -1 otherwise.
+
+  --============================================================================
+  -- Comparison Operators
+  --============================================================================
+
+  -- Id: C.1
+  function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.3
+  function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L > R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.5
+  function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L > R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.7
+  function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.9
+  function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L < R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.11
+  function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L < R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.13
+  function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.15
+  function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L <= R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.17
+  function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L <= R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.19
+  function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.21
+  function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L >= R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.23
+  function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L >= R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.25
+  function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.27
+  function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L = R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.29
+  function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L = R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.31
+  function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.33
+  function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L /= R" where L is a non-negative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.35
+  function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
+  -- Result subtype: BOOLEAN
+  -- Result: Computes "L /= R" where L is an UNSIGNED vector and
+  --         R is a non-negative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.37
+  function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR
+  -- Result: Returns the lesser of two UNSIGNED vectors that may be
+  --         of different lengths.
+
+  -- Id: C.39
+  function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR
+  -- Result: Returns the lesser of a nonnegative INTEGER, L, and
+  --         an UNSIGNED vector, R.
+
+  -- Id: C.41
+  function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR
+  -- Result: Returns the lesser of an UNSIGNED vector, L, and
+  --         a nonnegative INTEGER, R.
+
+  --============================================================================
+
+  -- Id: C.43
+  function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR
+  -- Result: Returns the greater of two UNSIGNED vectors that may be
+  --         of different lengths.
+
+  -- Id: C.45
+  function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR
+  -- Result: Returns the greater of a nonnegative INTEGER, L, and
+  --         an UNSIGNED vector, R.
+
+  -- Id: C.47
+  function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR
+  -- Result: Returns the greater of an UNSIGNED vector, L, and
+  --         a nonnegative INTEGER, R.
+
+  --============================================================================
+  -- Id: C.49
+  function "?>" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.51
+  function "?>" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L > R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.53
+  function "?>" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L > R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.55
+  function "?<" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.57
+  function "?<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L < R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.59
+  function "?<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L < R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.61
+  function "?<=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.63
+  function "?<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L <= R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.65
+  function "?<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L <= R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.67
+  function "?>=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.69
+  function "?>=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L >= R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.71
+  function "?>=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L >= R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.73
+  function "?=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.75
+  function "?=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L = R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.77
+  function "?=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L = R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+
+  -- Id: C.79
+  function "?/=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
+  --         of different lengths.
+
+  -- Id: C.81
+  function "?/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L /= R" where L is a nonnegative INTEGER and
+  --         R is an UNSIGNED vector.
+
+  -- Id: C.83
+  function "?/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
+  -- Result subtype: STD_ULOGIC
+  -- Result: Computes "L /= R" where L is an UNSIGNED vector and
+  --         R is a nonnegative INTEGER.
+
+  --============================================================================
+  -- Shift and Rotate Functions
+  --============================================================================
+
+  -- Id: S.1
+  function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
+    return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
+  --         The vacated positions are filled with '0'.
+  --         The COUNT leftmost elements are lost.
+
+  -- Id: S.2
+  function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
+    return STD_ULOGIC_VECTOR;
+  -- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
+  -- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
+  --         The vacated positions are filled with '0'.
+  --         The COUNT rightmost elements are lost.
+  --============================================================================
+
+  -- Id: S.5
+  function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
+    return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
+
+  -- Id: S.6
+  function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
+    return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
+
+
+  --============================================================================
+
+  ------------------------------------------------------------------------------
+  -- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
+  -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
+  ------------------------------------------------------------------------------
+  -- Id: S.17
+  function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: SHIFT_LEFT(ARG, COUNT)
+
+  ------------------------------------------------------------------------------
+  -- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
+  -- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
+  ------------------------------------------------------------------------------
+  -- Id: S.19
+  function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
+  -- Result: SHIFT_RIGHT(ARG, COUNT)
+
+
+  --============================================================================
+  --   RESIZE Functions
+  --============================================================================
+
+  -- Id: R.2
+  function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
+    return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
+  -- Result: Resizes the UNSIGNED vector ARG to the specified size.
+  --         To create a larger vector, the new [leftmost] bit positions
+  --         are filled with '0'. When truncating, the leftmost bits
+  --         are dropped.
+
+  function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
+
+  --============================================================================
+  -- Conversion Functions
+  --============================================================================
+
+  -- Id: D.1
+  function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
+  -- Result subtype: NATURAL. Value cannot be negative since parameter is an
+  --             UNSIGNED vector.
+  -- Result: Converts the UNSIGNED vector to an INTEGER.
+
+  -- Id: D.3
+  function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
+  -- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
+  -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
+  --         the specified SIZE.
+
+  function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
+    return STD_LOGIC_VECTOR;
+  -- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
+
+  alias To_Std_Logic_Vector is
+    To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
+  alias To_SLV is
+    To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
+  alias To_Std_Logic_Vector is
+    To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
+  alias To_SLV is
+    To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
+
+  -- Id: D.5
+  function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
+  -- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
+  --         the specified SIZE.
+
+  function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
+    return STD_ULOGIC_VECTOR;
+  -- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
+
+  alias To_Std_ULogic_Vector is
+    To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
+  alias To_SULV is
+    To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
+  alias To_Std_ULogic_Vector is
+    To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
+  alias To_SULV is
+    To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
+
+end package NUMERIC_STD_UNSIGNED;

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_1164.vhdl

@@ -0,0 +1,369 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE. All rights reserved.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This
+-- source file may be used and distributed without restriction.
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+-- 
+--   Title     :  Standard multivalue logic package
+--             :  (STD_LOGIC_1164 package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  IEEE model standards group (PAR 1164),
+--             :  Accellera VHDL-TC, and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This packages defines a standard for designers
+--             :  to use in describing the interconnection data types
+--             :  used in vhdl modeling.
+--             :
+--   Limitation:  The logic system defined in this package may
+--             :  be insufficient for modeling switched transistors,
+--             :  since such a requirement is out of the scope of this
+--             :  effort. Furthermore, mathematics, primitives,
+--             :  timing standards, etc. are considered orthogonal
+--             :  issues as it relates to this package and are therefore
+--             :  beyond the scope of this effort.
+--             :
+--   Note      :  This package may be modified to include additional data
+--             :  required by tools, but it must in no way change the
+--             :  external interfaces or simulation behavior of the
+--             :  description. It is permissible to add comments and/or
+--             :  attributes to the package declarations, but not to change
+--             :  or delete any original lines of the package declaration.
+--             :  The package body may be changed only in accordance with
+--             :  the terms of Clause 16 of this standard.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1.5 $
+-- $Date: 2016/04/08 07:56:22 $
+-- --------------------------------------------------------------------
+
+use STD.TEXTIO.all;
+
+package std_logic_1164 is
+
+  -------------------------------------------------------------------    
+  -- logic state system  (unresolved)
+  -------------------------------------------------------------------    
+  type STD_ULOGIC is ( 'U',             -- Uninitialized
+                       'X',             -- Forcing  Unknown
+                       '0',             -- Forcing  0
+                       '1',             -- Forcing  1
+                       'Z',             -- High Impedance   
+                       'W',             -- Weak     Unknown
+                       'L',             -- Weak     0       
+                       'H',             -- Weak     1       
+                       '-'              -- Don't care
+                       );
+
+  -------------------------------------------------------------------    
+  -- Directives for synthesis of std_ulogic.
+  -- Declare the type encoding attribute and set the value for std_ulogic
+  -- Directives for the resolution function and all other function are 
+  -- in the package body
+  -------------------------------------------------------------------    
+  ATTRIBUTE logic_type_encoding : string ;
+  ATTRIBUTE logic_type_encoding of std_ulogic:type is
+    -- ('U','X','0','1','Z','W','L','H','-') 
+    ('X','X','0','1','Z','X','0','1','X') ; 
+
+  -------------------------------------------------------------------    
+  -- Declare the synthesis-directive attribute; to be set on 
+  -- basic functions that are difficult for synthesis 
+  -------------------------------------------------------------------    
+  ATTRIBUTE synthesis_return : string ;
+  ATTRIBUTE is_signed : boolean ;
+
+  -------------------------------------------------------------------    
+  -- unconstrained array of std_ulogic for use with the resolution function
+  -- and for use in declaring signal arrays of unresolved elements
+  -------------------------------------------------------------------    
+  type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
+
+  -------------------------------------------------------------------    
+  -- resolution function
+  -------------------------------------------------------------------    
+  function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+
+
+  -------------------------------------------------------------------    
+  -- logic state system  (resolved)
+  -------------------------------------------------------------------    
+  subtype STD_LOGIC is resolved STD_ULOGIC;
+
+  -- Xilinx begin (160405)
+  -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+  type STD_LOGIC_VECTOR_93 is array (NATURAL range <>) of STD_LOGIC ;
+  -- Xilinx end (160405)
+  -------------------------------------------------------------------    
+  -- unconstrained array of resolved std_ulogic for use in declaring
+  -- signal arrays of resolved elements
+  -------------------------------------------------------------------    
+  subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
+
+  -------------------------------------------------------------------    
+  -- common subtypes
+  -------------------------------------------------------------------    
+  subtype X01 is resolved STD_ULOGIC range 'X' to '1';    -- ('X','0','1') 
+  subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z';   -- ('X','0','1','Z') 
+  subtype UX01 is resolved STD_ULOGIC range 'U' to '1';   -- ('U','X','0','1') 
+  subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z';  -- ('U','X','0','1','Z') 
+
+  -------------------------------------------------------------------    
+  -- overloaded logical operators
+  -------------------------------------------------------------------    
+
+  function "and"  (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
+  function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
+  function "or"   (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
+  function "nor"  (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
+  function "xor"  (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
+  function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
+  function "not"  (l : STD_ULOGIC) return UX01;
+
+  -------------------------------------------------------------------    
+  -- vectorized overloaded logical operators
+  -------------------------------------------------------------------    
+  function "and"  (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function "or"   (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function "nor"  (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function "xor"  (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function "not"  (l    : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+  function "and"  (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+  function "and"  (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+  function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+  function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+  function "or"   (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+  function "or"   (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+  function "nor"  (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+  function "nor"  (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+  function "xor"  (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+  function "xor"  (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+  function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
+  function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+  function "and"  (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  function "or"   (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  function "nor"  (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  function "xor"  (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+  function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+
+  -------------------------------------------------------------------
+  -- shift operators
+  -------------------------------------------------------------------
+
+  function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
+  function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
+  function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
+  function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
+
+  -------------------------------------------------------------------
+  -- conversion functions
+  -------------------------------------------------------------------
+  function To_bit       (s : STD_ULOGIC; xmap : BIT        := '0') return BIT;
+  function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
+
+  function To_StdULogic       (b : BIT) return STD_ULOGIC;
+  function To_StdLogicVector  (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
+  function To_StdLogicVector  (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
+  function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
+  function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+
+  alias To_Bit_Vector is
+    To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
+  alias To_BV is
+    To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
+  
+  alias To_Std_Logic_Vector is
+    To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
+  alias To_SLV is
+    To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
+
+  alias To_Std_Logic_Vector is
+    To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
+  alias To_SLV is
+    To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
+
+  alias To_Std_ULogic_Vector is
+    To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
+  alias To_SULV is
+    To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
+
+  alias To_Std_ULogic_Vector is
+    To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
+  alias To_SULV is
+    To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
+
+  -------------------------------------------------------------------    
+  -- strength strippers and type convertors
+  -------------------------------------------------------------------    
+
+  function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
+    return STD_ULOGIC_VECTOR;
+  function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
+    return STD_ULOGIC;
+  function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
+    return STD_ULOGIC_VECTOR;
+  function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
+    return STD_ULOGIC;
+
+  function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function To_X01 (s : STD_ULOGIC) return X01;
+  function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
+  function To_X01 (b : BIT) return X01;
+
+  function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function To_X01Z (s : STD_ULOGIC) return X01Z;
+  function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
+  function To_X01Z (b : BIT) return X01Z;
+
+  function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
+  function To_UX01 (s : STD_ULOGIC) return UX01;
+  function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
+  function To_UX01 (b : BIT) return UX01;
+
+  function "??" (l : STD_ULOGIC) return BOOLEAN;
+
+  -------------------------------------------------------------------    
+  -- edge detection
+  -------------------------------------------------------------------    
+  function rising_edge  (signal s : STD_ULOGIC) return BOOLEAN;
+  function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;
+
+  -------------------------------------------------------------------    
+  -- object contains an unknown
+  -------------------------------------------------------------------    
+  function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
+  function Is_X (s : STD_ULOGIC) return BOOLEAN;
+
+  -------------------------------------------------------------------
+  -- matching relational operators
+  -------------------------------------------------------------------
+  -- the following operations are predefined
+
+  --  function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
+  --  function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+
+  --  function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
+  --  function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
+
+  --  function "?<" (l, r  : STD_ULOGIC) return STD_ULOGIC;
+  --  function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
+  --  function "?>" (l, r  : STD_ULOGIC) return STD_ULOGIC;
+  --  function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;
+  
+  -------------------------------------------------------------------
+  -- string conversion and write operations
+  -------------------------------------------------------------------
+  -- the following operations are predefined
+
+  -- function to_string (value : STD_ULOGIC) return STRING;
+  -- function to_string (value : STD_ULOGIC_VECTOR) return STRING;
+
+  -- explicitly defined operations
+
+  alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
+  alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
+  function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
+  alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
+  function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
+  alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
+
+  procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
+  procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
+
+  procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
+  procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
+
+  procedure WRITE (L         : inout LINE; VALUE : in STD_ULOGIC;
+  JUSTIFIED : in    SIDE := right; FIELD : in WIDTH := 0);
+
+  procedure WRITE (L         : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+  JUSTIFIED : in    SIDE := right; FIELD : in WIDTH := 0);
+
+  alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+  alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
+  alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+  alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
+
+  procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
+  procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
+  alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+  alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
+
+  procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
+  procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
+  alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+  alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
+
+  alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+  alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+  
+  procedure OWRITE (L         : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+  JUSTIFIED : in    SIDE := right; FIELD : in WIDTH := 0);
+  alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+  
+  procedure HWRITE (L         : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
+  JUSTIFIED : in    SIDE := right; FIELD : in WIDTH := 0);
+  alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+
+  -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+  -- Xilinx begin (160405)
+  -- type STD_LOGIC_VECTOR_93 is array (NATURAL range <>) of STD_LOGIC ;
+  -- Xilinx end (160405)
+
+  -- Viper #10710: Following two are redundant. To_StdULogicVector and 
+  -- To_StdLogicVector already declared before w.r.t. STD_LOGIC_VECTOR 
+  -- function To_StdULogicVector (s : STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR;
+  -- function To_StdLogicVector  (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93;
+
+  FUNCTION "and"   ( l, r : std_logic_vector_93  ) RETURN std_logic_vector_93 ;
+  FUNCTION "nand"  ( l, r : std_logic_vector_93  ) RETURN std_logic_vector_93 ;
+  FUNCTION "or"    ( l, r : std_logic_vector_93  ) RETURN std_logic_vector_93 ;
+  FUNCTION "nor"   ( l, r : std_logic_vector_93  ) RETURN std_logic_vector_93 ;
+  FUNCTION "xor"   ( l, r : std_logic_vector_93  ) RETURN std_logic_vector_93 ;
+  FUNCTION "xnor"  ( l, r : std_logic_vector_93  ) RETURN std_logic_vector_93 ;
+  FUNCTION "not"   ( l : std_logic_vector_93  ) RETURN std_logic_vector_93 ;
+  FUNCTION To_bitvector ( s : std_logic_vector_93 ; xmap : BIT := '0') RETURN BIT_VECTOR ;
+  FUNCTION To_X01  ( s : std_logic_vector_93  ) RETURN  std_logic_vector_93 ;
+  FUNCTION To_X01  ( b : BIT_VECTOR        ) RETURN  std_logic_vector_93 ;
+  FUNCTION To_X01Z ( s : std_logic_vector_93  ) RETURN  std_logic_vector_93 ;
+  FUNCTION To_X01Z ( b : BIT_VECTOR        ) RETURN  std_logic_vector_93 ;
+  FUNCTION To_UX01 ( s : std_logic_vector_93  ) RETURN  std_logic_vector_93 ;
+  FUNCTION To_UX01 ( b : BIT_VECTOR        ) RETURN  std_logic_vector_93 ;
+  FUNCTION Is_X    ( s : std_logic_vector_93  ) RETURN  BOOLEAN ;
+
+  -- Read and Write procedures for STD_LOGIC_VECTOR_93
+  procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93);
+  procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN);
+  procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93;
+                  JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
+
+  procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93);
+  procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN);
+  procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93;
+                   JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
+
+  procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93);
+  procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN);
+  procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93;
+                   JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
+  -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+
+end package std_logic_1164;

resources/dide-lsp/static/vhdl_std_lib/ieee_2008/std_logic_textio.vhdl

@@ -0,0 +1,66 @@
+-- --------------------------------------------------------------------
+--
+-- Copyright © 2008 by IEEE. All rights reserved.
+--
+-- This source file is an essential part of IEEE Std 1076-2008, 
+-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This
+-- source file may be used and distributed without restriction.
+-- Modifications to this source file as permitted in IEEE Std 1076-2008
+-- may also be made and distributed. All other uses require permission
+-- from the IEEE Standards Department(stds-ipr@ieee.org). 
+-- All other rights reserved.
+-- 
+--   Title     :  Standard multivalue logic package
+--             :  (STD_LOGIC_TEXTIO package declaration)
+--             :
+--   Library   :  This package shall be compiled into a library
+--             :  symbolically named IEEE.
+--             :
+--   Developers:  Accellera VHDL-TC and IEEE P1076 Working Group
+--             :
+--   Purpose   :  This packages is provided as a replacement for non-standard
+--             :  implementations of the package provided by implementers of
+--             :  previous versions of this standard. The declarations that
+--             :  appeared in those non-standard implementations appear in the
+--             :  package STD_LOGIC_1164 in this standard.
+--             :
+--   Note      :  No declarations or definitions shall be included in,
+--             :  or excluded from this package.
+--             :
+-- --------------------------------------------------------------------
+-- $Revision: 1.3 $
+-- $Date: 2016/04/07 08:10:20 $
+-- --------------------------------------------------------------------
+library ieee ; -- RD added.
+use STD.TEXTIO.all;
+use IEEE.std_logic_1164.all;
+
+PACKAGE std_logic_textio IS
+
+  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC];
+  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC, BOOLEAN];
+  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC_VECTOR];
+  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_LOGIC_VECTOR_93];
+  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+  alias READ  is IEEE.std_logic_1164.READ [LINE, STD_LOGIC_VECTOR_93, BOOLEAN];
+  alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_ULOGIC, SIDE, WIDTH];
+  alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+  alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH];
+
+  alias HREAD  is IEEE.std_logic_1164.HREAD [LINE, STD_ULOGIC_VECTOR];
+  alias HREAD  is IEEE.std_logic_1164.HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+  alias HWRITE is IEEE.std_logic_1164.HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+
+  alias HREAD  is IEEE.std_logic_1164.HREAD [LINE, STD_LOGIC_VECTOR_93];
+  alias HREAD  is IEEE.std_logic_1164.HREAD [LINE, STD_LOGIC_VECTOR_93, BOOLEAN];
+  alias HWRITE is IEEE.std_logic_1164.HWRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH];
+
+  alias OREAD  is IEEE.std_logic_1164.OREAD [LINE, STD_ULOGIC_VECTOR];
+  alias OREAD  is IEEE.std_logic_1164.OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
+  alias OWRITE is IEEE.std_logic_1164.OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
+
+  alias OREAD  is IEEE.std_logic_1164.OREAD [LINE, STD_LOGIC_VECTOR_93];
+  alias OREAD  is IEEE.std_logic_1164.OREAD [LINE, STD_LOGIC_VECTOR_93, BOOLEAN];
+  alias OWRITE is IEEE.std_logic_1164.OWRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH];
+
+END PACKAGE std_logic_textio;

resources/dide-lsp/static/vhdl_std_lib/std/env.vhd

@@ -0,0 +1,11 @@
+-- Package env as defined by IEEE 1076-2008
+
+package env is
+  procedure stop(status : integer);
+  procedure stop;
+
+  procedure finish(status : integer);
+  procedure finish;
+
+  function resolution_limit return delay_length;
+end package;

resources/dide-lsp/static/vhdl_std_lib/std/standard.vhd

@@ -0,0 +1,94 @@
+-- Package standard as defined by IEEE 1076-2008
+
+package standard is
+
+  -- Predefined enumeration types:
+  type BOOLEAN is (FALSE, TRUE);
+  type BIT is ('0', '1');
+
+  type CHARACTER is (
+    NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
+    BS,  HT,  LF,  VT,  FF,  CR,  SO,  SI,
+    DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
+    CAN, EM,  SUB, ESC, FSP, GSP, RSP, USP,
+
+    ' ', '!', '"', '#', '$', '%', '&', ''',
+    '(', ')', '*', '+', ',', '-', '.', '/',
+    '0', '1', '2', '3', '4', '5', '6', '7',
+    '8', '9', ':', ';', '<', '=', '>', '?',
+
+    '@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
+    'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
+    'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
+    'X', 'Y', 'Z', '[', '\', ']', '^', '_',
+
+    '`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
+    'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
+    'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
+    'x', 'y', 'z', '{', '|', '}', '~', DEL,
+
+    C128, C129, C130, C131, C132, C133, C134, C135,
+    C136, C137, C138, C139, C140, C141, C142, C143,
+    C144, C145, C146, C147, C148, C149, C150, C151,
+    C152, C153, C154, C155, C156, C157, C158, C159,
+
+    ' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
+    '¨', '©', 'ª', '«', '¬', '­', '®', '¯',
+    '°', '±', '²', '³', '´', 'µ', '¶', '·',
+    '¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
+    'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
+    'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
+    'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
+    'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
+    'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
+    'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
+    'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
+    'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ');
+
+  type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);
+  type INTEGER is range -2147483647 to 2147483647;
+  type REAL is range -1.7976931348623157e308 to 1.7976931348623157e308;
+
+  type TIME is range -9223372036854775807 to 9223372036854775807
+    units
+      fs; -- femtosecond
+      ps = 1000 fs; -- picosecond
+      ns = 1000 ps; -- nanosecond
+      us = 1000 ns; -- microsecond
+      ms = 1000 us; -- millisecond
+      sec = 1000 ms; -- second
+      min = 60 sec; -- minute
+      hr= 60 min; -- hour
+    end units;
+
+  subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
+  impure function NOW return DELAY_LENGTH;
+
+  subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
+  subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
+
+  type STRING is array (POSITIVE range <>) of CHARACTER;
+
+  type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
+  type BIT_VECTOR is array (NATURAL range <>) of BIT;
+  type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
+  type REAL_VECTOR is array (NATURAL range <>) of REAL;
+  type TIME_VECTOR is array (NATURAL range <>) of TIME;
+
+  type FILE_OPEN_KIND is (READ_MODE,
+                          WRITE_MODE,
+                          APPEND_MODE);
+
+  type FILE_OPEN_STATUS is (OPEN_OK,
+                            STATUS_ERROR,
+                            NAME_ERROR,
+                            MODE_ERROR);
+
+  attribute FOREIGN: STRING;
+
+  function RISING_EDGE(signal S: BOOLEAN) return BOOLEAN;
+  function RISING_EDGE(signal B: BIT) return BOOLEAN;
+  function FALLING_EDGE(signal S: BOOLEAN) return BOOLEAN;
+  function FALLING_EDGE(signal B: BIT) return BOOLEAN;
+
+end package;

resources/dide-lsp/static/vhdl_std_lib/std/textio.vhd

@@ -0,0 +1,73 @@
+-- Package texio as defined by IEEE 1076-2008
+
+package textio is
+  type LINE is access STRING;
+  type TEXT is file of STRING;
+
+  procedure FILE_REWIND (file F: TEXT);
+  function  FILE_MODE (file F: TEXT) return FILE_OPEN_KIND;
+  function  FILE_SIZE (file F: TEXT) return INTEGER;
+
+  type SIDE is (RIGHT, LEFT);
+  subtype WIDTH is NATURAL; -- For specifying widths of output fields.
+
+  function JUSTIFY (VALUE: STRING; JUSTIFIED: SIDE := RIGHT; FIELD: WIDTH := 0 ) return STRING;
+  -- Standard text files:
+  file INPUT: TEXT open READ_MODE is "STD_INPUT";
+  file OUTPUT: TEXT open WRITE_MODE is "STD_OUTPUT";
+
+  -- Input routines for standard types:
+  procedure READLINE (file F: TEXT; L: inout LINE);
+  procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out BIT);
+  procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out BIT_VECTOR);
+  procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out CHARACTER);
+  procedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out INTEGER);
+  procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out REAL);
+  procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out STRING);
+  procedure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN);
+  procedure READ (L: inout LINE; VALUE: out TIME);
+  procedure SREAD (L: inout LINE; VALUE: out STRING; STRLEN: out NATURAL);
+  alias STRING_READ is SREAD [LINE, STRING, NATURAL];
+  alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
+  alias BREAD is READ [LINE, BIT_VECTOR];
+  alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
+  alias BINARY_READ is READ [LINE, BIT_VECTOR];
+  procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
+  procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR);
+  alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
+  alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
+  procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
+  procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR);
+  alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
+  alias HEX_READ is HREAD [LINE, BIT_VECTOR];
+
+  -- Output routines for standard types:
+  procedure WRITELINE (file F: TEXT; L: inout LINE);
+  procedure TEE (file F: TEXT; L: inout LINE);
+  procedure WRITE (L: inout LINE; VALUE: in BIT; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
+  procedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
+  procedure WRITE (L: inout LINE; VALUE: in BOOLEAN; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
+  procedure WRITE (L: inout LINE; VALUE: in CHARACTER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
+  procedure WRITE (L: inout LINE; VALUE: in INTEGER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
+  procedure WRITE (L: inout LINE; VALUE: in REAL; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; DIGITS: in NATURAL:= 0);
+  procedure WRITE (L: inout LINE; VALUE: in REAL; FORMAT: in STRING);
+  procedure WRITE (L: inout LINE; VALUE: in STRING; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
+  procedure WRITE (L: inout LINE; VALUE: in TIME; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; UNIT: in TIME:= ns);
+  alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
+  alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
+  alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
+  alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
+  procedure OWRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
+  alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
+  procedure HWRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
+  alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
+
+end package;

resources/dide-lsp/static/vhdl_std_lib/synopsys/attributes.vhd

@@ -0,0 +1,213 @@
+----------------------------------------------------------------------------
+-- 
+-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc.  All rights reserved.
+-- 
+-- This source file may be used and distributed without restriction 
+-- provided that this copyright statement is not removed from the file 
+-- and that any derivative work contains this copyright notice.
+--
+--	Package name: ATTRIBUTES
+--
+--	Purpose: This package defines the attributes associated with
+--		 the Synopsys VHDL System Simulator and the HDL compiler.
+--		 The simulator specific attributes  are built into the
+--		 the analyzer, so this source should not be analyzed on 
+--		 the Synopsys VHDL System Simulator.  It is provided for 
+--		 reference and portability to other systems.
+--
+--	Author: JT, PH, GWH, RV
+--
+--	Modified. Added translate_off and translate_on pairs because
+--	HDL compiler does not use/support the simulator specific attributes 
+--	in this package.
+--
+--      Modified: Apr 30, 1996, PZ: Moved the three BC attributes
+--                (dont_unroll, variables, synthesis_type) to this package.
+--      Modified: Nov 25, 1996, PZ: Removed the three BC attributes
+--                (dont_unroll, variables, synthesis_type) from this package.
+--                They are now in the behavioral package again.
+--
+----------------------------------------------------------------------------
+-- Simulator specific attributes
+-----------------------------------------------------------------------
+--
+--  attributes for type conversion functions, SDF backannotation and 
+--  resolution functions
+--
+-----------------------------------------------------------------------
+
+package ATTRIBUTES is
+--synopsys translate_off
+	attribute CLOSELY_RELATED_TCF: boolean;
+	attribute PROPAGATE_VALUE: string;
+	attribute SDT_CONDITION: string;
+	attribute SDT_VALUE_NAME: string;
+	attribute SDT_VALUE: string;
+	attribute REFLEXIVE: boolean;
+	attribute COMMUTATIVE: boolean;
+	attribute ASSOCIATIVE: boolean;
+	attribute RESULT_INITIAL_VALUE: integer;
+	attribute TABLE_NAME: string;
+	attribute REAL_NAME: string;
+
+	attribute PRIVATE: boolean;
+	attribute UNPRIVATE: boolean;
+	attribute ASIC_CELL: boolean;
+	attribute DIVERT_MESSAGES: boolean;
+
+	-- Note:  type BUILTIN_TYPE and attributes BUILTIN and EXTRA_SPACE
+	--        will be phased out after Elroy.  This is to move towards
+	--        the upcoming '92 standard.
+
+ 	type BUILTIN_TYPE is (VHDL_SYSTEM_PRIMITIVE, LMSI, C_BEHAVIOR,
+			      VHDL_SYSTEM_PRIMITIVE_STD_LOGIC);
+ 	attribute BUILTIN: BUILTIN_TYPE;
+ 	attribute EXTRA_SPACE: positive;
+
+	-- Note:  ### For the '92 standard, attribute FOREIGN must be 
+	--        moved to package STANDARD.
+
+	attribute FOREIGN : STRING;
+
+	-- CLI (C Language Interface) attributes
+
+	type CLI_PIN_SENSITIVITY is (CLI_PASSIVE, CLI_EVENT, CLI_ACTIVE);
+
+	attribute CLI_ELABORATE   : STRING;	-- components only
+	attribute CLI_EVALUATE    : STRING;	-- components only
+	attribute CLI_ERROR       : STRING;	-- components only
+	attribute CLI_CLOSE       : STRING;	-- components only
+	attribute CLI_PIN         : CLI_PIN_SENSITIVITY; -- components only
+
+	attribute CLI_FUNCTION    : STRING;	-- functions only
+	attribute CLI_PROCEDURE   : STRING;	-- procedures only
+
+	attribute CLI_POSTPONED   : BOOLEAN;	-- components only
+
+	-- Logic Modeling Corporation (LMC) interface attributes:
+
+ 	type LMSI_DELAY_TYPE_TYPE is (TYPICAL, MINIMUM, MAXIMUM);
+	attribute LMSI_DELAY_TYPE : LMSI_DELAY_TYPE_TYPE;
+
+ 	type LMSI_TIMING_MEASUREMENT_TYPE is (DISABLED, ENABLED);
+ 	attribute LMSI_TIMING_MEASUREMENT: LMSI_TIMING_MEASUREMENT_TYPE;
+
+	type LMSI_LOG_TYPE is (DISABLED, ENABLED);
+	attribute LMSI_LOG: LMSI_LOG_TYPE;
+
+	type LMSI_DELAY_ED_TYPE is (ENABLED, DISABLED);
+	attribute LMSI_DELAY: LMSI_DELAY_ED_TYPE;
+
+	type LMSI_TIMING_VIOLATIONS_TYPE is (ENABLED, DISABLED);
+	attribute LMSI_TIMING_VIOLATIONS: LMSI_TIMING_VIOLATIONS_TYPE;
+
+	type LMSI_XPROP_TYPE is (DISABLED, ENABLED);
+	attribute LMSI_XPROP: LMSI_XPROP_TYPE;
+
+	type LMSI_XPROP_METHOD_TYPE is (PREVIOUS, HIGH, LOW, FLOAT);
+	attribute LMSI_XPROP_METHOD: LMSI_XPROP_METHOD_TYPE;
+
+	-- Zycad XP interface attributes:
+
+ 	type BACKPLANE_TYPE is (XP, VERILOG, VIP);
+ 	attribute BACKPLANE: BACKPLANE_TYPE;
+
+	-- Attribute to instantiate a Model Bank component in the Zycad
+	-- XP box.
+
+ 	type ENCRYPTION_TYPE is (MODELBANK);
+ 	attribute ENCRYPTION: ENCRYPTION_TYPE;
+
+	-- Attribute to specify the EDIF file for an architecture. This
+	-- attribute can be specified in architecture(s) where the structural
+	-- information is in EDIF and we want to use it. This should be used
+	-- in conjunction with BACKPLANE attribute.
+ 	attribute EDIF_FILE_FOR_THIS_ARCHITECTURE: string;
+	attribute VERILOG_FILES_FOR_THIS_ARCHITECTURE: string;
+
+	-- The following two attributes are used to specify the physical
+	-- filename of the EDIF file containing the definitions of cell(s) or
+	-- entity(s) from a package and the EDIF library name used in the
+	-- above EDIF file. 
+ 	attribute EDIF_LIBRARY_FILENAME: string;
+ 	attribute EDIF_LIBRARY_NAME: string;
+
+        -- XPMSW 
+  	-- XP attribute for a component which is described by a ZYCAD
+  	-- CBMOD.
+  	attribute ZYCAD_XP_CBMOD : BOOLEAN;
+
+	-- This attribute is used to specify the initialization file for
+	-- RAM(s) and ROM(s).
+ 	attribute MVL7_MEM_INITFILE: string;
+
+	-- attributes for the function units bus (funbus)
+	type FUNBUS_TYPE is (LAI,CBMOD);
+	attribute FUNBUS : FUNBUS_TYPE;
+
+        attribute CHANGE_SIMPLE_NAME : string;
+        attribute CHECKOUT_LICENSE : string;
+        attribute COMPILED_SYSTEM : boolean;
+        attribute USE_FULL_NAME : boolean;
+        attribute USE_SIMPLE_NAME : boolean;
+
+--synopsys translate_on
+--------------------------------------------------------------------
+-- HDL compiler specific Attributes
+        attribute async_set_reset : string;
+        attribute sync_set_reset : string;
+        attribute async_set_reset_local : string;
+        attribute sync_set_reset_local : string;
+        attribute async_set_reset_local_all : string;
+        attribute sync_set_reset_local_all : string;
+
+        attribute one_hot : string;
+        attribute one_cold : string;
+        attribute infer_mux : string;
+
+--------------------------------------------------------------------
+-- design compiler constraints and attributes
+	attribute ARRIVAL : REAL;
+	attribute DONT_TOUCH : BOOLEAN;
+	attribute DONT_TOUCH_NETWORK : BOOLEAN;
+	attribute DRIVE_STRENGTH : REAL;
+	attribute EQUAL : BOOLEAN;
+	attribute FALL_ARRIVAL : REAL;
+	attribute FALL_DRIVE : REAL;
+	attribute LOAD : REAL;
+	attribute LOGIC_ONE : BOOLEAN;
+	attribute LOGIC_ZERO : BOOLEAN;
+	attribute MAX_AREA : REAL;
+	attribute MAX_DELAY : REAL;
+	attribute MAX_FALL_DELAY : REAL;
+	attribute MAX_RISE_DELAY : REAL;
+	attribute MAX_TRANSITION : REAL;
+	attribute MIN_DELAY : REAL;
+	attribute MIN_FALL_DELAY : REAL;
+	attribute MIN_RISE_DELAY : REAL;
+	attribute OPPOSITE : BOOLEAN;
+	attribute RISE_ARRIVAL : REAL;
+	attribute RISE_DRIVE : REAL;
+	attribute UNCONNECTED : BOOLEAN;
+	attribute INFER_MULTIBIT : STRING;
+
+-- state machine attributes
+	attribute STATE_VECTOR : STRING;
+
+-- resource sharing attributes
+	subtype resource is integer;
+	attribute ADD_OPS : STRING;
+	attribute DONT_MERGE_WITH : STRING;
+	attribute MAP_TO_MODULE : STRING;
+	attribute IMPLEMENTATION : STRING;
+	attribute MAY_MERGE_WITH : STRING;
+	attribute OPS : STRING;
+
+-- general attributes
+	attribute ENUM_ENCODING : STRING;
+
+-- optimization attributes
+	attribute TRANSFORM_CONST_MULT : boolean;
+
+--
+end ATTRIBUTES;

resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_misc.vhd

@@ -0,0 +1,882 @@
+--------------------------------------------------------------------------
+--
+-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc.  All rights reserved.
+-- 
+-- This source file may be used and distributed without restriction 
+-- provided that this copyright statement is not removed from the file 
+-- and that any derivative work contains this copyright notice.
+--
+--	Package name: std_logic_misc
+--
+--	Purpose: This package defines supplemental types, subtypes, 
+--		 constants, and functions for the Std_logic_1164 Package.
+--
+--	Author:  GWH
+--
+--------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+library SYNOPSYS;
+use SYNOPSYS.attributes.all;
+
+
+package std_logic_misc is
+
+    -- output-strength types
+
+    type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1, 
+		      strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
+
+
+--synopsys synthesis_off
+
+    type MINOMAX is array (1 to 3) of TIME;
+    
+
+    ---------------------------------------------------------------------
+    --
+    -- functions for mapping the STD_(U)LOGIC according to STRENGTH
+    --
+    ---------------------------------------------------------------------
+
+    function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
+
+    function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
+
+    ---------------------------------------------------------------------
+    --
+    -- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
+    --
+    ---------------------------------------------------------------------
+
+    -- STD_ULOGIC_VECTOR is the base type of STD_LOGIC_VECTOR in 2008
+    -- So following function is redundant
+--synopsys synthesis_on
+    -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+    function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93;
+
+    function Drive (V: STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR;
+    -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+--synopsys synthesis_off
+
+    attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
+
+    ---------------------------------------------------------------------
+    --
+    -- conversion functions for sensing various types
+    -- (the second argument allows the user to specify the value to
+    --  be returned when the network is undriven)
+    --
+    ---------------------------------------------------------------------
+
+    function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
+
+    function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) 
+    					   return STD_LOGIC_VECTOR_93;
+    function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) 
+    					   return STD_ULOGIC_VECTOR;
+
+--     function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC) 
+--     					   return STD_LOGIC_VECTOR_93;
+--     function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC) 
+--     					   return STD_ULOGIC_VECTOR;
+
+--synopsys synthesis_on
+
+
+    ---------------------------------------------------------------------
+    --
+    --	Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
+    --
+    --	Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
+    --
+    --	Mapping:	0, L --> 0
+    --			1, H --> 1
+    --			X, W --> vX if Xflag is TRUE
+    --			X, W --> 0  if Xflag is FALSE
+    --			Z --> vZ if Zflag is TRUE
+    --			Z --> 0  if Zflag is FALSE
+    --			U --> vU if Uflag is TRUE
+    --			U --> 0  if Uflag is FALSE
+    --			- --> vDC if DCflag is TRUE
+    --			- --> 0  if DCflag is FALSE
+    --
+    ---------------------------------------------------------------------
+
+    function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
+--synopsys synthesis_off
+    	; vX, vZ, vU, vDC: BIT := '0'; 
+    	  Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
+--synopsys synthesis_on
+    	) return BIT_VECTOR;
+
+    function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
+--synopsys synthesis_off
+    	; vX, vZ, vU, vDC: BIT := '0'; 
+    	  Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
+--synopsys synthesis_on
+    	) return BIT_VECTOR;
+    
+
+    ---------------------------------------------------------------------
+    --
+    --	Function: STD_ULOGICtoBIT
+    --
+    --	Purpose: Conversion function from STD_(U)LOGIC to BIT
+    --
+    --	Mapping:	0, L --> 0
+    --			1, H --> 1
+    --			X, W --> vX if Xflag is TRUE
+    --			X, W --> 0  if Xflag is FALSE
+    --			Z --> vZ if Zflag is TRUE
+    --			Z --> 0  if Zflag is FALSE
+    --			U --> vU if Uflag is TRUE
+    --			U --> 0  if Uflag is FALSE
+    --			- --> vDC if DCflag is TRUE
+    --			- --> 0  if DCflag is FALSE
+    --
+    ---------------------------------------------------------------------
+
+    function STD_ULOGICtoBIT (V: STD_ULOGIC
+--synopsys synthesis_off
+    	; vX, vZ, vU, vDC: BIT := '0'; 
+    	  Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
+--synopsys synthesis_on
+    	) return BIT;
+
+        --------------------------------------------------------------------
+    -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+        function AND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
+        function NAND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
+        function OR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
+        function NOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
+        function XOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
+        function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
+    
+        function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
+        function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
+        function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
+        function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
+        function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
+        function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
+    -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+    
+--synopsys synthesis_off
+	
+        function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
+        function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
+        function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
+
+        function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
+        function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
+
+--synopsys synthesis_on
+
+-- Synthesis Directive Attributes
+        attribute IS_SIGNED : BOOLEAN ;
+        attribute SYNTHESIS_RETURN : STRING ;	
+end;
+
+
+package body std_logic_misc is
+
+--synopsys synthesis_off
+
+    type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
+
+    --------------------------------------------------------------------
+    --
+    -- Truth tables for output strength --> STD_ULOGIC lookup
+    --
+    --------------------------------------------------------------------
+
+    -- truth table for output strength --> STD_ULOGIC lookup
+    constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE := 
+    --  ------------------------------------------------------------------
+    --  | X01  X0H  XL1  X0Z  XZ1  WLH  WLZ  WZH  W0H  WL1 | strn/ output|
+    --  ------------------------------------------------------------------
+        (('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'),  -- |   U   |
+         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   X   |
+         ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'),  -- |   0   |
+         ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'),  -- |   1   |
+         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   Z   |
+         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   W   |
+         ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'),  -- |   L   |
+         ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'),  -- |   H   |
+         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- |   -   |
+
+
+
+    --------------------------------------------------------------------
+    --
+    -- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
+    --
+    --------------------------------------------------------------------
+
+    -- truth table for output strength --> STD_ULOGIC lookup
+    constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE := 
+    --  ------------------------------------------------------------------
+    --  | X01  X0H  XL1  X0Z  XZ1  WLH  WLZ  WZH  W0H  WL1 | strn/ output|
+    --  ------------------------------------------------------------------
+        (('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'),  -- |   U   |
+         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   X   |
+         ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'),  -- |   0   |
+         ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'),  -- |   1   |
+         ('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'),  -- |   Z   |
+         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'),  -- |   W   |
+         ('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'),  -- |   L   |
+         ('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'),  -- |   H   |
+         ('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- |   -   |
+
+
+
+    ---------------------------------------------------------------------
+    --
+    -- functions for mapping the STD_(U)LOGIC according to STRENGTH
+    --
+    ---------------------------------------------------------------------
+
+    function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
+    begin
+    	return tbl_STRN_STD_ULOGIC(input, strn);
+    end strength_map;
+
+
+    function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
+    begin
+    	return tbl_STRN_STD_ULOGIC_Z(input, strn);
+    end strength_map_z;
+
+
+    ---------------------------------------------------------------------
+    --
+    -- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
+    --
+    ---------------------------------------------------------------------
+
+--synopsys synthesis_on
+    function Drive (V: STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR is
+      -- pragma built_in SYN_FEED_THRU
+      --synopsys synthesis_off
+    	alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V;
+      --synopsys synthesis_on
+        -- Added Synthesis Directive
+        variable result : STD_ULOGIC_VECTOR(V'length-1 downto 0) ;
+        attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
+    begin
+      --synopsys synthesis_off
+    	result := STD_ULOGIC_VECTOR(Value);
+        return result ;
+      --synopsys synthesis_on
+    end Drive;
+
+
+    function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93 is
+      -- pragma built_in SYN_FEED_THRU
+      --synopsys synthesis_off
+    	alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
+      --synopsys synthesis_on
+        -- Added Synthesis Directive
+        variable result : STD_LOGIC_VECTOR_93(V'length-1 downto 0) ;
+        attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
+    begin
+      --synopsys synthesis_off
+    	result := STD_LOGIC_VECTOR_93(Value);
+        return result ;
+      --synopsys synthesis_on
+    end Drive;
+--synopsys synthesis_off
+
+
+    ---------------------------------------------------------------------
+    --
+    -- conversion functions for sensing various types
+    --
+    -- (the second argument allows the user to specify the value to
+    --  be returned when the network is undriven)
+    --
+    ---------------------------------------------------------------------
+
+    function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) 
+    					        return STD_LOGIC is
+    begin
+    	if V = 'Z' then
+    		return vZ;
+    	else
+    		return V;
+    	end if;
+    end Sense;
+
+
+    function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) 
+    					return STD_LOGIC_VECTOR_93 is
+    	alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
+    	variable Result: STD_LOGIC_VECTOR_93 (V'length-1 downto 0);
+    begin
+    	for i in Value'range loop
+    		if ( Value(i) = 'Z' ) then
+    			Result(i) := vZ;
+    		else
+    			Result(i) := Value(i);
+    		end if;
+    	end loop;
+    	return Result;
+    end Sense;
+
+
+    function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC) 
+    					return STD_ULOGIC_VECTOR is
+    	alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
+    	variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
+    begin
+    	for i in Value'range loop
+    		if ( Value(i) = 'Z' ) then
+    			Result(i) := vZ;
+    		else
+    			Result(i) := Value(i);
+    		end if;
+    	end loop;
+    	return Result;
+    end Sense;
+
+
+--     function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC) 
+--     					return STD_LOGIC_VECTOR_93 is
+--     	alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V;
+--     	variable Result: STD_LOGIC_VECTOR_93 (V'length-1 downto 0);
+--     begin
+--     	for i in Value'range loop
+--     		if ( Value(i) = 'Z' ) then
+--     			Result(i) := vZ;
+--     		else
+--     			Result(i) := Value(i);
+--     		end if;
+--     	end loop;
+--     	return Result;
+--     end Sense;
+
+
+--     function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC) 
+--     					return STD_ULOGIC_VECTOR is
+--     	alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V;
+--     	variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
+--     begin
+--     	for i in Value'range loop
+--     		if ( Value(i) = 'Z' ) then
+--     			Result(i) := vZ;
+--     		else
+--     			Result(i) := Value(i);
+--     		end if;
+--     	end loop;
+--     	return Result;
+--     end Sense;
+
+    ---------------------------------------------------------------------
+    --
+    --	Function: STD_LOGIC_VECTORtoBIT_VECTOR
+    --
+    --	Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
+    --
+    --	Mapping:	0, L --> 0
+    --			1, H --> 1
+    --			X, W --> vX if Xflag is TRUE
+    --			X, W --> 0  if Xflag is FALSE
+    --			Z --> vZ if Zflag is TRUE
+    --			Z --> 0  if Zflag is FALSE
+    --			U --> vU if Uflag is TRUE
+    --			U --> 0  if Uflag is FALSE
+    --			- --> vDC if DCflag is TRUE
+    --			- --> 0  if DCflag is FALSE
+    --
+    ---------------------------------------------------------------------
+
+--synopsys synthesis_on
+    function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
+--synopsys synthesis_off
+    	; vX, vZ, vU, vDC: BIT := '0'; 
+    	  Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
+--synopsys synthesis_on
+    		   ) return BIT_VECTOR is
+      -- pragma built_in SYN_FEED_THRU
+    	variable Result: BIT_VECTOR (V'length-1 downto 0);
+
+        -- Added Synthesis Directive
+        attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
+--synopsys synthesis_off
+    	alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
+--synopsys synthesis_on
+    begin
+--synopsys synthesis_off
+    	for i in Value'range loop
+    		case Value(i) is
+    			when '0' | 'L' =>
+    				Result(i) := '0';
+    			when '1' | 'H' =>
+    				Result(i) := '1';
+    			when 'X' | 'W' =>
+    				if ( Xflag ) then
+    					Result(i) := vX;
+    				else
+    					Result(i) := '0';
+    			 		assert FALSE
+    				 	    report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
+    				 	    severity WARNING;
+    				end if;
+    			when others =>
+    				if ( Zflag ) then
+    					Result(i) := vZ;
+    				else
+    					Result(i) := '0';
+    					assert FALSE
+    					    report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
+    					    severity WARNING;
+    				end if;
+    		end case;
+    	end loop;
+    	return Result;
+--synopsys synthesis_on
+    end STD_LOGIC_VECTORtoBIT_VECTOR;
+
+
+
+
+    ---------------------------------------------------------------------
+    --
+    --	Function: STD_ULOGIC_VECTORtoBIT_VECTOR
+    --
+    --	Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
+    --
+    --	Mapping:	0, L --> 0
+    --			1, H --> 1
+    --			X, W --> vX if Xflag is TRUE
+    --			X, W --> 0  if Xflag is FALSE
+    --			Z --> vZ if Zflag is TRUE
+    --			Z --> 0  if Zflag is FALSE
+    --			U --> vU if Uflag is TRUE
+    --			U --> 0  if Uflag is FALSE
+    --			- --> vDC if DCflag is TRUE
+    --			- --> 0  if DCflag is FALSE
+    --
+    ---------------------------------------------------------------------
+
+    function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
+--synopsys synthesis_off
+    	; vX, vZ, vU, vDC: BIT := '0'; 
+    	  Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
+--synopsys synthesis_on
+    		   ) return BIT_VECTOR is
+      -- pragma built_in SYN_FEED_THRU
+    	variable Result: BIT_VECTOR (V'length-1 downto 0);
+
+        -- Added Synthesis Directive
+        attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
+--synopsys synthesis_off
+    	alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
+--synopsys synthesis_on
+    begin
+--synopsys synthesis_off
+    	for i in Value'range loop
+    		case Value(i) is
+    			when '0' | 'L' =>
+    				Result(i) := '0';
+    			when '1' | 'H' =>
+    				Result(i) := '1';
+    			when 'X' | 'W' =>
+    				if ( Xflag ) then
+    					Result(i) := vX;
+    				else
+    					Result(i) := '0';
+    			 		assert FALSE
+    				 	    report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
+    				 	    severity WARNING;
+    				end if;
+    			when others =>
+    				if ( Zflag ) then
+    					Result(i) := vZ;
+    				else
+    					Result(i) := '0';
+    					assert FALSE
+    					    report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
+    					    severity WARNING;
+    				end if;
+    		end case;
+    	end loop;
+    	return Result;
+--synopsys synthesis_on
+    end STD_ULOGIC_VECTORtoBIT_VECTOR;
+
+
+
+
+    ---------------------------------------------------------------------
+    --
+    --	Function: STD_ULOGICtoBIT
+    --
+    --	Purpose: Conversion function from STD_ULOGIC to BIT
+    --
+    --	Mapping:	0, L --> 0
+    --			1, H --> 1
+    --			X, W --> vX if Xflag is TRUE
+    --			X, W --> 0  if Xflag is FALSE
+    --			Z --> vZ if Zflag is TRUE
+    --			Z --> 0  if Zflag is FALSE
+    --			U --> vU if Uflag is TRUE
+    --			U --> 0  if Uflag is FALSE
+    --			- --> vDC if DCflag is TRUE
+    --			- --> 0  if DCflag is FALSE
+    --
+    ---------------------------------------------------------------------
+
+    function STD_ULOGICtoBIT (V: STD_ULOGIC
+--synopsys synthesis_off
+    	; vX, vZ, vU, vDC: BIT := '0'; 
+    	  Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
+--synopsys synthesis_on
+    		   ) return BIT is
+      -- pragma built_in SYN_FEED_THRU
+    	variable Result: BIT;
+
+        -- Added Synthesis Directive
+        attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
+    begin
+--synopsys synthesis_off
+    	case V is
+    		when '0' | 'L' =>
+    			Result := '0';
+    		when '1' | 'H' =>
+    			Result := '1';
+    		when 'X' | 'W' =>
+    			if ( Xflag ) then
+    				Result := vX;
+    			else
+    				Result := '0';
+    		 		assert FALSE
+    			 	    report "STD_ULOGICtoBIT: X --> 0"
+    			 	    severity WARNING;
+    			end if;
+    		when others =>
+    			if ( Zflag ) then
+    				Result := vZ;
+    			else
+    				Result := '0';
+    				assert FALSE
+    				    report "STD_ULOGICtoBIT: Z --> 0"
+    				    severity WARNING;
+    			end if;
+    	end case;
+    	return Result;
+--synopsys synthesis_on
+    end STD_ULOGICtoBIT;
+
+
+    --------------------------------------------------------------------------
+
+    -- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+    function AND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
+    variable result: STD_LOGIC;
+    -- Added Synthesis Directive
+    attribute SYNTHESIS_RETURN of result:variable is "REDUCE_AND" ;
+    begin
+    result := '1';
+    for i in ARG'range loop
+        result := result and ARG(i);
+    end loop;
+        return result;
+    end;
+
+    function NAND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
+    begin
+        return not AND_REDUCE(ARG);
+    end;
+
+    function OR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
+    variable result: STD_LOGIC;
+    -- Added Synthesis Directive
+    attribute SYNTHESIS_RETURN of result:variable is "REDUCE_OR" ;
+    begin
+    result := '0';
+    for i in ARG'range loop
+        result := result or ARG(i);
+    end loop;
+        return result;
+    end;
+
+    function NOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
+    begin
+        return not OR_REDUCE(ARG);
+    end;
+
+    function XOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
+    variable result: STD_LOGIC;
+    -- Added Synthesis Directive
+    attribute SYNTHESIS_RETURN of result:variable is "REDUCE_XOR" ;
+    begin
+    result := '0';
+    for i in ARG'range loop
+        result := result xor ARG(i);
+    end loop;
+        return result;
+    end;
+
+    function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
+    begin
+        return not XOR_REDUCE(ARG);
+    end;
+
+    function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
+    variable result: STD_LOGIC;
+    -- Added Synthesis Directive
+    attribute SYNTHESIS_RETURN of result:variable is "REDUCE_AND" ;
+    begin
+    result := '1';
+    for i in ARG'range loop
+        result := result and ARG(i);
+    end loop;
+        return result;
+    end;
+
+    function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
+    begin
+        return not AND_REDUCE(ARG);
+    end;
+
+    function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
+    variable result: STD_LOGIC;
+    -- Added Synthesis Directive
+    attribute SYNTHESIS_RETURN of result:variable is "REDUCE_OR" ;
+    begin
+    result := '0';
+    for i in ARG'range loop
+        result := result or ARG(i);
+    end loop;
+        return result;
+    end;
+
+    function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
+    begin
+        return not OR_REDUCE(ARG);
+    end;
+
+    function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
+    variable result: STD_LOGIC;
+    -- Added Synthesis Directive
+    attribute SYNTHESIS_RETURN of result:variable is "REDUCE_XOR" ;
+    begin
+    result := '0';
+    for i in ARG'range loop
+        result := result xor ARG(i);
+    end loop;
+        return result;
+    end;
+
+    function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
+    begin
+        return not XOR_REDUCE(ARG);
+    end;
+    -- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
+
+--synopsys synthesis_off
+	
+    function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
+	type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
+
+	-- truth table for tristate "buf" function (Enable active Low)
+          constant tbl_BUF3S: TRISTATE_TABLE := 
+          -- ----------------------------------------------------
+          -- | Input   U    X    0    1       | Enable Strength |
+          -- ---------------------------------|-----------------|
+        	   ((('U', 'U', 'U', 'U'),  --|   U       X01   |
+        	     ('U', 'X', 'X', 'X'),  --|   X       X01   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       X01   |
+        	     ('U', 'X', '0', '1')), --|   1       X01   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       X0H   |
+        	     ('U', 'X', 'X', 'X'),  --|   X       X0H   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       X0H   |
+        	     ('U', 'X', '0', 'H')), --|   1       X0H   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       XL1   |
+        	     ('U', 'X', 'X', 'X'),  --|   X       XL1   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       XL1   |
+        	     ('U', 'X', 'L', '1')), --|   1       XL1   |
+        	    (('U', 'U', 'U', 'Z'),  --|   U       X0Z   |
+        	     ('U', 'X', 'X', 'Z'),  --|   X       X0Z   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       X0Z   |
+        	     ('U', 'X', '0', 'Z')), --|   1       X0Z   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       XZ1   |
+        	     ('U', 'X', 'X', 'X'),  --|   X       XZ1   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       XZ1   |
+        	     ('U', 'X', 'Z', '1')), --|   1       XZ1   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       WLH   |
+        	     ('U', 'W', 'W', 'W'),  --|   X       WLH   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       WLH   |
+        	     ('U', 'W', 'L', 'H')), --|   1       WLH   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       WLZ   |
+        	     ('U', 'W', 'W', 'Z'),  --|   X       WLZ   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       WLZ   |
+        	     ('U', 'W', 'L', 'Z')), --|   1       WLZ   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       WZH   |
+        	     ('U', 'W', 'W', 'W'),  --|   X       WZH   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       WZH   |
+        	     ('U', 'W', 'Z', 'H')), --|   1       WZH   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       W0H   |
+        	     ('U', 'W', 'W', 'W'),  --|   X       W0H   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       W0H   |
+        	     ('U', 'W', '0', 'H')), --|   1       W0H   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       WL1   |
+        	     ('U', 'W', 'W', 'W'),  --|   X       WL1   |
+        	     ('Z', 'Z', 'Z', 'Z'),  --|   0       WL1   |
+        	     ('U', 'W', 'L', '1')));--|   1       WL1   |
+    begin
+	return tbl_BUF3S(Strn, Enable, Input);
+    end fun_BUF3S;
+
+
+    function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
+	type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
+
+	-- truth table for tristate "buf" function (Enable active Low)
+          constant tbl_BUF3SL: TRISTATE_TABLE := 
+          -- ----------------------------------------------------
+          -- | Input   U    X    0    1       | Enable Strength |
+          -- ---------------------------------|-----------------|
+        	   ((('U', 'U', 'U', 'U'),  --|   U       X01   |
+        	     ('U', 'X', 'X', 'X'),  --|   X       X01   |
+        	     ('U', 'X', '0', '1'),  --|   0       X01   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       X01   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       X0H   |
+        	     ('U', 'X', 'X', 'X'),  --|   X       X0H   |
+        	     ('U', 'X', '0', 'H'),  --|   0       X0H   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       X0H   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       XL1   |
+        	     ('U', 'X', 'X', 'X'),  --|   X       XL1   |
+        	     ('U', 'X', 'L', '1'),  --|   0       XL1   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       XL1   |
+        	    (('U', 'U', 'U', 'Z'),  --|   U       X0Z   |
+        	     ('U', 'X', 'X', 'Z'),  --|   X       X0Z   |
+        	     ('U', 'X', '0', 'Z'),  --|   0       X0Z   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       X0Z   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       XZ1   |
+        	     ('U', 'X', 'X', 'X'),  --|   X       XZ1   |
+        	     ('U', 'X', 'Z', '1'),  --|   0       XZ1   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       XZ1   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       WLH   |
+        	     ('U', 'W', 'W', 'W'),  --|   X       WLH   |
+        	     ('U', 'W', 'L', 'H'),  --|   0       WLH   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       WLH   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       WLZ   |
+        	     ('U', 'W', 'W', 'Z'),  --|   X       WLZ   |
+        	     ('U', 'W', 'L', 'Z'),  --|   0       WLZ   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       WLZ   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       WZH   |
+        	     ('U', 'W', 'W', 'W'),  --|   X       WZH   |
+        	     ('U', 'W', 'Z', 'H'),  --|   0       WZH   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       WZH   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       W0H   |
+        	     ('U', 'W', 'W', 'W'),  --|   X       W0H   |
+        	     ('U', 'W', '0', 'H'),  --|   0       W0H   |
+        	     ('Z', 'Z', 'Z', 'Z')), --|   1       W0H   |
+        	    (('U', 'U', 'U', 'U'),  --|   U       WL1   |
+        	     ('U', 'W', 'W', 'W'),  --|   X       WL1   |
+        	     ('U', 'W', 'L', '1'),  --|   0       WL1   |
+        	     ('Z', 'Z', 'Z', 'Z')));--|   1       WL1   |
+    begin
+	return tbl_BUF3SL(Strn, Enable, Input);
+    end fun_BUF3SL;
+
+
+    function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
+	type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
+
+	-- truth table for "MUX2x1" function
+	constant tbl_MUX2x1: MUX_TABLE :=
+	--------------------------------------------
+        --| In0  'U'  'X'  '0'  '1'      | Sel In1 |
+	--------------------------------------------
+	      ((('U', 'U', 'U', 'U'),  --| 'U' 'U' |
+	        ('U', 'U', 'U', 'U'),  --| 'X' 'U' |
+		('U', 'X', '0', '1'),  --| '0' 'U' |
+		('U', 'U', 'U', 'U')), --| '1' 'U' |
+	       (('U', 'X', 'U', 'U'),  --| 'U' 'X' |
+	        ('U', 'X', 'X', 'X'),  --| 'X' 'X' |
+		('U', 'X', '0', '1'),  --| '0' 'X' |
+		('X', 'X', 'X', 'X')), --| '1' 'X' |
+	       (('U', 'U', '0', 'U'),  --| 'U' '0' |
+	        ('U', 'X', '0', 'X'),  --| 'X' '0' |
+		('U', 'X', '0', '1'),  --| '0' '0' |
+		('0', '0', '0', '0')), --| '1' '0' |
+	       (('U', 'U', 'U', '1'),  --| 'U' '1' |
+	        ('U', 'X', 'X', '1'),  --| 'X' '1' |
+		('U', 'X', '0', '1'),  --| '0' '1' |
+		('1', '1', '1', '1')));--| '1' '1' |
+    begin
+	return tbl_MUX2x1(Input1, Sel, Input0);
+    end fun_MUX2x1;
+
+
+    function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
+	type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
+
+	----------------------------------------------------------------------------
+	--	The "tbl_MAJ23" truth table return 1 if the majority of three
+	--	inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
+	--	uninitialized.
+	----------------------------------------------------------------------------
+	constant tbl_MAJ23: MAJ23_TABLE :=
+        --------------------------------------------
+        --| In0  'U'  'X'  '0'  '1'      | In1 In2 |
+        --------------------------------------------
+              ((('U', 'U', 'U', 'U'),  --| 'U' 'U' |
+                ('U', 'U', 'U', 'U'),  --| 'X' 'U' |
+                ('U', 'U', '0', 'U'),  --| '0' 'U' |
+                ('U', 'U', 'U', '1')), --| '1' 'U' |
+               (('U', 'U', 'U', 'U'),  --| 'U' 'X' |
+                ('U', 'X', 'X', 'X'),  --| 'X' 'X' |
+                ('U', 'X', '0', 'X'),  --| '0' 'X' |
+                ('U', 'X', 'X', '1')), --| '1' 'X' |
+               (('U', 'U', '0', 'U'),  --| 'U' '0' |
+                ('U', 'X', '0', 'X'),  --| 'X' '0' |
+                ('0', '0', '0', '0'),  --| '0' '0' |
+                ('U', 'X', '0', '1')), --| '1' '0' |
+               (('U', 'U', 'U', '1'),  --| 'U' '1' |
+                ('U', 'X', 'X', '1'),  --| 'X' '1' |
+                ('U', 'X', '0', '1'),  --| '0' '1' |
+                ('1', '1', '1', '1')));--| '1' '1' |
+
+    begin
+	return tbl_MAJ23(Input0, Input1, Input2);
+    end fun_MAJ23;
+
+
+    function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
+        TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
+
+	-- truth table for "WiredX" function
+        -------------------------------------------------------------------    
+        -- resolution function
+        -------------------------------------------------------------------    
+        CONSTANT resolution_table : stdlogic_table := (
+        --      ---------------------------------------------------------
+        --      |  U    X    0    1    Z    W    L    H    -        |   |  
+        --      ---------------------------------------------------------
+                ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
+                ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
+                ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
+                ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
+                ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
+                ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
+                ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
+                ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
+                ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
+        -- Added Synthesis Directive
+        variable result : STD_LOGIC ;
+        attribute SYNTHESIS_RETURN of result:variable is "WIRED_THREE_STATE" ;
+    begin
+	result := resolution_table(Input0, Input1);
+        return result ;
+    end fun_WiredX;
+
+--synopsys synthesis_on
+	
+end;
+

resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_signed.vhd

@@ -0,0 +1,389 @@
+--------------------------------------------------------------------------
+--                                                                      --
+-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc.                     --
+--                                             All rights reserved.     --
+--                                                                      --
+-- This source file may be used and distributed without restriction     --
+-- provided that this copyright statement is not removed from the file  --
+-- and that any derivative work contains this copyright notice.         --
+--                                                                      --
+--	Package name: STD_LOGIC_SIGNED                                  --
+--                                 					--
+--									--
+--      Date:        09/11/91 KN                                        --
+--                   10/08/92 AMT change std_ulogic to signed std_logic --
+--		     10/28/92 AMT added signed functions, -, ABS	--
+--									--
+--	Purpose: 							--
+--	 A set of signed arithemtic, conversion,                        --
+--           and comparision functions for STD_LOGIC_VECTOR.            --
+--									--
+--	Note:	Comparision of same length std_logic_vector is defined  --
+--		in the LRM.  The interpretation is for unsigned vectors --
+--		This package will "overload" that definition.		--
+--									--
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+package STD_LOGIC_SIGNED is
+
+    function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
+    function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
+    function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+    function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
+    function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
+    function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+    function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+
+    function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+    function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; 
+    function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR; 
+
+    function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
+
+-- remove this since it is already in std_logic_arith
+--    function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
+
+
+    attribute foreign of "+"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_plus";
+    attribute foreign of "+"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_integer_plus";
+    attribute foreign of "+"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_signed_plus";
+    attribute foreign of "+"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_ulogic_plus";
+    attribute foreign of "+"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_signed_plus";
+
+    attribute foreign of "-"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_minus";
+    attribute foreign of "-"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_integer_minus";
+    attribute foreign of "-"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_signed_minus";
+    attribute foreign of "-"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_ulogic_minus";
+    attribute foreign of "-"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_signed_minus";
+
+    attribute foreign of "+"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unary_plus";
+    attribute foreign of "-"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_unary_minus";
+    attribute foreign of "*"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_mult";
+
+    attribute foreign of "<"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_less"; 
+    attribute foreign of "<"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_less";
+    attribute foreign of "<"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_less";
+
+    attribute foreign of "<="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_less_or_equal"; 
+    attribute foreign of "<="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_less_or_equal";
+    attribute foreign of "<="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_less_or_equal";
+
+    attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_greater"; 
+    attribute foreign of ">"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_greater";
+    attribute foreign of ">"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_greater";
+
+    attribute foreign of ">="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_greater_or_equal"; 
+    attribute foreign of ">="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_greater_or_equal";
+    attribute foreign of ">="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_greater_or_equal";
+
+    attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_equal"; 
+    attribute foreign of "="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_equal";
+    attribute foreign of "="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_equal";
+
+    attribute foreign of "/="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_not_equal"; 
+    attribute foreign of "/="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_not_equal";
+    attribute foreign of "/="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_not_equal";
+
+    attribute foreign of conv_integer[STD_LOGIC_VECTOR return integer]:function is "std_logic_arith_conv_signed_to_integer";
+
+    attribute foreign of SHL[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_signed_shl";
+    attribute foreign of SHR[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_signed_shr";
+    
+end STD_LOGIC_SIGNED;
+
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+package body STD_LOGIC_SIGNED is
+
+
+    function maximum(L, R: INTEGER) return INTEGER is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end;
+
+
+    function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_LOGIC_VECTOR (length-1 downto 0);
+    begin
+        result  := SIGNED(L) + SIGNED(R); -- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := SIGNED(L) + R; -- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        variable result  : STD_LOGIC_VECTOR (R'range);
+    begin
+        result  := L + SIGNED(R); -- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := SIGNED(L) + R; -- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        variable result  : STD_LOGIC_VECTOR (R'range);
+    begin
+        result  := L + SIGNED(R); -- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_LOGIC_VECTOR (length-1 downto 0);
+    begin
+        result  := SIGNED(L) - SIGNED(R); -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := SIGNED(L) - R; -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        variable result  : STD_LOGIC_VECTOR (R'range);
+    begin
+        result  := L - SIGNED(R); -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := SIGNED(L) - R; -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        variable result  : STD_LOGIC_VECTOR (R'range);
+    begin
+        result  := L - SIGNED(R); -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := + SIGNED(L); -- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := - SIGNED(L); -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := ABS( SIGNED(L));
+        return   std_logic_vector(result);
+    end;
+
+    function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to mult
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
+    begin
+        result  := SIGNED(L) * SIGNED(R); -- pragma label mult
+        return   std_logic_vector(result);
+    end;
+        
+    function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to lt
+        constant length: INTEGER := maximum(L'length, R'length);
+    begin
+        return   SIGNED(L) < SIGNED(R); -- pragma label lt
+    end;
+
+    function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+            -- pragma label_applies_to lt
+    begin
+        return   SIGNED(L) < R; -- pragma label lt
+    end;
+
+    function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to lt
+    begin
+        return   L < SIGNED(R); -- pragma label lt
+    end;
+
+    function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to leq
+    begin
+        return   SIGNED(L) <= SIGNED(R); -- pragma label leq
+    end;
+
+    function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+        -- pragma label_applies_to leq
+    begin
+        return   SIGNED(L) <= R; -- pragma label leq
+    end;
+
+    function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to leq
+    begin
+        return   L <= SIGNED(R); -- pragma label leq
+    end;
+
+    function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to gt
+    begin
+        return   SIGNED(L) > SIGNED(R); -- pragma label gt
+    end;
+
+    function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+        -- pragma label_applies_to gt
+    begin
+        return   SIGNED(L) > R; -- pragma label gt
+    end;
+
+    function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to gt
+    begin
+        return   L > SIGNED(R); -- pragma label gt
+    end;
+
+    function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to geq
+    begin
+        return   SIGNED(L) >= SIGNED(R); -- pragma label geq
+    end;
+
+    function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+        -- pragma label_applies_to geq
+    begin
+        return   SIGNED(L) >= R; -- pragma label geq
+    end;
+
+    function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to geq
+    begin
+        return   L >= SIGNED(R); -- pragma label geq
+    end;
+
+    function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+    begin
+        return   SIGNED(L) = SIGNED(R);
+    end;
+
+    function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+    begin
+        return   SIGNED(L) = R;
+    end;
+
+    function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+    begin
+        return   L = SIGNED(R);
+    end;
+
+    function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+    begin
+        return   SIGNED(L) /= SIGNED(R);
+    end;
+
+    function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+    begin
+        return   SIGNED(L) /= R;
+    end;
+
+    function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+    begin
+        return   L /= SIGNED(R);
+    end;
+
+    function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is 
+    begin
+       return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
+    end; 
+
+    function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+    begin
+       return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
+    end;
+ 
+
+
+--  This function converts std_logic_vector to a signed integer value
+--  using a conversion function in std_logic_arith
+    function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
+        variable result    : SIGNED(ARG'range);
+    begin
+        result    := SIGNED(ARG);
+        return   CONV_INTEGER(result);
+    end;
+end STD_LOGIC_SIGNED;
+
+

resources/dide-lsp/static/vhdl_std_lib/synopsys/std_logic_unsigned.vhd

@@ -0,0 +1,382 @@
+--------------------------------------------------------------------------
+--                                                                      --
+-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc.                     --
+--                                             All rights reserved.     --
+--                                                                      --
+-- This source file may be used and distributed without restriction     --
+-- provided that this copyright statement is not removed from the file  --
+-- and that any derivative work contains this copyright notice.         --
+--                                                                      --
+--	Package name: STD_LOGIC_UNSIGNED                                --
+--                                 					--
+--									--
+--      Date:        	09/11/92	KN				--
+--			10/08/92 	AMT				--
+--									--
+--	Purpose: 							--
+--	 A set of unsigned arithemtic, conversion,                      --
+--           and comparision functions for STD_LOGIC_VECTOR.            --
+--									--
+--	Note:  comparision of same length discrete arrays is defined	--
+--		by the LRM.  This package will "overload" those 	--
+--		definitions						--
+--									--
+--------------------------------------------------------------------------
+-- Modifications :
+-- Attributes added for Xilinx specific optimizations
+--------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+package STD_LOGIC_UNSIGNED is
+
+    function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
+    function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
+    function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+    function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
+    function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
+    function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+    function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+    function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+    function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+
+    function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
+    function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
+    function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+    function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
+
+    function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
+
+    --attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "ieee_std_logic_unsigned_greater_stdv_stdv"; 
+
+    --attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "ieee_std_logic_unsigned_equal_stdv_stdv";
+
+    attribute foreign of "+"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_plus";
+    attribute foreign of "+"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_integer_plus";
+    attribute foreign of "+"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_unsigned_plus";
+    attribute foreign of "+"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_ulogic_plus";
+    attribute foreign of "+"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_unsigned_plus";
+
+    attribute foreign of "-"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_minus";
+    attribute foreign of "-"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_integer_minus";
+    attribute foreign of "-"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_unsigned_minus";
+    attribute foreign of "-"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_ulogic_minus";
+    attribute foreign of "-"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_unsigned_minus";
+
+    attribute foreign of "+"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unary_plus";
+
+    attribute foreign of "*"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_mult";
+
+    attribute foreign of "<"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_less"; 
+    attribute foreign of "<"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_less";
+    attribute foreign of "<"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_less";
+
+    attribute foreign of "<="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_less_or_equal"; 
+    attribute foreign of "<="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_less_or_equal";
+    attribute foreign of "<="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_less_or_equal";
+
+    attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_greater"; 
+    attribute foreign of ">"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_greater";
+    attribute foreign of ">"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_greater";
+
+    attribute foreign of ">="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_greater_or_equal"; 
+    attribute foreign of ">="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_greater_or_equal";
+    attribute foreign of ">="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_greater_or_equal";
+
+
+    attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_equal"; 
+    attribute foreign of "="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_equal";
+    attribute foreign of "="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_equal";
+
+    attribute foreign of "/="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_not_equal"; 
+    attribute foreign of "/="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_not_equal";
+    attribute foreign of "/="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_not_equal";
+
+    attribute foreign of conv_integer[STD_LOGIC_VECTOR return integer]:function is "std_logic_arith_conv_unsigned_to_integer";
+
+    attribute foreign of SHL[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_unsigned_shl";
+    attribute foreign of SHR[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_unsigned_shr";
+                                                                                            
+-- remove this since it is already in std_logic_arith
+--    function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
+
+end STD_LOGIC_UNSIGNED;
+
+
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+package body STD_LOGIC_UNSIGNED is
+
+
+    function maximum(L, R: INTEGER) return INTEGER is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end;
+
+
+    function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_LOGIC_VECTOR (length-1 downto 0);
+    begin
+        result  := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := UNSIGNED(L) + R;-- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        variable result  : STD_LOGIC_VECTOR (R'range);
+    begin
+        result  := L + UNSIGNED(R);-- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to plus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := UNSIGNED(L) + R;-- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+            -- pragma label_applies_to plus
+    variable result  : STD_LOGIC_VECTOR (R'range);
+    begin
+        result  := L + UNSIGNED(R);-- pragma label plus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_LOGIC_VECTOR (length-1 downto 0);
+    begin
+        result  := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := UNSIGNED(L) - R; -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        variable result  : STD_LOGIC_VECTOR (R'range);
+    begin
+        result  := L - UNSIGNED(R);  -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := UNSIGNED(L) - R;
+        return   std_logic_vector(result);
+    end;
+
+    function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to minus
+        variable result  : STD_LOGIC_VECTOR (R'range);
+    begin
+        result  := L - UNSIGNED(R);  -- pragma label minus
+        return   std_logic_vector(result);
+    end;
+
+    function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        variable result  : STD_LOGIC_VECTOR (L'range);
+    begin
+        result  := + UNSIGNED(L);
+        return   std_logic_vector(result);
+    end;
+
+    function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+        -- pragma label_applies_to mult
+        constant length: INTEGER := maximum(L'length, R'length);
+        variable result  : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
+    begin
+        result  := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
+        return   std_logic_vector(result);
+    end;
+        
+    function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to lt
+        constant length: INTEGER := maximum(L'length, R'length);
+    begin
+        return   UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
+    end;
+
+    function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+        -- pragma label_applies_to lt
+    begin
+        return   UNSIGNED(L) < R; -- pragma label lt
+    end;
+
+    function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to lt
+    begin
+        return   L < UNSIGNED(R); -- pragma label lt
+    end;
+
+    function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+       -- pragma label_applies_to leq
+    begin
+        return   UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
+    end;
+
+    function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+       -- pragma label_applies_to leq
+    begin
+        return   UNSIGNED(L) <= R; -- pragma label leq
+    end;
+
+    function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+       -- pragma label_applies_to leq
+    begin
+        return   L <= UNSIGNED(R); -- pragma label leq
+    end;
+
+    function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to gt
+    begin
+        return   UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
+    end;
+
+    function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+        -- pragma label_applies_to gt
+    begin
+        return   UNSIGNED(L) > R; -- pragma label gt
+    end;
+
+    function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to gt
+    begin
+        return   L > UNSIGNED(R); -- pragma label gt
+    end;
+
+    function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to geq
+    begin
+        return   UNSIGNED(L) >= UNSIGNED(R);  -- pragma label geq
+    end;
+
+    function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+        -- pragma label_applies_to geq
+    begin
+        return   UNSIGNED(L) >= R;  -- pragma label geq
+    end;
+
+    function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+        -- pragma label_applies_to geq
+    begin
+        return   L >= UNSIGNED(R);  -- pragma label geq
+    end;
+
+    function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+    begin
+        return   UNSIGNED(L) = UNSIGNED(R);
+    end;
+
+    function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+    begin
+        return   UNSIGNED(L) = R;
+    end;
+
+    function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+    begin
+        return   L = UNSIGNED(R);
+    end;
+
+    function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
+    begin
+        return   UNSIGNED(L) /= UNSIGNED(R);
+    end;
+
+    function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
+    begin
+        return   UNSIGNED(L) /= R;
+    end;
+
+    function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
+    begin
+        return   L /= UNSIGNED(R);
+    end;
+
+    function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
+        variable result    : UNSIGNED(ARG'range);
+    begin
+        result    := UNSIGNED(ARG);
+        return   CONV_INTEGER(result);
+    end;
+    function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+    begin
+       return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
+    end;
+ 
+    function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
+    begin
+       return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
+    end;
+
+
+-- remove this since it is already in std_logic_arith
+    --function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
+        --variable result1 : UNSIGNED (SIZE-1 downto 0);
+        --variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
+    --begin
+        --result1 := CONV_UNSIGNED(ARG,SIZE);
+        --return   std_logic_vector(result1);
+    --end;
+
+
+end STD_LOGIC_UNSIGNED;
+
+

resources/dide-lsp/static/vhdl_std_lib/unifast/primitive/vhdl_analyze_order

@@ -0,0 +1,3 @@
+DSP48E1.vhd
+MMCME2_ADV.vhd
+PLLE2_ADV.vhd

resources/dide-lsp/static/vhdl_std_lib/unimacro/ADDMACC_MACRO.vhd

@@ -0,0 +1,453 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2015 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 2015.3
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for DSP48
+-- /___/   /\     Filename : ADDMACC_MACRO.vhd
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Revision:
+--    04/18/08 - Initial version.
+--    04/09/15 - 852167 - align with verilog
+-- End Revision
+
+----- CELL ADDMACC_MACRO -----
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+
+entity ADDMACC_MACRO is
+  generic ( 
+            DEVICE : string := "VIRTEX6";
+            LATENCY : integer := 4;
+            WIDTH_PREADD : integer := 25;
+            WIDTH_MULTIPLIER : integer := 18;
+            WIDTH_PRODUCT : integer := 48
+       );
+
+  port (
+      PRODUCT : out std_logic_vector(WIDTH_PRODUCT-1 downto 0);
+      CARRYIN : in std_logic;  
+      CE : in std_logic;
+      CLK : in std_logic;   
+      MULTIPLIER : in std_logic_vector(WIDTH_MULTIPLIER-1 downto 0);   
+      LOAD : in std_logic;   
+      LOAD_DATA : in std_logic_vector(WIDTH_PRODUCT-1 downto 0);
+      PREADD1 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
+      PREADD2 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
+      RST : in std_logic
+     );   
+end entity ADDMACC_MACRO;
+
+architecture addmacc of ADDMACC_MACRO is
+  function CheckDevice (
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write ( Message, DEVICE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" VIRTEX6, SPARTAN6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckWidthPreadd (
+    width : in integer;
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (width > 0 and width <= 25) then
+      func_val := true;
+      else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_PREADD : ") );
+      write ( Message, WIDTH_PREADD);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 25 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+      end if;
+    -- begin s1
+    else
+      if (DEVICE = "SPARTAN6" and width > 0 and width <= 18) then
+      func_val := true;
+      else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_PREADD : ") );
+      write ( Message, WIDTH_PREADD);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 18 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+      end if;
+    -- end s1
+    end if;
+    return func_val;
+  end;
+  function GetWidthPreadd (
+    device : in string
+    ) return integer is
+    variable func_val : integer;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      func_val := 25;
+    else
+      func_val := 18;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+
+  function CheckWidthMult (
+    width : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (width > 0 and width <= 18 ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_MULTPLIER : ") );
+      write ( Message, WIDTH_MULTIPLIER);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 18 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckWidthProd (
+    width : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (width > 0 and width <= 48 ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_PRODUCT : ") );
+      write ( Message, WIDTH_PRODUCT);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 48 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+   function GetABREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 2 or LATENCY = 3) then
+      func_width := 1;
+    elsif (LATENCY = 4 ) then
+      func_width := 2;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+   function GetABREG1_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 2 or LATENCY = 3 or LATENCY = 4) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetABREG0_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 4) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetMREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 3 or LATENCY = 4 ) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetPREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3 or LATENCY = 4 ) then
+      func_width := 1;
+    else
+      func_width := 0;
+      write( Message, STRING'("Illegal value of Attribute LATENCY : ") );
+      write ( Message, LATENCY);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 4 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_width;
+  end;
+
+  function GetOPMODE_IN (
+    device : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      func_width := 7;
+    elsif (DEVICE = "SPARTAN6") then
+      func_width := 8;
+    else
+      func_width := 8;
+    end if;
+    return func_width;
+  end;
+
+--Signal Declarations:   
+
+   constant OPMODE_WIDTH : integer := GetOPMODE_IN(DEVICE);
+   constant ChkDevice : boolean := CheckDevice(DEVICE);
+   constant ChkWidthPreAdd : boolean := CheckWidthPreAdd(WIDTH_PREADD, DEVICE);
+   constant MaxWidthPreAdd : integer := GetWidthPreAdd(DEVICE);
+   constant ChkWidthMult : boolean := CheckWidthMult(WIDTH_MULTIPLIER);
+   constant ChkWidthProd : boolean := CheckWidthProd(WIDTH_PRODUCT);
+   constant AREG_IN : integer := GetABREG_IN(LATENCY);
+   constant BREG_IN : integer := GetABREG_IN(LATENCY);
+   constant A0REG_IN : integer := GetABREG0_IN(LATENCY);
+   constant B0REG_IN : integer := GetABREG0_IN(LATENCY);
+   constant A1REG_IN : integer := GetABREG1_IN(LATENCY);
+   constant B1REG_IN : integer := GetABREG1_IN(LATENCY);
+   constant MREG_IN : integer := GetMREG_IN(LATENCY);
+   constant PREG_IN : integer := GetPREG_IN(LATENCY);
+
+   signal OPMODE_IN :  std_logic_vector((OPMODE_WIDTH-1) downto 0);
+   signal PREADD1_IN :  std_logic_vector(29 downto 0) := "000000000000000000000000000000";
+   signal PREADD2_IN :  std_logic_vector(24 downto 0) := "0000000000000000000000000";
+   signal MULTIPLIER_IN :  std_logic_vector(17 downto 0) := "000000000000000000";
+   signal LOAD_DATA_IN :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal RESULT_OUT :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal CEA1_IN :  std_logic;
+   signal CEA2_IN :  std_logic;
+   signal CEB1_IN :  std_logic;
+   signal CEB2_IN :  std_logic;
+
+-- Architecture Section: instantiation  
+begin
+  
+  CEA1_IN <=  CE when (AREG_IN = 2) else '0';
+  CEA2_IN <=  CE when (AREG_IN = 1 or AREG_IN = 2) else '0';
+  CEB1_IN <=  CE when (BREG_IN = 2) else '0';
+  CEB2_IN <=  CE when (BREG_IN = 1 or BREG_IN = 2) else '0';
+
+   v : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+         OPMODE_IN <= "01" & LOAD & "0101";
+   end generate v;
+
+   s : if (DEVICE = "SPARTAN6") generate
+          OPMODE_IN <= "00011" & LOAD & "01";
+   end generate s;
+
+    load1 : if (WIDTH_PRODUCT = 48) generate
+     begin
+       LOAD_DATA_IN <= LOAD_DATA;
+     end generate load1;
+   load2 : if (WIDTH_PRODUCT < 48) generate
+     begin
+       l1: for i in 47 downto WIDTH_PRODUCT generate
+             LOAD_DATA_IN(i) <= '0';
+           end generate;
+             LOAD_DATA_IN(WIDTH_PRODUCT-1 downto 0) <= LOAD_DATA;
+     end generate load2;
+
+  pa1 : if (WIDTH_PREADD = MaxWidthPreAdd) generate
+    begin 
+      PREADD1_IN(MaxWidthPreAdd-1 downto 0) <= PREADD1;
+      PREADD2_IN(MaxWidthPreAdd-1 downto 0) <= PREADD2;
+    end generate pa1;
+  mult1 : if (WIDTH_MULTIPLIER = 18) generate
+    begin 
+      MULTIPLIER_IN <= MULTIPLIER;
+    end generate mult1;
+  pa2 : if (WIDTH_PREADD < MaxWidthPreAdd) generate
+    begin 
+      pa: for i in MaxWidthPreAdd-1 downto WIDTH_PREADD generate
+            PREADD1_IN(i) <= PREADD1((WIDTH_PREADD-1));
+            PREADD2_IN(i) <= PREADD2((WIDTH_PREADD-1));
+          end generate;
+            PREADD1_IN(WIDTH_PREADD-1 downto 0) <= PREADD1;
+            PREADD2_IN(WIDTH_PREADD-1 downto 0) <= PREADD2;
+    end generate pa2;
+  mult2 : if (WIDTH_MULTIPLIER < 18) generate
+    begin 
+      m1: for i in 17 downto WIDTH_MULTIPLIER generate
+            MULTIPLIER_IN(i) <= MULTIPLIER((WIDTH_MULTIPLIER-1));
+          end generate;
+            MULTIPLIER_IN(WIDTH_MULTIPLIER-1 downto 0) <= MULTIPLIER;
+    end generate mult2;
+
+  PRODUCT <= RESULT_OUT(WIDTH_PRODUCT-1 downto 0);
+
+  -- begin generate virtex6
+  bl : if (DEVICE = "VIRTEX6"  or DEVICE = "7SERIES") generate
+    begin
+      DSP48E_1: DSP48E1 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,   
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          MREG => MREG_IN,      
+          PREG => PREG_IN,           
+          USE_DPORT => TRUE) 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => PREADD1_IN,          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => "0000", 
+          B => MULTIPLIER_IN,          
+          BCIN => "000000000000000000",    
+          C => LOAD_DATA_IN,           
+          CARRYCASCIN => '0', 
+          CARRYIN => CARRYIN, 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEAD => CE,
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE,
+          CED => CE,
+          CEINMODE => CE, 
+          CEM => CE,       
+          CEP => CE,       
+          CLK => CLK,       
+          D => PREADD2_IN,
+          INMODE => "00100", 
+          MULTSIGNIN => '0', 
+          OPMODE => OPMODE_IN, 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTD => RST,
+          RSTINMODE => RST,
+          RSTM => RST, 
+          RSTP => RST 
+       );
+end generate bl;
+-- end generate virtex6
+-- begin generate spartan6
+st : if DEVICE = "SPARTAN6" generate
+      begin
+        DSP48E_2: DSP48A1 
+        generic map (
+          A0REG => A0REG_IN,   
+          A1REG => A1REG_IN,   
+          B0REG => B0REG_IN,           
+          B1REG => B1REG_IN,           
+          MREG => MREG_IN,      
+          PREG => PREG_IN )           
+       port map ( 
+          BCOUT => open,  
+          CARRYOUT => open, 
+          CARRYOUTF => open, 
+          M => open, 
+          P => RESULT_OUT,          
+          PCOUT => open,  
+          A => MULTIPLIER_IN,          
+          B => PREADD1_IN(17 downto 0),          
+          C => LOAD_DATA_IN,           
+          CARRYIN => CARRYIN, 
+          CEA => CE,      
+          CEB => CE,      
+          CEC => CE,      
+          CECARRYIN => '0', 
+          CED => CE,
+          CEM => CE,       
+          CEOPMODE => CE, 
+          CEP => CE,       
+          CLK => CLK,       
+          D => PREADD2_IN(17 downto 0),
+          OPMODE => OPMODE_IN, 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCARRYIN => RST,     
+          RSTD => RST,
+          RSTM => RST, 
+          RSTOPMODE => RST,
+          RSTP => RST 
+         );
+  end generate st;
+-- end generate spartan6
+
+
+end addmacc;
+
+
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/ADDSUB_MACRO.vhd

@@ -0,0 +1,404 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2015 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 2015.3
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for DSP48
+-- /___/   /\     Filename : ADDSUB_MACRO.vhd
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Revision:
+--    06/06/08 - Initial version.
+--    04/18/11 - 652098 - Fix for latency 0
+--    10/27/14 - Added missing ALUMODEREG (CR 827820).
+--    04/09/15 - 852167 - align with verilog
+-- End Revision
+
+----- CELL ADDSUB_MACRO -----
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+
+entity ADDSUB_MACRO is
+  generic ( 
+    DEVICE : string := "VIRTEX5";
+            LATENCY : integer := 2;
+            STYLE : string := "DSP";
+            WIDTH : integer := 48;
+            WIDTH_B : integer := 48;
+            WIDTH_RESULT : integer := 48;
+            MODEL_TYPE : integer := 0;
+            VERBOSITY : integer := 0
+       );
+
+  port (
+      CARRYOUT : out std_logic;
+      RESULT : out std_logic_vector(WIDTH-1 downto 0);
+      A : in std_logic_vector(WIDTH-1 downto 0);   
+      ADD_SUB : in std_logic;   
+      B : in std_logic_vector(WIDTH-1 downto 0);   
+      CARRYIN : in std_logic;  
+      CE : in std_logic;
+      CLK : in std_logic;   
+      RST : in std_logic
+     );   
+end entity ADDSUB_MACRO;
+
+architecture addsub of ADDSUB_MACRO is
+  function CheckDevice (
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write( Message, DEVICE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckStyle (
+    style : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (style = "AUTO" or style = "DSP" ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute STYLE : ") );
+      write ( Message, STYLE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" AUTO, DSP ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+ function CheckLatency (
+    lat : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (LATENCY = 0 or LATENCY = 1 or LATENCY = 2) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute LATENCY : ") );
+      write ( Message, LATENCY);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 0, 1, 2. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckWidth (
+    width : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (width > 0 and width <= 48 ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH : ") );
+      write ( Message, WIDTH);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 48 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+
+  function GetABREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 2 ) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetPREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if (LATENCY = 1 or LATENCY = 2 ) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+
+
+--Signal Declarations:   
+
+   signal ALUMODE_IN :  std_logic_vector(3 downto 0);	
+   signal OPMODEST_IN :  std_logic_vector(7 downto 0);	
+   signal A_IN :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal B_IN :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal A_INST :  std_logic_vector(17 downto 0) := "000000000000000000";
+   signal RESULT_OUT :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal CARRYOUT_OUT : std_logic_vector(3 downto 0);
+   signal CARRYOUTST : std_logic;
+   signal CARRYIN_IN : std_logic;  
+ 
+   constant ChkDevice : boolean := CheckDevice(DEVICE);
+   constant ChkStyle : boolean := CheckStyle(STYLE);
+   constant ChkWidth : boolean := CheckWidth(WIDTH);
+   constant ChkLatency : boolean := CheckLatency(LATENCY);
+   constant AREG_IN : integer := GetABREG_IN(LATENCY);
+   constant ALUMODEREG_IN : integer := GetABREG_IN(LATENCY);
+   constant BREG_IN : integer := GetABREG_IN(LATENCY);
+   constant CREG_IN : integer := GetABREG_IN(LATENCY);
+   constant PREG_IN : integer := GetPREG_IN(LATENCY);
+
+-- Architecture Section: instantiation  
+begin
+  
+  ALUMODE_IN <= "00" & (not ADD_SUB) & (not ADD_SUB);
+  CARRYIN_IN <= CARRYIN when (WIDTH = 48) else '0';
+
+  OPMODEST_IN <= (not ADD_SUB) & (not ADD_SUB) & "001111";
+
+  add48 : if (WIDTH = 48) generate
+    begin 
+      A_IN <= A;
+      B_IN <= B;
+    end generate add48;
+  add : if (WIDTH < 48) generate
+    begin 
+      A_IN(47 downto (47-(WIDTH-1))) <= A;
+      A_IN((47-WIDTH)) <= ADD_SUB;
+      sa: for i in (47-(WIDTH+1)) downto 0 generate
+            A_IN(i) <= '0';
+          end generate;
+      B_IN(47 downto (47-(WIDTH-1))) <= B;
+      B_IN((47-WIDTH)) <= CARRYIN;
+      sb: for i in (47-(WIDTH+1)) downto 0 generate
+            B_IN(i) <= '0';
+          end generate;
+    end generate add;
+  
+  A_INST <= "000000" & A_IN(47 downto 36);
+  RESULT <= RESULT_OUT(47 downto (47-(WIDTH-1)));
+ 
+  c1: if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+        CARRYOUT <= CARRYOUT_OUT(3);
+   end generate c1;
+   -- begin s1
+  c2: if (DEVICE = "SPARTAN6") generate
+        CARRYOUT <= CARRYOUTST;
+   end generate c2;
+   -- end s1
+
+ -- begin generate virtex5
+  v5 : if DEVICE = "VIRTEX5" generate
+    begin
+      DSP48_1: DSP48E 
+        generic map (
+          ACASCREG => AREG_IN,       
+          ALUMODEREG => ALUMODEREG_IN,   
+          AREG => AREG_IN,           
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          CREG => CREG_IN,           
+          PREG => PREG_IN,           
+          USE_MULT => "NONE") 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => CARRYOUT_OUT(3 downto 0), 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => B_IN(47 downto 18),          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => B_IN(17 downto 0),          
+          BCIN => "000000000000000000",    
+          C => A_IN,           
+          CARRYCASCIN => '0', 
+          CARRYIN => CARRYIN_IN, 
+          CARRYINSEL => "000", 
+          CEA1 => CE,      
+          CEA2 => CE,      
+          CEALUMODE => CE, 
+          CEB1 => CE,      
+          CEB2 => CE,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE, 
+          CEM => '0',       
+          CEMULTCARRYIN => '0',
+          CEP => CE,       
+          CLK => CLK,       
+          MULTSIGNIN => '0', 
+          OPMODE => "0110011", 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTM => RST, 
+          RSTP => RST 
+       );
+  end generate v5;
+ -- end generate virtex5
+ -- begin generate virtex6
+  bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+    begin
+      DSP48_2: DSP48E1 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,   
+          ADREG => 0,
+          ALUMODEREG => ALUMODEREG_IN,   
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          CREG => CREG_IN,      
+          DREG => 0,
+          MREG => 0,
+          PREG => PREG_IN,           
+          USE_MULT => "NONE") 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => CARRYOUT_OUT, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => B_IN(47 downto 18),          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => B_IN(17 downto 0),          
+          BCIN => "000000000000000000",    
+          C => A_IN,           
+          CARRYCASCIN => '0', 
+          CARRYIN => CARRYIN_IN, 
+          CARRYINSEL => "000", 
+          CEA1 => CE,      
+          CEA2 => CE,      
+          CEAD => '0',
+          CEALUMODE => CE, 
+          CEB1 => CE,      
+          CEB2 => CE,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE,
+          CED => '0',
+          CEINMODE => '0', 
+          CEM => '0',       
+          CEP => CE,       
+          CLK => CLK,       
+          D => "0000000000000000000000000",
+          INMODE => "00000", 
+          MULTSIGNIN => '0', 
+          OPMODE => "0110011", 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTD => RST,
+          RSTINMODE => RST,
+          RSTM => RST, 
+          RSTP => RST 
+       );
+  end generate bl;
+  -- end generate virtex6
+  -- begin generate spartan6
+  st : if DEVICE = "SPARTAN6" generate
+      begin
+        DSP48_3: DSP48A1 
+        generic map (
+            A1REG => AREG_IN,   
+            B1REG => BREG_IN,           
+            CREG => CREG_IN,      
+            PREG => PREG_IN )           
+       port map ( 
+            BCOUT => open,  
+            CARRYOUT => CARRYOUTST, 
+            CARRYOUTF => open, 
+            M => open, 
+            P => RESULT_OUT,          
+            PCOUT => open,  
+            A => A_IN(35 downto 18),          
+            B => A_IN(17 downto 0),          
+            C => B_IN,           
+            CARRYIN => CARRYIN_IN, 
+            CEA => CE,      
+            CEB => CE,      
+            CEC => CE,      
+            CECARRYIN => CE, 
+            CED => CE,
+            CEM => '0',       
+            CEOPMODE => CE, 
+            CEP => CE,       
+            CLK => CLK,       
+            D => A_INST,
+            OPMODE => OPMODEST_IN, 
+            PCIN => "000000000000000000000000000000000000000000000000",      
+            RSTA => RST,     
+            RSTB => RST,     
+            RSTC => RST,     
+            RSTCARRYIN => RST,     
+            RSTD => RST,
+            RSTM => RST, 
+            RSTOPMODE => RST,
+            RSTP => RST 
+         );
+  end generate st;
+  -- end generate spartan6
+end addsub;
+
+
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/COUNTER_LOAD_MACRO.vhd

@@ -0,0 +1,329 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2008 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 13.1
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for DSP48
+-- /___/   /\     Filename : COUNTER_LOAD_MACRO.vhd
+-- \   \  /  \    Timestamp : Fri April 18 2008 10:43:59 PST 2008
+--  \___\/\___\
+--
+-- Revision:
+--    04/18/08 - Initial version.
+-- End Revision
+
+----- CELL COUNTER_LOAD_MACRO -----
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+entity COUNTER_LOAD_MACRO is
+  generic ( 
+            COUNT_BY : std_logic_vector := X"000000000001";
+    DEVICE : string := "VIRTEX5";
+            STYLE : string := "AUTO";
+            WIDTH_DATA : integer := 48
+       );
+
+  port (
+      Q : out std_logic_vector(WIDTH_DATA-1 downto 0);   
+      CE : in std_logic;
+      CLK : in std_logic;   
+      DIRECTION : in std_logic;
+      LOAD : in std_logic;
+      LOAD_DATA : in std_logic_vector(WIDTH_DATA-1 downto 0);
+      RST : in std_logic   
+     );   
+end entity COUNTER_LOAD_MACRO;
+
+architecture counter of COUNTER_LOAD_MACRO is
+
+  function CheckDevice (
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write ( Message, DEVICE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckStyle (
+    style : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (style = "AUTO" or style = "DSP" ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute STYLE : ") );
+      write ( Message, STYLE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" AUTO, DSP ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckWidth (
+    width : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (width > 0 and width <= 48 ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_DATA : ") );
+      write ( Message, WIDTH_DATA);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 48 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+
+  function GetOPMODE_IN (
+    device : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      func_width := 7;
+    elsif (DEVICE = "SPARTAN6") then
+      func_width := 8;
+    else
+      func_width := 8;
+    end if;
+    return func_width;
+  end;
+
+   constant OPMODE_WIDTH : integer := GetOPMODE_IN(DEVICE);
+   constant ChkDevice : boolean := CheckDevice(DEVICE);
+   constant ChkStyle : boolean := CheckStyle(STYLE);
+   constant ChkWidth : boolean := CheckWidth(WIDTH_DATA);
+
+--Signal Declarations:   
+   signal OPMODE_IN :  std_logic_vector((OPMODE_WIDTH-1) downto 0);
+   signal ALUMODE_IN :  std_logic_vector(3 downto 0);	
+   signal CNTR_OUT :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal COUNT_BY_IN :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal LOAD_DATA_IN :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal D_INST :  std_logic_vector(17 downto 0) := "000000000000000000";
+
+
+-- Architecture Section: instantiation  
+begin
+   
+  v : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+         OPMODE_IN <=  ("01" & LOAD & "00" & (not LOAD) & (not LOAD) );
+  end generate v;
+
+  s : if (DEVICE = "SPARTAN6") generate
+         OPMODE_IN <= (not DIRECTION) & (not DIRECTION) & "001" & LOAD & "11";
+  end generate s;
+
+  Q <=  CNTR_OUT(WIDTH_DATA-1 downto 0);
+
+    load1 : if (WIDTH_DATA = 48) generate
+     begin
+       LOAD_DATA_IN <= LOAD_DATA;
+     end generate load1;
+    load2 : if (WIDTH_DATA < 48) generate
+     begin
+       l1: for i in 47 downto WIDTH_DATA generate
+             LOAD_DATA_IN(i) <= '0';
+           end generate;
+             LOAD_DATA_IN(WIDTH_DATA-1 downto 0) <= LOAD_DATA;
+     end generate load2;
+
+  ALUMODE_IN <= "00" & (not DIRECTION) & (not DIRECTION);
+  COUNT_BY_IN <= COUNT_BY;
+
+  D_INST <= "000000" & COUNT_BY_IN(47 downto 36);
+
+  -- begin generate virtex5
+  v5 : if DEVICE = "VIRTEX5" generate
+    begin
+      DSP48E_1: DSP48E 
+        generic map (
+          USE_MULT => "NONE") 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => CNTR_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => COUNT_BY_IN(47 downto 18),          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => COUNT_BY_IN(17 downto 0),          
+          BCIN => "000000000000000000",    
+          C => LOAD_DATA_IN,           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => '0',      
+          CEA2 => CE,      
+          CEALUMODE => CE, 
+          CEB1 => '0',      
+          CEB2 => CE,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE, 
+          CEM => '0',       
+          CEMULTCARRYIN => '0',
+          CEP => CE,       
+          CLK => CLK,       
+          MULTSIGNIN => '0', 
+          OPMODE => OPMODE_IN, 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTM => RST, 
+          RSTP => RST 
+       );
+end generate v5;
+  -- end generate virtex5
+  -- begin generate virtex6
+bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+    begin
+      DSP48E_2: DSP48E1 
+        generic map (
+          DREG => 0,
+          ADREG => 0,
+          MREG => 0,
+          USE_MULT => "NONE") 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => CNTR_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => COUNT_BY_IN(47 downto 18),          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => COUNT_BY_IN(17 downto 0),          
+          BCIN => "000000000000000000",    
+          C => LOAD_DATA_IN,           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => '0',      
+          CEA2 => CE,      
+          CEAD => '0',
+          CEALUMODE => CE, 
+          CEB1 => '0',      
+          CEB2 => CE,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE,
+          CED => '0',
+          CEINMODE => '0', 
+          CEM => '0',       
+          CEP => CE,       
+          CLK => CLK,       
+          D => "0000000000000000000000000",
+          INMODE => "00000", 
+          MULTSIGNIN => '0', 
+          OPMODE => OPMODE_IN, 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTD => RST,
+          RSTINMODE => RST,
+          RSTM => RST, 
+          RSTP => RST 
+       );
+end generate bl;
+  -- end generate virtex6
+  -- begin generate spartan6
+  st : if DEVICE = "SPARTAN6" generate
+      begin
+        DSP48E_3: DSP48A1 
+       port map ( 
+            BCOUT => open,  
+            CARRYOUT => open, 
+            CARRYOUTF => open, 
+            M => open, 
+            P => CNTR_OUT,          
+            PCOUT => open,  
+            A => COUNT_BY_IN(35 downto 18),          
+            B => COUNT_BY_IN(17 downto 0),          
+            C => LOAD_DATA_IN,           
+            CARRYIN => '0', 
+            CEA => CE,      
+            CEB => CE,      
+            CEC => CE,      
+            CECARRYIN => CE, 
+            CED => CE,
+            CEM => '0',       
+            CEOPMODE => CE, 
+            CEP => CE,       
+            CLK => CLK,       
+            D => D_INST,
+            OPMODE => OPMODE_IN, 
+            PCIN => "000000000000000000000000000000000000000000000000",      
+            RSTA => RST,     
+            RSTB => RST,     
+            RSTC => RST,     
+            RSTCARRYIN => RST,     
+            RSTD => RST,
+            RSTM => RST, 
+            RSTOPMODE => RST,
+            RSTP => RST 
+         );
+  end generate st;
+  -- end generate spartan6
+
+end counter;
+
+
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/COUNTER_TC_MACRO.vhd

@@ -0,0 +1,301 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2007 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 13.1
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for DSP48
+-- /___/   /\     Filename : COUNTER_TC_MACRO.vhd
+-- \   \  /  \    Timestamp : Fri April 18 2008 10:43:59 PST 2008
+--  \___\/\___\
+--
+-- Revision:
+--    06/08/08 - Initial version.
+--    01/04/12 - Fix for CR 639887
+-- End Revision
+
+----- CELL COUNTER_TC_MACRO -----
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+entity COUNTER_TC_MACRO is
+  generic ( 
+            COUNT_BY : std_logic_vector := X"000000000001";
+    DEVICE : string := "VIRTEX5";
+            DIRECTION : string := "UP";
+            RESET_UPON_TC : string := "FALSE";
+            STYLE : string := "AUTO";
+            TC_VALUE : std_logic_vector := X"000000000000";
+            WIDTH_DATA : integer := 48
+       );
+
+  port (
+      Q : out std_logic_vector(WIDTH_DATA-1 downto 0);   
+      TC : out std_logic;   
+      CE : in std_logic;
+      CLK : in std_logic;   
+      RST : in std_logic   
+     );   
+end entity COUNTER_TC_MACRO;
+
+architecture count of COUNTER_TC_MACRO is
+
+  function CheckDevice (
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES" ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write ( Message, DEVICE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" VIRTEX5, VIRTEX6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckStyle (
+    style : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (style = "AUTO" or style = "DSP" ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute STYLE : ") );
+      write ( Message, STYLE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" AUTO, DSP ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckWidth (
+    width : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (width > 0 and width <= 48 ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_DATA : ") );
+      write ( Message, WIDTH_DATA);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 48 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+
+   function CheckReset (
+    reset : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (reset = "TRUE" or reset = "FALSE" ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute RESET_UPON_TC : ") );
+      write ( Message, STYLE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" TRUE or FALSE ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+
+  function GetDirection (
+    dir : in string
+    ) return std_logic is
+    variable func_val : std_logic;
+    variable Message : LINE;
+  begin
+    if (DIRECTION = "UP") then
+      func_val := '0';
+    elsif (DIRECTION = "DOWN") then
+      func_val := '1';
+    else
+      write( Message, STRING'("Illegal value of Attribute DIRECTION : ") );
+      write ( Message, DIRECTION);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" UP or DOWN ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+
+
+--Signal Declarations:   
+
+   signal ALUMODE_IN :  std_logic_vector(3 downto 0);	
+   signal OPMODE_IN :  std_logic_vector(6 downto 0);	
+   signal CNTR_OUT :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal COUNT_BY_INP :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal Q_IN :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal TC_INT :  std_logic;
+
+   constant ChkDevice : boolean := CheckDevice(DEVICE);
+   constant ChkStyle : boolean := CheckStyle(STYLE);
+   constant ChkWidth : boolean := CheckWidth(WIDTH_DATA);
+   constant ChkReset : boolean := CheckReset(RESET_UPON_TC);
+   constant ADD_SUB : std_logic := GetDirection(DIRECTION);
+
+-- Architecture Section: instantiation  
+begin
+ 
+  t1 : TC_INT <=  '1' when ( CNTR_OUT = (TC_VALUE -1) and RST = '0') else '0';
+  t2 : TC <=  '1' when ( CNTR_OUT = TC_VALUE and RST = '0') else '0';
+  op : OPMODE_IN <=  ('0' & (not TC_INT) & "000" & (not TC_INT) & (not TC_INT) ) when (RESET_UPON_TC = "TRUE") else "0100011";
+  Q <=  Q_IN(WIDTH_DATA-1 downto 0) when (RST = '1' or (RESET_UPON_TC = "TRUE" and CNTR_OUT = (TC_VALUE+1))) else CNTR_OUT(WIDTH_DATA-1 downto 0);
+
+  ALUMODE_IN <= "00" & ADD_SUB & ADD_SUB;
+  COUNT_BY_INP <= COUNT_BY;
+
+  -- begin generate virtex5
+  v5 : if DEVICE = "VIRTEX5" generate
+    begin
+      DSP48E_1: DSP48E 
+        generic map (
+          USE_MULT => "NONE") 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => CNTR_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => COUNT_BY_INP(47 downto 18),          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => COUNT_BY_INP(17 downto 0),          
+          BCIN => "000000000000000000",    
+          C => "000000000000000000000000000000000000000000000000",           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => '0',      
+          CEA2 => CE,      
+          CEALUMODE => CE, 
+          CEB1 => '0',      
+          CEB2 => CE,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE, 
+          CEM => '0',       
+          CEMULTCARRYIN => '0',
+          CEP => CE,       
+          CLK => CLK,       
+          MULTSIGNIN => '0', 
+          OPMODE => OPMODE_IN, 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTM => RST, 
+          RSTP => RST 
+       );
+end generate v5;
+  -- end generate virtex5
+  -- begin generate virtex6
+bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+    begin
+      DSP48E_2: DSP48E1 
+        generic map (
+          DREG => 0,
+          ADREG => 0,
+          MREG => 0,
+          USE_MULT => "NONE") 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => CNTR_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => COUNT_BY_INP(47 downto 18),          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => COUNT_BY_INP(17 downto 0),          
+          BCIN => "000000000000000000",    
+          C => "000000000000000000000000000000000000000000000000",           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => '0',      
+          CEA2 => CE,      
+          CEAD => '0',
+          CEALUMODE => CE, 
+          CEB1 => '0',      
+          CEB2 => CE,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE,
+          CED => '0',
+          CEINMODE => '0', 
+          CEM => '0',       
+          CEP => CE,       
+          CLK => CLK,       
+          D => "0000000000000000000000000",
+          INMODE => "00000", 
+          MULTSIGNIN => '0', 
+          OPMODE => OPMODE_IN, 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTD => RST,
+          RSTINMODE => RST,
+          RSTM => RST, 
+          RSTP => RST 
+       );
+end generate bl;
+  -- end generate virtex6
+end count;
+
+
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/EQ_COMPARE_MACRO.vhd

@@ -0,0 +1,368 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2015 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 2015.3
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for DSP48
+-- /___/   /\     Filename : EQ_COMPARE_MACRO.vhd
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Revision:
+--    04/04/08 - Initial version.
+--    04/09/15 - 852167 - align with verilog
+-- End Revision
+
+----- CELL EQ_COMPARE_MACRO -----
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+entity EQ_COMPARE_MACRO is
+  generic ( 
+            DEVICE : string := "VIRTEX6";
+            LATENCY : integer := 2;
+            MASK : bit_vector := X"000000000000";
+            SEL_MASK : string := "MASK";
+            SEL_PATTERN : string := "DYNAMIC_PATTERN";
+            STATIC_PATTERN : bit_vector := X"000000000000";
+            WIDTH : integer := 48
+       );
+
+  port (
+      Q : out std_logic;   
+      CE : in std_logic;
+      CLK : in std_logic;   
+      DATA_IN : in std_logic_vector(WIDTH-1 downto 0);
+      DYNAMIC_PATTERN : in std_logic_vector(WIDTH-1 downto 0);
+      RST : in std_logic   
+     );   
+end entity EQ_COMPARE_MACRO;
+
+architecture compare of EQ_COMPARE_MACRO is
+
+  function CheckDevice (
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write ( Message, DEVICE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" VIRTEX5, VIRTEX6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function GetSelPattern (
+    sel_pat : in string
+    ) return string is
+    variable Message : LINE;
+  begin
+    if (sel_pat = "STATIC_PATTERN") then
+      return "PATTERN";
+    elsif (sel_pat = "DYNAMIC_PATTERN") then
+      return "C";
+    else
+      write( Message, STRING'("Illegal value of Attribute SEL_PATTERN : ") );
+      write ( Message, SEL_PATTERN);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" STATIC_PATTERN, DYNAMIC_PATTERN ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+      return "PATTERN";
+    end if;
+  end;
+  function GetSelMask (
+    sel_mas : in string
+    ) return string is
+    variable Message : LINE;
+  begin
+    if (sel_mas = "MASK" ) then
+      return "MASK";
+    elsif (sel_mas = "DYNAMIC_PATTERN") then
+      return "C"; 
+    else
+      write( Message, STRING'("Illegal value of Attribute SEL_MASK : ") );
+      write ( Message, SEL_MASK);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" MASK, DYNAMIC_PATTERN ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+      return "MASK";
+    end if;
+  end;
+ function CheckWidth (
+    width : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (width > 0 and width <= 48 ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH : ") );
+      write ( Message, WIDTH);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 48 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function GetABREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 2 ) then
+      func_width := 1;
+    elsif (LATENCY = 3 ) then
+      func_width := 2;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetCREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if (LATENCY = 2 or LATENCY = 3 ) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetQREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3) then
+      func_width := 1;
+    elsif (LATENCY = 0) then
+      func_width := 0;
+    else
+      func_width := 0;
+      write( Message, STRING'("Illegal value of Attribute LATENCY : ") );
+      write ( Message, LATENCY);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 0 to 3 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_width;
+  end;
+
+  
+--Signal Declarations:   
+
+   signal DYNAMIC_PATTERN_INP :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal DATA_INP :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal CEA1_IN :  std_logic;
+   signal CEA2_IN :  std_logic;
+   signal CEB1_IN :  std_logic;
+   signal CEB2_IN :  std_logic;
+ 
+   constant AREG_IN : integer := GetABREG_IN(LATENCY);
+   constant BREG_IN : integer := GetABREG_IN(LATENCY);
+   constant CREG_IN : integer := GetCREG_IN(LATENCY);
+   constant QREG : integer := GetQREG_IN(LATENCY);
+   constant ChkDevice : boolean := CheckDevice(DEVICE);
+   constant SEL_PATTERN_IN : string := GetSelPattern(SEL_PATTERN);
+   constant SEL_MASK_IN : string := GetSelMask(SEL_MASK);
+   constant ChkWidth : boolean := CheckWidth(WIDTH);
+
+-- Architecture Section: instantiation  
+begin
+ 
+   CEA1_IN <=  CE when (AREG_IN = 2) else '0';
+   CEA2_IN <=  CE when (AREG_IN = 1 or AREG_IN = 2) else '0';
+   CEB1_IN <=  CE when (BREG_IN = 2) else '0';
+   CEB2_IN <=  CE when (BREG_IN = 1 or BREG_IN = 2) else '0';
+
+    inps1 : if (WIDTH = 48) generate
+     begin
+       DATA_INP  <= DATA_IN;
+       DYNAMIC_PATTERN_INP  <= DYNAMIC_PATTERN;
+     end generate inps1;
+    inps2 : if (WIDTH < 48) generate
+     begin
+        i1: for i in 47 downto WIDTH generate
+              DATA_INP(i) <= '0';
+              DYNAMIC_PATTERN_INP(i) <= '0';
+        end generate;
+        DATA_INP(WIDTH-1 downto 0)  <= DATA_IN(WIDTH-1 downto 0);
+        DYNAMIC_PATTERN_INP(WIDTH-1 downto 0)  <= DYNAMIC_PATTERN(WIDTH-1 downto 0);
+     end generate inps2;
+
+  -- begin generate virtex5
+  v5 : if DEVICE = "VIRTEX5" generate
+    begin
+      DSP48E_1: DSP48E 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,           
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          CREG => CREG_IN,           
+          MASK => MASK, 
+          PATTERN => STATIC_PATTERN, 
+          PREG => QREG,           
+          SEL_MASK => SEL_MASK_IN,  
+          SEL_PATTERN => SEL_PATTERN_IN, 
+          USE_MULT => "NONE", 
+          USE_PATTERN_DETECT => "PATDET" 
+          ) 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => open,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => Q, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => DATA_INP(47 downto 18),          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => "0000", 
+          B => DATA_INP(17 downto 0),          
+          BCIN => "000000000000000000",    
+          C => DYNAMIC_PATTERN_INP,           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE, 
+          CEM => '0',       
+          CEMULTCARRYIN => '0',
+          CEP => CE,       
+          CLK => CLK,       
+          MULTSIGNIN => '0', 
+          OPMODE => "0000011", 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTM => RST, 
+          RSTP => RST 
+       );
+end generate v5;
+  -- end generate virtex5
+  -- begin generate virtex6
+bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+    begin
+      DSP48E_2: DSP48E1 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,           
+          ADREG => 0,           
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          CREG => CREG_IN,           
+          DREG => 0,           
+          MREG => 0,           
+          MASK => MASK, 
+          PATTERN => STATIC_PATTERN, 
+          PREG => QREG,           
+          SEL_MASK => SEL_MASK_IN,  
+          SEL_PATTERN => SEL_PATTERN_IN, 
+          USE_MULT => "NONE", 
+          USE_PATTERN_DETECT => "PATDET" 
+          ) 
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => open,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => Q, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => DATA_INP(47 downto 18),          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => "0000", 
+          B => DATA_INP(17 downto 0),          
+          BCIN => "000000000000000000",    
+          C => DYNAMIC_PATTERN_INP,           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEAD => '0',
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE,
+          CED => '0',
+          CEINMODE => '0', 
+          CEM => '0',       
+          CEP => CE,       
+          CLK => CLK,       
+          D => "0000000000000000000000000",
+          INMODE => "00000", 
+          MULTSIGNIN => '0', 
+          OPMODE => "0000011", 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTD => RST,
+          RSTINMODE => RST,
+          RSTM => RST, 
+          RSTP => RST 
+       );
+end generate bl;
+  -- end generate virtex6
+
+end compare;
+
+
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/FIFO_DUALCLOCK_MACRO.vhd

@@ -0,0 +1,930 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2007 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 13.1
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for FIFO
+-- /___/   /\     Filename : FIFO_DUALCLOCK_MACRO.vhd
+-- \   \  /  \    Timestamp : Fri April 18 2008 10:43:59 PST 2006
+--  \___\/\___\
+--
+-- Revision:
+--    04/04/08 - Initial version.
+--    08/09/11 - Fixed CR 620349
+--    01/11/12 - 639772, 604428 -Constrain DI, DO, add width checking.
+-- End Revision
+
+----- CELL FIFO_DUALCLOCK_MACRO -----
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.numeric_std.all;
+
+library unisim;
+use unisim.VCOMPONENTS.all;
+
+library unimacro;
+use unimacro.VCOMPONENTS.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+entity FIFO_DUALCLOCK_MACRO is
+
+  generic (
+    ALMOST_FULL_OFFSET      : bit_vector := X"0080";
+    ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
+    DATA_WIDTH              : integer    := 4; 
+    DEVICE : string := "VIRTEX5";
+    FIFO_SIZE : string := "18Kb";  
+    FIRST_WORD_FALL_THROUGH : boolean    := FALSE;
+    INIT                    : bit_vector := X"000000000000000000"; -- This parameter is valid only for Virtex6
+    SRVAL                   : bit_vector := X"000000000000000000"; -- This parameter is valid only for Virtex6
+    SIM_MODE                  : string     := "SAFE" -- This parameter is valid only for Virtex5
+    );
+  port(
+    ALMOSTEMPTY : out std_logic;
+    ALMOSTFULL  : out std_logic;
+    DO          : out std_logic_vector(DATA_WIDTH-1 downto 0);
+    EMPTY       : out std_logic;
+    FULL        : out std_logic;
+    RDCOUNT     : out std_logic_vector(xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0);
+    RDERR       : out std_logic;
+    WRCOUNT     : out std_logic_vector(xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0);
+    WRERR       : out std_logic;
+
+    DI          : in  std_logic_vector(DATA_WIDTH-1 downto 0);
+    RDCLK       : in  std_logic;
+    RDEN        : in  std_logic;
+    RST         : in  std_logic;
+    WRCLK       : in  std_logic;
+    WREN        : in  std_logic
+    );
+
+  end entity FIFO_DUALCLOCK_MACRO;
+
+  architecture fifo_V of FIFO_DUALCLOCK_MACRO is
+ 
+  function GetDWidth (
+    d_width : in integer;
+    func_fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      case d_width is
+        when 0|1|2|3|4 => func_width := 4;
+                         if(d_width = 0) then
+                         write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") );
+                         write( Message, STRING'(". This attribute must atleast be equal to 1 . ") );
+                         ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+                         DEALLOCATE (Message);
+                         end if;
+        when 5|6|7|8|9 => func_width := 8;
+        when 10 to 18 => func_width := 16;
+        when 19 to 36 => func_width := 32;
+        when 37 to 72 => if(func_fifo_size = "18Kb") then
+                         write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") );
+                         write( Message, STRING'(". Legal values of this attribute for FIFO_SIZE 18Kb are ") );
+                         write( Message, STRING'(" 1 to 36 ") );
+                         ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+                         DEALLOCATE (Message);
+                         else
+                         func_width := 64;
+                         end if;
+        when others =>   write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") );
+                         write( Message, STRING'(". Legal values of this attribute are ") );
+                         write( Message, STRING'(" 1 to 36 for FIFO_SIZE of 18Kb and ") );
+                         write( Message, STRING'(" 1 to 72 for FIFO_SIZE of 36Kb .") );
+                         ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+                         DEALLOCATE (Message);
+                         func_width := 64;
+      end case;
+    else
+      func_width := 64;
+    end if;
+    return func_width;
+  end;
+  function GetD_Size (
+    d_size : in integer;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      case d_size is
+        when 0|1|2|3|4 => func_width := 4;
+        when 5|6|7|8|9 => func_width := 9;
+        when 10 to 18 => func_width := 18;
+        when 19 to 36 => func_width := 36;
+        when 37 to 72 => func_width := 72;
+        when others => func_width := 1;
+      end case;
+    else
+      func_width := 1;
+    end if;
+    return func_width;
+  end;
+
+  function GetDIPWidth (
+    d_width : in integer;
+    func_fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      case d_width is
+        when 9 => func_width := 1;
+        when 17 => func_width := 1;
+        when 18 => func_width := 2;
+        when 33 => func_width := 1;
+        when 34 => func_width := 2;
+        when 35 => func_width := 3;
+        when 36 => func_width := 4;
+        when 65 => func_width := 1;
+        when 66 => func_width := 2;
+        when 67 => func_width := 3;
+        when 68 => func_width := 4;
+        when 69 => func_width := 5;
+        when 70 => func_width := 6;
+        when 71 => func_width := 7;
+        when 72 => func_width := 8;
+        when others => func_width := 0;
+      end case;
+    else
+      func_width := 0;
+    end if;
+  return func_width;
+  end;
+  function GetDOPWidth (
+    d_width : in integer;
+    func_fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      case d_width is
+        when 9 => func_width := 1;
+        when 17 => func_width := 1;
+        when 18 => func_width := 2;
+        when 33 => func_width := 1;
+        when 34 => func_width := 2;
+        when 35 => func_width := 3;
+        when 36 => func_width := 4;
+        when 65 => func_width := 1;
+        when 66 => func_width := 2;
+        when 67 => func_width := 3;
+        when 68 => func_width := 4;
+        when 69 => func_width := 5;
+        when 70 => func_width := 6;
+        when 71 => func_width := 7;
+        when 72 => func_width := 8;
+        when others => func_width := 1;
+      end case;
+    else
+      func_width := 1;
+    end if;
+  return func_width;
+  end;
+
+  function GetCOUNTWidth (
+    d_width : in integer;
+    fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if(fifo_size = "18Kb") then
+        case d_width is
+          when 0|1|2|3|4 => func_width := 12;
+          when 5|6|7|8|9 => func_width := 11;
+          when 10 to 18 => func_width := 10;
+          when 19 to 36 => func_width := 9;
+          when others => func_width := 12;
+        end case;
+      elsif(fifo_size = "36Kb") then
+        case d_width is
+          when 0|1|2|3|4 => func_width := 13;
+          when 5|6|7|8|9 => func_width := 12;
+          when 10 to 18 => func_width := 11;
+          when 19 to 36 => func_width := 10;
+          when 37 to 72 => func_width := 9;
+          when others => func_width := 13;
+        end case;
+      end if;
+    else
+      func_width := 13;
+    end if;
+    return func_width;
+  end;
+
+  function GetMaxDWidth (
+    d_width : in integer;
+    fifo_size : in string; 
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if(DEVICE = "VIRTEX5") then
+      if (fifo_size = "18Kb" and d_width <= 18 ) then
+        func_width := 16;
+      elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then
+        func_width := 32;
+      elsif (fifo_size = "36Kb" and d_width <= 36 ) then
+        func_width := 32;
+      elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then
+        func_width := 64;
+      else
+        func_width := 64;
+      end if;
+    elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (fifo_size = "18Kb" and d_width <= 36 ) then
+        func_width := 32;
+      elsif (fifo_size = "36Kb" and d_width <= 72 ) then
+        func_width := 64;
+      else
+        func_width := 64;
+      end if; -- end b1
+    else
+      func_width := 64;
+    end if;
+    return func_width;
+  end;
+  function GetMaxDPWidth (
+    d_width : in integer;
+    fifo_size : in string; 
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if(DEVICE = "VIRTEX5") then
+      if (fifo_size = "18Kb" and d_width <= 18 ) then
+        func_width := 2;
+      elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then
+        func_width := 4;
+      elsif (fifo_size = "36Kb" and d_width <= 36 ) then
+        func_width := 4;
+      elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then
+        func_width := 8;
+      else
+        func_width := 8;
+      end if;
+     elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (fifo_size = "18Kb" and d_width <= 36 ) then
+        func_width := 4;
+      elsif (fifo_size = "36Kb" and d_width <= 72 ) then
+        func_width := 8;
+      else
+        func_width := 8;
+      end if; -- end b2
+
+    else
+      func_width := 8;
+    end if;
+    return func_width;
+  end;
+  function GetFinalWidth (
+    d_width : in integer
+    ) return integer is
+    variable func_least_width : integer;
+  begin
+    if (d_width = 0) then
+      func_least_width := 1;
+    else
+      func_least_width := d_width;
+    end if;
+    return func_least_width;
+  end;
+  function GetMaxCOUNTWidth (
+    d_width : in integer;
+    fifo_size : in string; 
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5") then
+      if (fifo_size = "18Kb" and d_width <= 18 ) then
+        func_width := 12;
+      elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then
+        func_width := 9;
+      elsif (fifo_size = "36Kb" and d_width <= 36 ) then
+        func_width := 13;
+      elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then
+        func_width := 9;
+      else
+        func_width := 13;
+      end if;
+    elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (fifo_size = "18Kb" and d_width <= 36 ) then
+        func_width := 12;
+      elsif (fifo_size = "36Kb" and d_width <= 72 ) then
+        func_width := 13;
+      else
+        func_width := 13;
+      end if; -- end b3
+    else
+      func_width := 13;
+    end if;
+    return func_width;
+  end;
+
+  function GetFIFOSize (
+    fifo_size : in string; 
+    device  : in string
+    ) return boolean is
+    variable fifo_val : boolean;
+    variable Message : LINE;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if fifo_size = "18Kb" or fifo_size = "36Kb" then
+      fifo_val := TRUE;
+      else
+          fifo_val := FALSE;
+          write( Message, STRING'("Illegal value of Attribute FIFO_SIZE : ") );
+          write ( Message, FIFO_SIZE);
+          write( Message, STRING'(". Legal values of this attribute are ") );
+          write( Message, STRING'(" 18Kb or 36Kb ") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+      end if;
+    else
+      fifo_val := FALSE;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write ( Message, DEVICE);
+      write( Message, STRING'(". Allowed values of this attribute are ") );
+      write( Message, STRING'(" VIRTEX5, VIRTEX6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return fifo_val;
+  end;
+
+  function GetD_P (
+    dw : in integer;
+    device  : in string
+    ) return boolean is
+    variable dp : boolean;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if dw = 9 or dw = 17 or dw = 18 or dw = 33 or dw = 34 or dw = 35 or dw = 36 or dw = 65 or dw = 66 or dw = 67 or dw = 68 or dw = 69 or dw = 70 or dw = 71 or dw = 72 then
+      dp := TRUE;
+       else
+          dp := FALSE;
+      end if;
+    else
+      dp := FALSE;
+    end if;
+    return dp;
+  end;
+
+  function GetSIMDev (
+    device  : in string
+    ) return string is
+  begin
+    if(DEVICE = "VIRTEX6") then
+      return "VIRTEX6";
+    else
+      return "7SERIES";
+      end if;
+  end;
+
+ function CheckRDCOUNT (
+    d_width : in integer;
+    fifo_size : in string;
+    device  : in string;
+    rd_vec : in integer
+    ) return boolean is
+    variable Message : LINE;
+  begin
+    if(fifo_size = "18Kb") then
+        if ((d_width > 0 and d_width <= 4) and rd_vec /= 12) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 12 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >4 and d_width <= 9) and rd_vec /= 11) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 11 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >=10 and d_width <=18) and rd_vec /= 10) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 10 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >19 and d_width <=36) and rd_vec /= 9) then
+          write( Message, STRING'(" .RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 9 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+	else
+	  return true;
+        end if;
+    elsif(fifo_size = "36Kb") then
+        if ((d_width > 0 and d_width <= 4) and rd_vec /= 13) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 13 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width > 4 and d_width <= 9) and rd_vec /= 12) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 12 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >=10 and d_width <=18) and rd_vec /= 11) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 11 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >18 and d_width <=36) and rd_vec /= 10) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 10 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >36 and d_width <=72) and rd_vec /= 9) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 9 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+	else
+	  return true;
+	end if;
+      else
+        return true;
+      end if;
+  end;
+
+  function CheckWRCOUNT (
+    d_width : in integer;
+    fifo_size : in string;
+    device  : in string;
+    wr_vec : in integer
+    ) return boolean is
+    variable Message : LINE;
+  begin
+    if(fifo_size = "18Kb") then
+        if ((d_width > 0 and d_width <= 4) and wr_vec /= 12) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 12 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >4 and d_width <= 9) and wr_vec /= 11) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 11 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >=10 and d_width <=18) and wr_vec /= 10) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 10 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >19 and d_width <=36) and wr_vec /= 9) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 9 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+	else
+	  return true;
+	end if;
+      elsif(fifo_size = "36Kb") then
+        if ((d_width > 0 and d_width <= 4) and wr_vec /= 13) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 13 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width > 4 and d_width <= 9) and wr_vec /= 12) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 12 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >=10 and d_width <=18) and wr_vec /= 11) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 11 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >18 and d_width <=36) and wr_vec /= 10) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 10 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >36 and d_width <=72) and wr_vec /= 9) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 9 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+	else
+	  return true;
+	end if;
+      else
+        return true;
+      end if;
+  end;
+
+  constant fifo_size_val : boolean := GetFIFOSize(FIFO_SIZE, DEVICE);
+  constant data_p : boolean := GetD_P(DATA_WIDTH, DEVICE); 
+  constant count_width : integer := GetCOUNTWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant d_width : integer  := GetDWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant d_size : integer := GetD_Size(DATA_WIDTH, DEVICE);
+  constant dip_width : integer := GetDIPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant dop_width : integer := GetDOPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant fin_width : integer := GetFinalWidth(DATA_WIDTH);
+  constant sim_device_dp : string := GetSIMDev(DEVICE);
+  constant rdctleng : integer := RDCOUNT'length;
+  constant wrctleng : integer := WRCOUNT'length;
+  constant checkrdct : boolean := CheckRDCount(DATA_WIDTH, FIFO_SIZE, DEVICE, rdctleng);
+  constant checkwrct : boolean := CheckWRCount(DATA_WIDTH, FIFO_SIZE, DEVICE, wrctleng);
+
+  constant max_data_width : integer := GetMaxDWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant max_datap_width : integer := GetMaxDPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant max_count_width : integer := GetMaxCOUNTWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+
+  signal di_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0');  
+  signal do_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0');  
+  signal dip_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0');  
+  signal dop_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0');  
+  signal rdcount_pattern : std_logic_vector(max_count_width-1 downto 0) := (others =>'0');
+  signal wrcount_pattern : std_logic_vector(max_count_width-1 downto 0) := (others =>'0');
+
+  
+  begin
+    di1v5 : if  (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate 
+      digen1 : if (data_p = TRUE  and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate
+      begin 
+        dip_pattern(dip_width-1 downto 0) <= DI(fin_width-1 downto d_width) ;
+        di_pattern (d_width-1 downto 0) <= DI(d_width-1 downto 0);
+      end generate digen1;
+    end generate di1v5;
+
+    di2v5 : if  (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate 
+      digen2 : if (data_p = FALSE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate
+      begin 
+        di_pattern(fin_width-1 downto 0) <= DI(fin_width-1 downto 0);
+      end generate digen2;
+    end generate di2v5;
+
+    do1v5 : if  (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate 
+      dogen1 : if (data_p= TRUE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate
+      begin
+        DO <= (dop_pattern(dop_width-1 downto 0) & do_pattern(d_width-1 downto 0));
+      end generate dogen1;
+    end generate do1v5;
+
+    do2v5 : if  (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate 
+      dogen2 : if (data_p= FALSE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate
+      begin
+        DO <= do_pattern(fin_width-1 downto 0);
+      end generate dogen2;
+    end generate do2v5;
+ 
+    RDCOUNT <= rdcount_pattern(count_width-1 downto 0); 
+    WRCOUNT <= wrcount_pattern(count_width-1 downto 0); 
+
+  -- begin generate virtex5
+  v5 : if (DEVICE = "VIRTEX5") generate
+    fifo_18_inst : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH <=18 ) generate 
+    begin
+    fifo_18_inst : FIFO18 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => 1,
+      EN_SYN => FALSE,
+      FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH,
+      SIM_MODE => SIM_MODE
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => RDCLK,
+      RDEN => RDEN,
+      RST => RST,
+      WRCLK => WRCLK,
+      WREN => WREN
+      );
+    end generate fifo_18_inst;
+   
+  fifo_18_36_inst : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36 ) generate 
+    begin
+    fifo_18_36_inst : fifo18_36
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DO_REG => 1,
+      EN_SYN => FALSE,
+      FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH,
+      SIM_MODE => SIM_MODE
+      )
+   port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => RDCLK,
+      RDEN => RDEN,
+      RST => RST,
+      WRCLK => WRCLK,
+      WREN => WREN
+      );
+   end generate fifo_18_36_inst; 
+
+  fifo_36_inst : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH <= 36 ) generate 
+    begin
+    fifo_36_inst : FIFO36 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => 1,
+      EN_SYN => FALSE,
+      FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH,
+      SIM_MODE => SIM_MODE
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => RDCLK,
+      RDEN => RDEN,
+      RST => RST,
+      WRCLK => WRCLK,
+      WREN => WREN
+      );
+   end generate fifo_36_inst;
+
+  fifo_36_72_inst : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72 ) generate 
+    begin
+    fifo_36_72_inst : fifo36_72
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DO_REG => 1,
+      EN_SYN => FALSE,
+      FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH,
+      SIM_MODE => SIM_MODE
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DBITERR => OPEN,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      ECCPARITY => OPEN,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      SBITERR => OPEN,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => RDCLK,
+      RDEN => RDEN,
+      RST => RST,
+      WRCLK => WRCLK,
+      WREN => WREN
+      );
+   end generate fifo_36_72_inst; 
+  end generate v5;
+  -- end generate virtex5
+  -- begin generate virtex6
+  bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+    fifo_18_inst_bl : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH <= 18 ) generate 
+    begin
+    fifo_18_bl : FIFO18E1 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => 1,
+      EN_SYN => FALSE,
+      FIFO_MODE => "FIFO18",
+      FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH,
+      INIT => INIT(0 to 35),
+      SIM_DEVICE => sim_device_dp,
+      SRVAL => SRVAL(0 to 35)
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => RDCLK,
+      RDEN => RDEN,
+      REGCE => '1',
+      RST => RST,
+      RSTREG => '1',
+      WRCLK => WRCLK,
+      WREN => WREN
+      );
+    end generate fifo_18_inst_bl;
+    fifo_18_inst_bl_1 : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36 ) generate 
+    begin
+    fifo_18_bl_1 : FIFO18E1 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => 1,
+      EN_SYN => FALSE,
+      FIFO_MODE => "FIFO18_36",
+      FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH,
+      INIT => INIT(0 to 35),
+      SIM_DEVICE => sim_device_dp,
+      SRVAL => SRVAL(0 to 35)
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => RDCLK,
+      RDEN => RDEN,
+      REGCE => '1',
+      RST => RST,
+      RSTREG => '1',
+      WRCLK => WRCLK,
+      WREN => WREN
+      );
+    end generate fifo_18_inst_bl_1;   
+  fifo_36_inst_bl : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH <= 36 ) generate 
+    begin
+    fifo_36_bl : FIFO36E1 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => 1,
+      EN_SYN => FALSE,
+      FIFO_MODE => "FIFO36",
+      FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH,
+      INIT => INIT,
+      SIM_DEVICE => sim_device_dp,
+      SRVAL => SRVAL
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DBITERR => OPEN,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      ECCPARITY => OPEN,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      SBITERR => OPEN,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      INJECTDBITERR => '0',
+      INJECTSBITERR => '0',
+      RDCLK => RDCLK,
+      RDEN => RDEN,
+      REGCE => '1',
+      RST => RST,
+      RSTREG => '1',
+      WRCLK => WRCLK,
+      WREN => WREN
+      );
+   end generate fifo_36_inst_bl;
+   fifo_36_inst_bl_1 : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72 ) generate 
+    begin
+    fifo_36_bl_1 : FIFO36E1 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => 1,
+      EN_SYN => FALSE,
+      FIFO_MODE => "FIFO36_72",
+      FIRST_WORD_FALL_THROUGH => FIRST_WORD_FALL_THROUGH,
+      INIT => INIT,
+      SIM_DEVICE => sim_device_dp,
+      SRVAL => SRVAL
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DBITERR => OPEN,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      ECCPARITY => OPEN,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      SBITERR => OPEN,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      INJECTDBITERR => '0',
+      INJECTSBITERR => '0',
+      RDCLK => RDCLK,
+      RDEN => RDEN,
+      REGCE => '1',
+      RST => RST,
+      RSTREG => '1',
+      WRCLK => WRCLK,
+      WREN => WREN
+      );
+   end generate fifo_36_inst_bl_1;
+
+  end generate bl;
+  -- end generate virtex6
+  
+ end fifo_V;
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/FIFO_SYNC_MACRO.vhd

@@ -0,0 +1,934 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2007 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 13.1
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for FIFO
+-- /___/   /\     Filename : FIFO_SYNC_MACRO.vhd
+-- \   \  /  \    Timestamp : Fri April 18 2008 10:43:59 PST 2008
+--  \___\/\___\
+--
+-- Revision:
+--    04/04/08 - Initial version.
+--    01/11/12 - 639772, 604428 -Constrain DI, DO, add width checking.
+--    03/16/12 - fix for 7series
+-- End Revision
+
+----- CELL FIFO_SYNC_MACRO -----
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+use IEEE.numeric_std.all;
+
+library unisim;
+use unisim.VCOMPONENTS.all;
+
+library unimacro;
+use unimacro.VCOMPONENTS.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+entity FIFO_SYNC_MACRO is
+
+  generic (
+    ALMOST_FULL_OFFSET      : bit_vector := X"0080";
+    ALMOST_EMPTY_OFFSET     : bit_vector := X"0080"; 
+    DATA_WIDTH              : integer    := 4; 
+    DEVICE : string := "VIRTEX5";
+    DO_REG                  : integer    := 0;
+    FIFO_SIZE               : string := "18Kb";  
+    INIT                    : bit_vector := X"000000000000000000"; -- This parameter is valid only for Virtex6
+    SRVAL                   : bit_vector := X"000000000000000000"; -- This parameter is valid only for Virtex6
+    SIM_MODE                : string     := "SAFE" -- This parameter is valid only for Virtex5
+    );
+  port(
+    ALMOSTEMPTY : out std_logic;
+    ALMOSTFULL  : out std_logic;
+    DO          : out std_logic_vector(DATA_WIDTH-1 downto 0);
+    EMPTY       : out std_logic;
+    FULL        : out std_logic;
+    RDCOUNT     : out std_logic_vector(xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0);
+    RDERR       : out std_logic;
+    WRCOUNT     : out std_logic_vector(xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0);
+    WRERR       : out std_logic;
+
+    CLK         : in  std_logic;
+    DI          : in  std_logic_vector(DATA_WIDTH-1 downto 0);
+    RDEN        : in  std_logic;
+    RST         : in  std_logic;
+    WREN        : in  std_logic
+    );
+
+  end entity FIFO_SYNC_MACRO;
+
+  architecture fifo_V of FIFO_SYNC_MACRO is
+ 
+  function GetDWidth (
+    d_width : in integer;
+    func_fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      case d_width is
+        when 0|1|2|3|4 => func_width := 4;
+                         if(d_width = 0) then
+                         write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") );
+                         write( Message, STRING'(". This attribute must atleast be equal to 1 . ") );
+                         ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+                         DEALLOCATE (Message);
+                         end if;
+        when 5|6|7|8|9 => func_width := 8;
+        when 10 to 18 => func_width := 16;
+        when 19 to 36 => func_width := 32;
+        when 37 to 72 => if(func_fifo_size = "18Kb") then
+                         write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") );
+                         write( Message, STRING'(". Legal values of this attribute for FIFO_SIZE 18Kb are ") );
+                         write( Message, STRING'(" 1 to 36 ") );
+                         ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+                         DEALLOCATE (Message);
+                         else
+                         func_width := 64;
+                         end if;
+        when others =>   write( Message, STRING'("Illegal value of Attribute DATA_WIDTH : ") );
+                         write( Message, STRING'(". Legal values of this attribute are ") );
+                         write( Message, STRING'(" 1 to 36 for FIFO_SIZE of 18Kb and ") );
+                         write( Message, STRING'(" 1 to 72 for FIFO_SIZE of 36Kb .") );
+                         ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+                         DEALLOCATE (Message);
+                         func_width := 64;
+      end case;
+    else
+      func_width := 64;
+    end if;
+    return func_width;
+  end;
+  function GetD_Size (
+    d_size : in integer;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      case d_size is
+        when 0|1|2|3|4 => func_width := 4;
+        when 5|6|7|8|9 => func_width := 9;
+        when 10 to 18 => func_width := 18;
+        when 19 to 36 => func_width := 36;
+        when 37 to 72 => func_width := 72;
+        when others => func_width := 1;
+      end case;
+    else
+      func_width := 1;
+    end if;
+    return func_width;
+  end;
+
+  function GetDIPWidth (
+    d_width : in integer;
+    func_fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      case d_width is
+        when 9 => func_width := 1;
+        when 17 => func_width := 1;
+        when 18 => func_width := 2;
+        when 33 => func_width := 1;
+        when 34 => func_width := 2;
+        when 35 => func_width := 3;
+        when 36 => func_width := 4;
+        when 65 => func_width := 1;
+        when 66 => func_width := 2;
+        when 67 => func_width := 3;
+        when 68 => func_width := 4;
+        when 69 => func_width := 5;
+        when 70 => func_width := 6;
+        when 71 => func_width := 7;
+        when 72 => func_width := 8;
+        when others => func_width := 0;
+      end case;
+    else
+      func_width := 0;
+    end if;
+  return func_width;
+  end;
+  function GetDOPWidth (
+    d_width : in integer;
+    func_fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      case d_width is
+        when 9 => func_width := 1;
+        when 17 => func_width := 1;
+        when 18 => func_width := 2;
+        when 33 => func_width := 1;
+        when 34 => func_width := 2;
+        when 35 => func_width := 3;
+        when 36 => func_width := 4;
+        when 65 => func_width := 1;
+        when 66 => func_width := 2;
+        when 67 => func_width := 3;
+        when 68 => func_width := 4;
+        when 69 => func_width := 5;
+        when 70 => func_width := 6;
+        when 71 => func_width := 7;
+        when 72 => func_width := 8;
+        when others => func_width := 1;
+      end case;
+    else
+      func_width := 1;
+    end if;
+  return func_width;
+  end;
+
+  function GetCOUNTWidth (
+    d_width : in integer;
+    fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if(fifo_size = "18Kb") then
+        case d_width is
+          when 0|1|2|3|4 => func_width := 12;
+          when 5|6|7|8|9 => func_width := 11;
+          when 10 to 18 => func_width := 10;
+          when 19 to 36 => func_width := 9;
+          when others => func_width := 12;
+        end case;
+      elsif(fifo_size = "36Kb") then
+        case d_width is
+          when 0|1|2|3|4 => func_width := 13;
+          when 5|6|7|8|9 => func_width := 12;
+          when 10 to 18 => func_width := 11;
+          when 19 to 36 => func_width := 10;
+          when 37 to 72 => func_width := 9;
+          when others => func_width := 13;
+        end case;
+      end if;
+    else
+      func_width := 13;
+    end if;
+    return func_width;
+  end;
+
+  function GetMaxDWidth (
+    d_width : in integer;
+    fifo_size : in string; 
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if(DEVICE = "VIRTEX5") then
+      if (fifo_size = "18Kb" and d_width <= 18 ) then
+        func_width := 16;
+      elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then
+        func_width := 32;
+      elsif (fifo_size = "36Kb" and d_width <= 36 ) then
+        func_width := 32;
+      elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then
+        func_width := 64;
+      else
+        func_width := 64;
+      end if;
+    elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (fifo_size = "18Kb" and d_width <= 36 ) then
+        func_width := 32;
+      elsif (fifo_size = "36Kb" and d_width <= 72 ) then
+        func_width := 64;
+      else
+        func_width := 64;
+      end if;  -- end b1
+    else
+      func_width := 64;
+    end if;
+    return func_width;
+  end;
+  function GetMaxDPWidth (
+    d_width : in integer;
+    fifo_size : in string; 
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if(DEVICE = "VIRTEX5") then
+      if (fifo_size = "18Kb" and d_width <= 18 ) then
+        func_width := 2;
+      elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then
+        func_width := 4;
+      elsif (fifo_size = "36Kb" and d_width <= 36 ) then
+        func_width := 4;
+      elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then
+        func_width := 8;
+      else
+        func_width := 8;
+      end if;
+    elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (fifo_size = "18Kb" and d_width <= 36 ) then
+        func_width := 4;
+      elsif (fifo_size = "36Kb" and d_width <= 72 ) then
+        func_width := 8;
+      else
+        func_width := 8;
+      end if; -- end b2
+    else
+      func_width := 8;
+    end if;
+    return func_width;
+  end;
+  function GetFinalWidth (
+    d_width : in integer
+    ) return integer is
+    variable func_least_width : integer;
+  begin
+    if (d_width = 0) then
+      func_least_width := 1;
+    else
+      func_least_width := d_width;
+    end if;
+    return func_least_width;
+  end;
+  function GetMaxCOUNTWidth (
+    d_width : in integer;
+    fifo_size : in string; 
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(DEVICE = "VIRTEX5") then
+      if (fifo_size = "18Kb" and d_width <= 18 ) then
+        func_width := 12;
+      elsif (fifo_size = "18Kb" and d_width > 18 and d_width <= 36 ) then
+        func_width := 9;
+      elsif (fifo_size = "36Kb" and d_width <= 36 ) then
+        func_width := 13;
+      elsif (fifo_size = "36Kb" and d_width > 36 and d_width <= 72 ) then
+        func_width := 9;
+      else
+        func_width := 13;
+      end if;
+   elsif(DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (fifo_size = "18Kb" and d_width <= 36 ) then
+        func_width := 12;
+      elsif (fifo_size = "36Kb" and d_width <= 72 ) then
+        func_width := 13;
+      else
+        func_width := 13;
+      end if; -- end b3
+    else
+      func_width := 13;
+    end if;
+    return func_width;
+  end;
+
+  function GetFIFOSize (
+    fifo_size : in string; 
+    device  : in string
+    ) return boolean is
+    variable fifo_val : boolean;
+    variable Message : LINE;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if fifo_size = "18Kb" or fifo_size = "36Kb" then
+      fifo_val := TRUE;
+      else
+          fifo_val := FALSE;
+          write( Message, STRING'("Illegal value of Attribute FIFO_SIZE : ") );
+          write ( Message, FIFO_SIZE);
+          write( Message, STRING'(". Legal values of this attribute are ") );
+          write( Message, STRING'(" 18Kb or 36Kb ") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+      end if;
+    else
+      fifo_val := FALSE;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write ( Message, DEVICE);
+      write( Message, STRING'(". Allowed values of this attribute is ") );
+      write( Message, STRING'(" VIRTEX5, VIRTEX6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return fifo_val;
+  end;
+
+  function GetD_P (
+    dw : in integer;
+    device  : in string
+    ) return boolean is
+    variable dp : boolean;
+  begin
+    if(DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if dw = 9 or dw = 17 or dw = 18 or dw = 33 or dw = 34 or dw = 35 or dw = 36 or dw = 65 or dw = 66 or dw = 67 or dw = 68 or dw = 69 or dw = 70 or dw = 71 or dw = 72 then
+      dp := TRUE;
+       else
+          dp := FALSE;
+      end if;
+    else
+      dp := FALSE;
+    end if;
+    return dp;
+  end;
+
+   function GetSIMDev (
+    device  : in string
+    ) return string is
+  begin
+    if(DEVICE = "VIRTEX6") then
+      return "VIRTEX6";
+    else
+      return "7SERIES";
+      end if;
+  end;
+
+  function CheckRDCOUNT (
+    d_width : in integer;
+    fifo_size : in string;
+    device  : in string;
+    rd_vec : in integer
+    ) return boolean is
+    variable Message : LINE;
+  begin
+    if(fifo_size = "18Kb") then
+        if ((d_width > 0 and d_width <= 4) and rd_vec /= 12) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 12 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >4 and d_width <= 9) and rd_vec /= 11) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 11 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >=10 and d_width <=18) and rd_vec /= 10) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 10 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >19 and d_width <=36) and rd_vec /= 9) then
+          write( Message, STRING'(" .RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 9 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+	else
+	  return true;
+        end if;
+    elsif(fifo_size = "36Kb") then
+        if ((d_width > 0 and d_width <= 4) and rd_vec /= 13) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 13 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width > 4 and d_width <= 9) and rd_vec /= 12) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 12 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >=10 and d_width <=18) and rd_vec /= 11) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 11 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >18 and d_width <=36) and rd_vec /= 10) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 10 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >36 and d_width <=72) and rd_vec /= 9) then
+          write( Message, STRING'("RDCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .RDCOUNT must be of width 9 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+	else
+	  return true;
+	end if;
+      else
+        return true;
+      end if;
+  end;
+
+  function CheckWRCOUNT (
+    d_width : in integer;
+    fifo_size : in string;
+    device  : in string;
+    wr_vec : in integer
+    ) return boolean is
+    variable Message : LINE;
+  begin
+    if(fifo_size = "18Kb") then
+        if ((d_width > 0 and d_width <= 4) and wr_vec /= 12) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 12 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >4 and d_width <= 9) and wr_vec /= 11) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 11 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >=10 and d_width <=18) and wr_vec /= 10) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 10 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >19 and d_width <=36) and wr_vec /= 9) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 9 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+	else
+	  return true;
+	end if;
+      elsif(fifo_size = "36Kb") then
+        if ((d_width > 0 and d_width <= 4) and wr_vec /= 13) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 13 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width > 4 and d_width <= 9) and wr_vec /= 12) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 12 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >=10 and d_width <=18) and wr_vec /= 11) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 11 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >18 and d_width <=36) and wr_vec /= 10) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 10 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+        elsif ((d_width >36 and d_width <=72) and wr_vec /= 9) then
+          write( Message, STRING'("WRCOUNT port width incorrectly set for DATA_WIDTH : ") );
+          write( Message, DATA_WIDTH);
+          write( Message, STRING'(" .WRCOUNT must be of width 9 .") );
+          ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+          DEALLOCATE (Message);
+          return false;
+	else
+	  return true;
+	end if;
+      else
+        return true;
+      end if;
+  end;
+
+  constant fifo_size_val : boolean := GetFIFOSize(FIFO_SIZE, DEVICE);
+  constant data_p : boolean := GetD_P(DATA_WIDTH, DEVICE); 
+  constant count_width : integer := GetCOUNTWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant d_width : integer  := GetDWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant d_size : integer := GetD_Size(DATA_WIDTH, DEVICE);
+  constant dip_width : integer := GetDIPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant dop_width : integer := GetDOPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant fin_width : integer := GetFinalWidth(DATA_WIDTH);
+  constant sim_device_dp : string := GetSIMDev(DEVICE);
+  constant rdctleng : integer := RDCOUNT'length;
+  constant wrctleng : integer := WRCOUNT'length;
+  constant checkrdct : boolean := CheckRDCOUNT(DATA_WIDTH, FIFO_SIZE, DEVICE, rdctleng);
+  constant checkwrct : boolean := CheckWRCOUNT(DATA_WIDTH, FIFO_SIZE, DEVICE, wrctleng);
+
+
+  constant max_data_width : integer := GetMaxDWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant max_datap_width : integer := GetMaxDPWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+  constant max_count_width : integer := GetMaxCOUNTWidth(DATA_WIDTH, FIFO_SIZE, DEVICE);
+
+  signal di_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0');  
+  signal do_pattern : std_logic_vector(max_data_width-1 downto 0) := (others=>'0');  
+  signal dip_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0');  
+  signal dop_pattern : std_logic_vector(max_datap_width-1 downto 0) := (others=>'0');  
+  signal rdcount_pattern : std_logic_vector(max_count_width-1 downto 0) := (others =>'0');
+  signal wrcount_pattern : std_logic_vector(max_count_width-1 downto 0) := (others =>'0');
+  signal regce_pattern : std_logic := '0';
+  signal rstreg_pattern : std_logic := '0';
+  
+  begin
+    di1v5 : if  (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate 
+      digen1 : if (data_p = TRUE  and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate
+      begin 
+        dip_pattern(dip_width-1 downto 0) <= DI(fin_width-1 downto d_width) ;
+        di_pattern (d_width-1 downto 0) <= DI(d_width-1 downto 0);
+      end generate digen1;
+    end generate di1v5;
+
+    di2v5 : if  (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate 
+      digen2 : if (data_p = FALSE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate
+      begin 
+        di_pattern(fin_width-1 downto 0) <= DI(fin_width-1 downto 0);
+      end generate digen2;
+    end generate di2v5;
+
+    do1v5 : if  (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate 
+      dogen1 : if (data_p= TRUE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate
+      begin
+        DO <= (dop_pattern(dop_width-1 downto 0) & do_pattern(d_width-1 downto 0));
+      end generate dogen1;
+    end generate do1v5;
+
+    do2v5 : if  (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate 
+      dogen2 : if (data_p= FALSE and ((FIFO_SIZE = "18Kb" and DATA_WIDTH <= 36) or (FIFO_SIZE = "36Kb" and DATA_WIDTH <= 72) ) ) generate
+      begin
+        DO <= do_pattern(fin_width-1 downto 0);
+      end generate dogen2;
+    end generate do2v5;
+ 
+    RDCOUNT <= rdcount_pattern(count_width-1 downto 0); 
+    WRCOUNT <= wrcount_pattern(count_width-1 downto 0); 
+    regce_pattern <= '1' when (DO_REG = 1) else '0';
+    rstreg_pattern <= '1' when (DO_REG = 1) else '0';
+  
+  -- begin generate virtex5
+  v5 : if (DEVICE = "VIRTEX5") generate
+    fifo_18_inst : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH <=18 ) generate 
+    begin
+    fifo_18_inst : FIFO18 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => DO_REG,
+      EN_SYN => TRUE,
+      FIRST_WORD_FALL_THROUGH => FALSE,
+      SIM_MODE => SIM_MODE
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => CLK,
+      RDEN => RDEN,
+      RST => RST,
+      WRCLK => CLK,
+      WREN => WREN
+      );
+    end generate fifo_18_inst;
+   
+  fifo_18_36_inst : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36 ) generate 
+    begin
+    fifo_18_36_inst : fifo18_36
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DO_REG => DO_REG,
+      EN_SYN => TRUE,
+      FIRST_WORD_FALL_THROUGH => FALSE,
+      SIM_MODE => SIM_MODE
+      )
+   port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => CLK,
+      RDEN => RDEN,
+      RST => RST,
+      WRCLK => CLK,
+      WREN => WREN
+      );
+   end generate fifo_18_36_inst; 
+
+  fifo_36_inst : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH <= 36 ) generate 
+    begin
+    fifo_36_inst : FIFO36 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => DO_REG,
+      EN_SYN => TRUE,
+      FIRST_WORD_FALL_THROUGH => FALSE,
+      SIM_MODE => SIM_MODE
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => CLK,
+      RDEN => RDEN,
+      RST => RST,
+      WRCLK => CLK,
+      WREN => WREN
+      );
+   end generate fifo_36_inst;
+
+  fifo_36_72_inst : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72 ) generate 
+    begin
+    fifo_36_72_inst : fifo36_72
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DO_REG => DO_REG,
+      EN_SYN => TRUE,
+      FIRST_WORD_FALL_THROUGH => FALSE,
+      SIM_MODE => SIM_MODE
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DBITERR => OPEN,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      ECCPARITY => OPEN,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      SBITERR => OPEN,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => CLK,
+      RDEN => RDEN,
+      RST => RST,
+      WRCLK => CLK,
+      WREN => WREN
+      );
+   end generate fifo_36_72_inst; 
+  end generate v5;
+  -- end generate virtex5
+  -- begin generate virtex6
+  bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+    fifo_18_inst_bl : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH <= 18 ) generate 
+    begin
+    fifo_18_bl : FIFO18E1 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => DO_REG,
+      EN_SYN => TRUE,
+      FIFO_MODE => "FIFO18",
+      FIRST_WORD_FALL_THROUGH => FALSE,
+      INIT => INIT(0 to 35),
+      SIM_DEVICE => sim_device_dp,
+      SRVAL => SRVAL(0 to 35)
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => CLK,
+      RDEN => RDEN,
+      REGCE => regce_pattern,
+      RST => RST,
+      RSTREG => rstreg_pattern,
+      WRCLK => CLK,
+      WREN => WREN
+      );
+    end generate fifo_18_inst_bl;
+    fifo_18_inst_bl_1 : if ( FIFO_SIZE = "18Kb" and DATA_WIDTH > 18 and DATA_WIDTH <= 36 ) generate 
+    begin
+    fifo_18_bl_1 : FIFO18E1 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => DO_REG,
+      EN_SYN => TRUE,
+      FIFO_MODE => "FIFO18_36",
+      FIRST_WORD_FALL_THROUGH => FALSE,
+      INIT => INIT(0 to 35),
+      SIM_DEVICE => sim_device_dp,
+      SRVAL => SRVAL(0 to 35)
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      RDCLK => CLK,
+      RDEN => RDEN,
+      REGCE => regce_pattern,
+      RST => RST,
+      RSTREG => rstreg_pattern,
+      WRCLK => CLK,
+      WREN => WREN
+      );
+    end generate fifo_18_inst_bl_1;
+   
+  fifo_36_inst_bl : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH <= 36 ) generate 
+    begin
+    fifo_36_bl : FIFO36E1 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => DO_REG,
+      EN_SYN => TRUE,
+      FIFO_MODE => "FIFO36",
+      FIRST_WORD_FALL_THROUGH => FALSE,
+      INIT => INIT,
+      SIM_DEVICE => sim_device_dp,
+      SRVAL => SRVAL
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DBITERR => OPEN,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      ECCPARITY => OPEN,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      SBITERR => OPEN,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      INJECTDBITERR => '0',
+      INJECTSBITERR => '0',
+      RDCLK => CLK,
+      RDEN => RDEN,
+      REGCE => regce_pattern,
+      RST => RST,
+      RSTREG => rstreg_pattern,
+      WRCLK => CLK,
+      WREN => WREN
+      );
+   end generate fifo_36_inst_bl;
+   fifo_36_inst_bl_1 : if ( FIFO_SIZE = "36Kb" and DATA_WIDTH > 36 and DATA_WIDTH <= 72 ) generate 
+    begin
+    fifo_36_bl_1 : FIFO36E1 
+    generic map (
+      ALMOST_FULL_OFFSET => ALMOST_FULL_OFFSET,
+      ALMOST_EMPTY_OFFSET => ALMOST_EMPTY_OFFSET, 
+      DATA_WIDTH => d_size,
+      DO_REG => DO_REG,
+      EN_SYN => TRUE,
+      FIFO_MODE => "FIFO36_72",
+      FIRST_WORD_FALL_THROUGH => FALSE,
+      INIT => INIT,
+      SIM_DEVICE => sim_device_dp,
+      SRVAL => SRVAL
+      )
+    port map (
+      ALMOSTEMPTY => ALMOSTEMPTY,
+      ALMOSTFULL => ALMOSTFULL,
+      DBITERR => OPEN,
+      DO => do_pattern,
+      DOP => dop_pattern,
+      ECCPARITY => OPEN,
+      EMPTY => EMPTY,
+      FULL => FULL,
+      RDCOUNT => rdcount_pattern,
+      RDERR => RDERR,
+      SBITERR => OPEN,
+      WRCOUNT => wrcount_pattern,
+      WRERR => WRERR,
+      DI => di_pattern,
+      DIP => dip_pattern,
+      INJECTDBITERR => '0',
+      INJECTSBITERR => '0',
+      RDCLK => CLK,
+      RDEN => RDEN,
+      REGCE => regce_pattern,
+      RST => RST,
+      RSTREG => rstreg_pattern,
+      WRCLK => CLK,
+      WREN => WREN
+      );
+   end generate fifo_36_inst_bl_1;
+
+
+  end generate bl;
+  -- end generate virtex6
+  
+ end fifo_V;
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/MACC_MACRO.vhd

@@ -0,0 +1,558 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2015 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 2015.3
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for DSP48
+-- /___/   /\     Filename : MACC_MACRO.vhd
+-- \   \  /  \
+--  \___\/\___\
+--
+-- Revision:
+--    06/06/08 - Initial version.
+--    04/09/15 - 852167 - align with verilog
+-- End Revision
+
+----- CELL MACC_MACRO -----
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+
+entity MACC_MACRO is
+  generic ( 
+    DEVICE : string := "VIRTEX5";
+            LATENCY : integer := 3;
+            WIDTH_A : integer := 25;
+            WIDTH_B : integer := 18;
+            WIDTH_P : integer := 48
+       );
+
+  port (
+      P : out std_logic_vector(WIDTH_P-1 downto 0);
+      A : in std_logic_vector(WIDTH_A-1 downto 0);   
+      ADDSUB : in std_logic;
+      B : in std_logic_vector(WIDTH_B-1 downto 0);  
+      CARRYIN : in std_logic; 
+      CE : in std_logic;
+      CLK : in std_logic;
+      LOAD : in std_logic;
+      LOAD_DATA : in std_logic_vector(WIDTH_P-1 downto 0);   
+      RST : in std_logic
+     );   
+end entity MACC_MACRO;
+
+architecture macc of MACC_MACRO is
+
+  function CheckDevice (
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write ( Message, DEVICE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckWidthA (
+    widtha : in integer;
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (widtha > 0 and widtha <= 25) then
+      func_val := true;
+      else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_A : ") );
+      write ( Message, WIDTH_A);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 25 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    -- begin s1
+    else
+      if (DEVICE = "SPARTAN6" and (widtha > 0 and widtha <= 18)) then
+        func_val := true;
+      else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_A : ") );
+      write ( Message, WIDTH_A);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 18 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+      end if;
+    -- end s1
+    end if;
+    return func_val;
+  end;
+  function CheckWidthB (
+    widthb : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (widthb > 0 and widthb <= 18 ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_B : ") );
+      write ( Message, WIDTH_B);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 18 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+    function GetWidthA (
+    device : in string
+    ) return integer is
+    variable func_val : integer;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      func_val := 25;
+    else
+      func_val := 18;
+    end if;
+    return func_val;
+  end;
+  function GetABREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 2 or LATENCY = 3) then
+      func_width := 1;
+    elsif (LATENCY = 4 ) then
+      func_width := 2;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetABREG1_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 2 or LATENCY = 3 or LATENCY = 4) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetABREG0_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 4) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+
+  function GetMREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 3 or LATENCY = 4 ) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetPREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3 or LATENCY = 4 ) then
+      func_width := 1;
+    else
+      func_width := 0;
+      write( Message, STRING'("Illegal value of Attribute LATENCY : ") );
+      write ( Message, LATENCY);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 4 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_width;
+  end;
+  function GetOPMODE_IN (
+    device : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      func_width := 7;
+    elsif (DEVICE = "SPARTAN6") then
+      func_width := 8;
+    else
+      func_width := 8;
+    end if;
+    return func_width;
+  end;
+
+
+--Signal Declarations:   
+
+
+   constant OPMODE_WIDTH : integer := GetOPMODE_IN(DEVICE);
+   constant ChkDevice : boolean := CheckDevice(DEVICE);
+   constant ChkWidthA : boolean := CheckWidthA(WIDTH_A, DEVICE);
+   constant ChkWidthB : boolean := CheckWidthB(WIDTH_B);
+   constant MaxWidthA : integer := GetWidthA(DEVICE);
+   constant AREG_IN : integer := GetABREG_IN(LATENCY);
+   constant BREG_IN : integer := GetABREG_IN(LATENCY);
+   constant A0REG_IN : integer := GetABREG0_IN(LATENCY);
+   constant B0REG_IN : integer := GetABREG0_IN(LATENCY);
+   constant A1REG_IN : integer := GetABREG1_IN(LATENCY);
+   constant B1REG_IN : integer := GetABREG1_IN(LATENCY);
+   constant MREG_IN : integer := GetMREG_IN(LATENCY);
+   constant PREG_IN : integer := GetPREG_IN(LATENCY);
+
+   signal A_INP :  std_logic_vector(24 downto 0) := "0000000000000000000000000";
+   signal A_IN :  std_logic_vector(29 downto 0) := "000000000000000000000000000000";
+   signal B_IN :  std_logic_vector(17 downto 0) := "000000000000000000";
+   signal RESULT_OUT :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal LOAD_DATA_IN :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal OPMODE_IN :  std_logic_vector((OPMODE_WIDTH-1) downto 0);
+   signal ALUMODE_IN :  std_logic_vector(3 downto 0);
+   
+   signal CEA1_IN :  std_logic;
+   signal CEA2_IN :  std_logic;
+   signal CEB1_IN :  std_logic;
+   signal CEB2_IN :  std_logic;
+
+  
+
+-- Architecture Section: instantiation  
+begin
+
+   CEA1_IN <=  CE when (AREG_IN = 2) else '0';
+   CEA2_IN <=  CE when (AREG_IN = 1 or AREG_IN = 2) else '0';
+   CEB1_IN <=  CE when (BREG_IN = 2) else '0';
+   CEB2_IN <=  CE when (BREG_IN = 1 or BREG_IN = 2) else '0';
+
+   ALUMODE_IN <= "00" & (not (ADDSUB)) & (not (ADDSUB));
+ 
+   v : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+   OPMODE_IN <= "01" & LOAD & "0101";
+   end generate v;
+
+   s : if (DEVICE = "SPARTAN6") generate
+   OPMODE_IN <= (not (ADDSUB)) & (not (ADDSUB)) & "001" & LOAD & "01";
+   end generate s;
+
+  load1 : if (WIDTH_P = 48) generate
+    begin
+      LOAD_DATA_IN <= LOAD_DATA;
+    end generate load1;
+  load2 : if (WIDTH_P < 48) generate
+    begin
+      l1: for i in 47 downto WIDTH_P generate
+            LOAD_DATA_IN(i) <= '0';
+          end generate;
+            LOAD_DATA_IN(WIDTH_P-1 downto 0) <= LOAD_DATA;
+   end generate load2;
+
+  multa : if (WIDTH_A = MaxWidthA) generate
+    begin 
+      A_INP((MaxWidthA-1) downto 0) <= A;
+      A_IN <= "00000" & A_INP;
+    end generate multa;
+  multb : if (WIDTH_B = 18) generate
+    begin 
+      B_IN <= B;
+    end generate multb;
+  multas : if (WIDTH_A < MaxWidthA) generate
+    begin 
+      sa: for i in (MaxWidthA-1) downto WIDTH_A generate
+            A_INP(i) <= A((WIDTH_A-1));
+          end generate;
+            A_INP(WIDTH_A-1 downto 0) <= A;
+            A_IN <= "00000" & A_INP;
+    end generate multas;
+  multbs : if (WIDTH_B < 18) generate
+    begin 
+      sb: for i in 17 downto WIDTH_B generate
+            B_IN(i) <= B((WIDTH_B-1));
+          end generate;
+            B_IN(WIDTH_B-1 downto 0) <= B;
+    end generate multbs;
+
+  P <= RESULT_OUT(WIDTH_P-1 downto 0);
+
+  -- begin generate virtex5
+  v5 : if DEVICE = "VIRTEX5" generate
+    v5_1 : if ((LATENCY >= 0) and (LATENCY <= 2)) generate
+    begin
+      DSP48E_1: DSP48E 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,           
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          MREG => MREG_IN,           
+          PREG => PREG_IN,
+          USE_MULT => "MULT"           
+          )
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => A_IN,          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => B_IN,          
+          BCIN => "000000000000000000",    
+          C => LOAD_DATA_IN,           
+          CARRYCASCIN => '0', 
+          CARRYIN => CARRYIN, 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE, 
+          CEM => CE,       
+          CEMULTCARRYIN => CE,
+          CEP => CE,       
+          CLK => CLK,       
+          MULTSIGNIN => '0', 
+          OPMODE => OPMODE_IN(6 downto 0), 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTM => RST, 
+          RSTP => RST 
+       );
+     end generate v5_1;
+    v5_2 : if ((LATENCY =3) or (LATENCY = 4)) generate
+          begin
+      DSP48E_1: DSP48E 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,           
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          MREG => MREG_IN,           
+          PREG => PREG_IN,
+          USE_MULT => "MULT_S"           
+          )
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => A_IN,          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => B_IN,          
+          BCIN => "000000000000000000",    
+          C => LOAD_DATA_IN,           
+          CARRYCASCIN => '0', 
+          CARRYIN => CARRYIN, 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE, 
+          CEM => CE,       
+          CEMULTCARRYIN => CE,
+          CEP => CE,       
+          CLK => CLK,       
+          MULTSIGNIN => '0', 
+          OPMODE => OPMODE_IN(6 downto 0), 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTM => RST, 
+          RSTP => RST 
+       );
+    end generate v5_2;
+  end generate v5;
+  -- end generate virtex5
+  -- begin generate virtex6
+  bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+    begin
+      DSP48E_2: DSP48E1 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,   
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          MREG => MREG_IN,      
+          PREG => PREG_IN           
+          )
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => A_IN,          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => ALUMODE_IN, 
+          B => B_IN,          
+          BCIN => "000000000000000000",    
+          C => LOAD_DATA_IN,           
+          CARRYCASCIN => '0', 
+          CARRYIN => CARRYIN, 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEAD => '0',
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE,
+          CED => '0',
+          CEINMODE => '0', 
+          CEM => CE,       
+          CEP => CE,       
+          CLK => CLK,       
+          D => "0000000000000000000000000",
+          INMODE => "00000", 
+          MULTSIGNIN => '0', 
+          OPMODE => OPMODE_IN(6 downto 0), 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTD => RST,
+          RSTINMODE => RST,
+          RSTM => RST, 
+          RSTP => RST 
+       );
+  end generate bl;
+  -- end generate virtex6
+  -- begin generate spartan6
+  st : if DEVICE = "SPARTAN6" generate
+      begin
+       DSP48E_3: DSP48A1 
+        generic map (
+            A0REG => A0REG_IN,   
+            A1REG => A1REG_IN,   
+            B0REG => B0REG_IN,           
+            B1REG => B1REG_IN,           
+            MREG => MREG_IN,      
+            PREG => PREG_IN           
+            )
+         port map ( 
+            BCOUT => open,  
+            CARRYOUT => open, 
+            CARRYOUTF => open, 
+            M => open, 
+            P => RESULT_OUT,          
+            PCOUT => open,  
+            A => A_IN(17 downto 0),          
+            B => B_IN,          
+            C => LOAD_DATA_IN,           
+            CARRYIN => CARRYIN, 
+            CEA => CE,      
+            CEB => CE,      
+            CEC => CE,      
+            CECARRYIN => CE, 
+            CED => CE,
+            CEM => CE,       
+            CEOPMODE => CE, 
+            CEP => CE,       
+            CLK => CLK,       
+            D => "000000000000000000",
+            OPMODE => OPMODE_IN, 
+            PCIN => "000000000000000000000000000000000000000000000000",      
+            RSTA => RST,     
+            RSTB => RST,     
+            RSTC => RST,     
+            RSTCARRYIN => RST,     
+            RSTD => RST,
+            RSTM => RST, 
+            RSTOPMODE => RST,
+            RSTP => RST 
+         );
+  end generate st;
+  -- end generate spartan6
+end macc;
+
+
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/MULT_MACRO.vhd

@@ -0,0 +1,561 @@
+-------------------------------------------------------------------------------
+-- Copyright (c) 1995/2008 Xilinx, Inc.
+-- All Right Reserved.
+-------------------------------------------------------------------------------
+--   ____  ____
+--  /   /\/   /
+-- /___/  \  /    Vendor : Xilinx
+-- \   \   \/     Version : 14.1
+--  \   \         Description : Xilinx Functional Simulation Library Component
+--  /   /                  Macro for DSP48
+-- /___/   /\     Filename : MULT_MACRO.vhd
+-- \   \  /  \    Timestamp : Fri June 06 2008 10:43:59 PST 2008
+--  \___\/\___\
+--
+-- Revision:
+--    06/06/08 - Initial version.
+--    05/22/12 - 660408 - fix for latency 3 and 4
+-- End Revision
+
+----- CELL MULT_MACRO -----
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.std_logic_arith.all;
+use IEEE.std_logic_unsigned.all;
+
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+library STD;
+use STD.TEXTIO.ALL;
+
+
+entity MULT_MACRO is
+  generic ( 
+    DEVICE : string := "VIRTEX5";
+            LATENCY : integer := 3;
+            STYLE : string := "DSP";
+            WIDTH_A : integer := 18;
+            WIDTH_B : integer := 18
+       );
+
+  port (
+      P : out std_logic_vector((WIDTH_A+WIDTH_B)-1 downto 0);
+      A : in std_logic_vector(WIDTH_A-1 downto 0);   
+      B : in std_logic_vector(WIDTH_B-1 downto 0);   
+      CE : in std_logic;
+      CLK : in std_logic;   
+      RST : in std_logic
+     );   
+end entity MULT_MACRO;
+
+architecture mult of MULT_MACRO is
+
+  function CheckDevice (
+    device : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
+      write ( Message, DEVICE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" VIRTEX5, VIRTEX6, SPARTAN6, 7SERIES. ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckStyle (
+    style : in string
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (style = "AUTO" or style = "DSP" ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute STYLE : ") );
+      write ( Message, STYLE);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" AUTO, DSP ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function CheckWidthA (
+    widtha : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      if (widtha > 0 and widtha <= 25) then
+      func_val := true;
+      else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_A : ") );
+      write ( Message, WIDTH_A);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 25 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+      end if;
+    -- begin s1
+    else
+      if (DEVICE = "SPARTAN6" and widtha > 0 and widtha <= 18) then
+      func_val := true;
+      else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_A : ") );
+      write ( Message, WIDTH_A);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 18 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+      end if;
+    -- end s1
+    end if;
+    return func_val;
+  end;
+  function CheckWidthB (
+    widthb : in integer
+    ) return boolean is
+    variable func_val : boolean;
+    variable Message : LINE;
+  begin
+    if (widthb > 0 and widthb <= 18 ) then
+      func_val := true;
+    else
+      func_val := false;
+      write( Message, STRING'("Illegal value of Attribute WIDTH_B : ") );
+      write ( Message, WIDTH_B);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 1 to 18 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function GetWidthA (
+    device : in string
+    ) return integer is
+    variable func_val : integer;
+    variable Message : LINE;
+
+  begin
+    if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
+      func_val := 25;
+    else
+      func_val := 18;
+      DEALLOCATE (Message);
+    end if;
+    return func_val;
+  end;
+  function GetABREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 2 or LATENCY = 3) then
+      func_width := 1;
+    elsif (LATENCY = 4 ) then
+      func_width := 2;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetABREG1_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 2 or LATENCY = 3 or LATENCY = 4) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetABREG0_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 4) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetPREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if (LATENCY = 3 or LATENCY = 4 ) then
+      func_width := 1;
+    else
+      func_width := 0;
+    end if;
+    return func_width;
+  end;
+  function GetMREG_IN (
+    latency : in integer
+    ) return integer is
+    variable func_width : integer;
+    variable Message : LINE;
+  begin
+    if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3 or LATENCY = 4 ) then
+      func_width := 1;
+    elsif (LATENCY = 0) then
+      func_width := 0;
+    else
+      func_width := 0;
+      write( Message, STRING'("Illegal value of Attribute LATENCY : ") );
+      write ( Message, LATENCY);
+      write( Message, STRING'(". Legal values of this attribute are ") );
+      write( Message, STRING'(" 0 to 4 ") );
+      ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
+      DEALLOCATE (Message);
+    end if;
+    return func_width;
+  end;
+
+
+
+--Signal Declarations:   
+
+   signal A_IN :  std_logic_vector(24 downto 0) := "0000000000000000000000000";
+   signal A_INP :  std_logic_vector(29 downto 0) := "000000000000000000000000000000";
+   signal A_INST :  std_logic_vector(17 downto 0) := "000000000000000000";
+   signal B_IN :  std_logic_vector(17 downto 0) := "000000000000000000";
+   signal RESULT_OUT :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal RESULT_OUTST :  std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
+   signal CEA1_IN :  std_logic;
+   signal CEA2_IN :  std_logic;
+   signal CEB1_IN :  std_logic;
+   signal CEB2_IN :  std_logic;
+
+   constant ChkDevice : boolean := CheckDevice(DEVICE);
+   constant ChkStyle : boolean := CheckStyle(STYLE);
+   constant ChkWidthA : boolean := CheckWidthA(WIDTH_A);
+   constant ChkWidthB : boolean := CheckWidthB(WIDTH_B);
+   constant MaxWidthA : integer := GetWidthA(DEVICE);
+   constant AREG_IN : integer := GetABREG_IN(LATENCY);
+   constant BREG_IN : integer := GetABREG_IN(LATENCY);
+   constant A0REG_IN : integer := GetABREG0_IN(LATENCY);
+   constant B0REG_IN : integer := GetABREG0_IN(LATENCY);
+   constant A1REG_IN : integer := GetABREG1_IN(LATENCY);
+   constant B1REG_IN : integer := GetABREG1_IN(LATENCY);
+   constant MREG_IN : integer := GetMREG_IN(LATENCY);
+   constant PREG_IN : integer := GetPREG_IN(LATENCY);
+
+-- Architecture Section: instantiation  
+begin
+
+   CEA1_IN <=  CE when (AREG_IN = 2) else '0';
+   CEA2_IN <=  CE when (AREG_IN = 1 or AREG_IN = 2) else '0';
+   CEB1_IN <=  CE when (BREG_IN = 2) else '0';
+   CEB2_IN <=  CE when (BREG_IN = 1 or BREG_IN = 2) else '0';
+
+  multa : if (WIDTH_A = MaxWidthA) generate
+    begin 
+      
+    ga1 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+      A_IN(MaxWidthA-1 downto 0) <= A;
+    end generate ga1;
+    ga2 : if (DEVICE = "SPARTAN6") generate
+      A_INST(MaxWidthA-1 downto 0) <= A;
+    end generate ga2;
+    end generate multa;
+  multb : if (WIDTH_B = 18) generate
+    begin 
+      B_IN <= B;
+    end generate multb;
+  multas : if (WIDTH_A < MaxWidthA) generate
+    begin 
+          g1 : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+             A_IN((MaxWidthA-1) downto (MaxWidthA-WIDTH_A)) <= A;
+          g3 : for i in ((MaxWidthA-1)-WIDTH_A) downto 0 generate
+             A_IN(i) <= '0';
+              end generate g3;
+          end generate g1;
+          -- begin s2
+          g2 : if (DEVICE = "SPARTAN6") generate
+            A_INST((MaxWidthA-1) downto (MaxWidthA-WIDTH_A)) <= A;
+          g4 : for i in ((MaxWidthA-1)-WIDTH_A) downto 0 generate
+            A_INST(i) <= '0';
+          end generate g4;
+          end generate g2;
+          -- end s2
+    end generate multas;
+  multbs : if (WIDTH_B < 18) generate
+    begin 
+      sb: for i in (17-WIDTH_B) downto 0 generate
+            B_IN(i) <= '0';
+          end generate;
+            B_IN(17 downto (18-(WIDTH_B))) <= B;
+    end generate multbs;
+ 
+  A_INP  <= "00000" & A_IN ;
+ 
+   p1: if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+     P <= RESULT_OUT(42 downto (42- ((WIDTH_A+WIDTH_B)-1)));
+   end generate p1;
+   -- begin s2
+   p2: if (DEVICE = "SPARTAN6") generate
+     P <= RESULT_OUTST(35 downto (35- ((WIDTH_A+WIDTH_B)-1)));
+   end generate p2;
+   -- end s2
+
+  -- begin generate virtex5
+  v5 : if DEVICE = "VIRTEX5" generate
+    v5_1 : if LATENCY = 0 generate
+    begin
+      DSP48E_1: DSP48E 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,           
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          MREG => MREG_IN,           
+          PREG => PREG_IN,
+          USE_MULT => "MULT"           
+          )
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => A_INP,          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => "0000", 
+          B => B_IN,          
+          BCIN => "000000000000000000",    
+          C => "000000000000000000000000000000000000000000000000",           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE, 
+          CEM => CE,       
+          CEMULTCARRYIN => '0',
+          CEP => CE,       
+          CLK => CLK,       
+          MULTSIGNIN => '0', 
+          OPMODE => "0000101", 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTM => RST, 
+          RSTP => RST 
+       );
+    end generate v5_1;
+    v5_2 : if LATENCY > 0 generate
+    begin
+      DSP48E_1: DSP48E 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,           
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,           
+          MREG => MREG_IN,           
+          PREG => PREG_IN,
+          USE_MULT => "MULT_S"           
+          )
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => A_INP,          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => "0000", 
+          B => B_IN,          
+          BCIN => "000000000000000000",    
+          C => "000000000000000000000000000000000000000000000000",           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE, 
+          CEM => CE,       
+          CEMULTCARRYIN => '0',
+          CEP => CE,       
+          CLK => CLK,       
+          MULTSIGNIN => '0', 
+          OPMODE => "0000101", 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTM => RST, 
+          RSTP => RST 
+       );
+    end generate v5_2;
+  end generate v5;
+  -- end generate virtex5
+  -- begin generate virtex6
+  bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
+    begin
+      DSP48E_2: DSP48E1 
+        generic map (
+          ACASCREG => AREG_IN,       
+          AREG => AREG_IN,   
+          ADREG => 0,
+          BCASCREG => BREG_IN,       
+          BREG => BREG_IN,
+          DREG => 0,
+          MREG => MREG_IN,      
+          PREG => PREG_IN           
+          )
+       port map (
+          ACOUT => open,   
+          BCOUT => open,  
+          CARRYCASCOUT => open, 
+          CARRYOUT => open, 
+          MULTSIGNOUT => open, 
+          OVERFLOW => open, 
+          P => RESULT_OUT,          
+          PATTERNBDETECT => open, 
+          PATTERNDETECT => open, 
+          PCOUT => open,  
+          UNDERFLOW => open, 
+          A => A_INP,          
+          ACIN => "000000000000000000000000000000",    
+          ALUMODE => "0000", 
+          B => B_IN,          
+          BCIN => "000000000000000000",    
+          C => "000000000000000000000000000000000000000000000000",           
+          CARRYCASCIN => '0', 
+          CARRYIN => '0', 
+          CARRYINSEL => "000", 
+          CEA1 => CEA1_IN,      
+          CEA2 => CEA2_IN,      
+          CEAD => '0',
+          CEALUMODE => CE, 
+          CEB1 => CEB1_IN,      
+          CEB2 => CEB2_IN,      
+          CEC => CE,      
+          CECARRYIN => CE, 
+          CECTRL => CE,
+          CED => '0',
+          CEINMODE => '0', 
+          CEM => CE,       
+          CEP => CE,       
+          CLK => CLK,       
+          D => "0000000000000000000000000",
+          INMODE => "00000", 
+          MULTSIGNIN => '0', 
+          OPMODE => "0000101", 
+          PCIN => "000000000000000000000000000000000000000000000000",      
+          RSTA => RST,     
+          RSTALLCARRYIN => RST, 
+          RSTALUMODE => RST, 
+          RSTB => RST,     
+          RSTC => RST,     
+          RSTCTRL => RST, 
+          RSTD => RST,
+          RSTINMODE => RST,
+          RSTM => RST, 
+          RSTP => RST 
+       );
+  end generate bl;
+  -- end generate virtex6
+  -- begin generate spartan6
+  st : if DEVICE = "SPARTAN6" generate
+      begin
+       DSP48E_3: DSP48A1 
+        generic map (
+            A0REG => A0REG_IN,   
+            A1REG => A1REG_IN,   
+            B0REG => B0REG_IN,           
+            B1REG => B1REG_IN,           
+            MREG => MREG_IN,      
+            PREG => PREG_IN           
+          )
+         port map ( 
+            BCOUT => open,  
+            CARRYOUT => open, 
+            CARRYOUTF => open, 
+            --M => RESULT_OUTST, 
+            M => open, 
+            P => RESULT_OUTST,          
+            PCOUT => open,  
+            A => A_INST,          
+            B => B_IN,          
+            C => "000000000000000000000000000000000000000000000000",           
+            CARRYIN => '0', 
+            CEA => CE,      
+            CEB => CE,      
+            CEC => CE,      
+            CECARRYIN => CE, 
+            CED => CE,
+            CEM => CE,       
+            CEOPMODE => CE, 
+            CEP => CE,       
+            CLK => CLK,       
+            D => "000000000000000000",
+            OPMODE => "00000001", 
+            PCIN => "000000000000000000000000000000000000000000000000",      
+            RSTA => RST,     
+            RSTB => RST,     
+            RSTC => RST,     
+            RSTCARRYIN => RST,     
+            RSTD => RST,
+            RSTM => RST, 
+            RSTOPMODE => RST,
+            RSTP => RST 
+         );
+  end generate st;
+ -- end generate spartan6
+
+end mult;
+
+
+

resources/dide-lsp/static/vhdl_std_lib/unimacro/unimacro_VCOMP.vhd

@@ -0,0 +1,802 @@
+--**************************************************************
+--  Copyright (c) 2008 Xilinx, Inc.  All rights reserved.
+--  File Name    : unimacro_VCOMP.vhd
+--  Library      : unisim
+--  Release      : 11.1
+--  Entity Count : 12
+--  Time         : Fri Mar  2 10:51:46 2012
+--  Generated by : gencomp.pl
+--**************************************************************
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+package VCOMPONENTS is
+
+  FUNCTION xil_UNM_GCW (
+  d_width : in integer;
+  fifo_size : in string;
+  device  : in string
+  ) return integer;
+
+-- START COMPONENT
+----- component ADDMACC_MACRO -----
+component ADDMACC_MACRO
+  generic (
+     DEVICE : string := "VIRTEX6";
+     LATENCY : integer := 4;
+     WIDTH_MULTIPLIER : integer := 18;
+     WIDTH_PREADD : integer := 25;
+     WIDTH_PRODUCT : integer := 48
+  );
+  port (
+     PRODUCT : out std_logic_vector(WIDTH_PRODUCT-1 downto 0);
+     CARRYIN : in std_logic;
+     CE : in std_logic;
+     CLK : in std_logic;
+     LOAD : in std_logic;
+     LOAD_DATA : in std_logic_vector(WIDTH_PRODUCT-1 downto 0);
+     MULTIPLIER : in std_logic_vector(WIDTH_MULTIPLIER-1 downto 0);
+     PREADD1 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
+     PREADD2 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
+     RST : in std_logic
+  );
+end component;
+
+----- component ADDSUB_MACRO -----
+component ADDSUB_MACRO
+  generic (
+     DEVICE : string := "VIRTEX5";
+     LATENCY : integer := 2;
+     MODEL_TYPE : integer := 0;
+     STYLE : string := "DSP";
+     VERBOSITY : integer := 0;
+     WIDTH : integer := 48;
+     WIDTH_B : integer := 48;
+     WIDTH_RESULT : integer := 48
+  );
+  port (
+     CARRYOUT : out std_logic;
+     RESULT : out std_logic_vector(WIDTH-1 downto 0);
+     A : in std_logic_vector(WIDTH-1 downto 0);
+     ADD_SUB : in std_logic;
+     B : in std_logic_vector(WIDTH-1 downto 0);
+     CARRYIN : in std_logic;
+     CE : in std_logic;
+     CLK : in std_logic;
+     RST : in std_logic
+  );
+end component;
+
+----- component BRAM_SDP_MACRO -----
+component BRAM_SDP_MACRO
+  generic (
+     BRAM_SIZE : string := "18Kb";
+     DEVICE : string := "VIRTEX5";
+     DO_REG : integer := 0;
+     INIT : bit_vector := X"000000000000000000";
+     INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_FILE : string := "NONE";
+     READ_WIDTH : integer := 0;
+     SIM_COLLISION_CHECK : string := "ALL";
+     SIM_MODE : string := "SAFE";
+     SRVAL : bit_vector := X"000000000000000000";
+     WRITE_MODE : string := "WRITE_FIRST";
+     WRITE_WIDTH : integer := 0
+  );
+  port (
+     DO : out std_logic_vector(READ_WIDTH-1 downto 0);
+     DI : in std_logic_vector(WRITE_WIDTH-1 downto 0);
+     RDADDR : in std_logic_vector;
+     RDCLK : in std_ulogic;
+     RDEN : in std_ulogic;
+     REGCE : in std_ulogic;
+     RST : in std_ulogic;
+     WE : in std_logic_vector;
+     WRADDR : in std_logic_vector;
+     WRCLK : in std_ulogic;
+     WREN : in std_ulogic
+  );
+end component;
+
+----- component BRAM_SINGLE_MACRO -----
+component BRAM_SINGLE_MACRO
+  generic (
+     BRAM_SIZE : string := "18Kb";
+     DEVICE : string := "VIRTEX5";
+     DO_REG : integer := 0;
+     INIT : bit_vector := X"000000000000000000";
+     INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_FILE : string := "NONE";
+     READ_WIDTH : integer := 1;
+     SIM_MODE : string := "SAFE";
+     SRVAL : bit_vector := X"000000000000000000";
+     WRITE_MODE : string := "WRITE_FIRST";
+     WRITE_WIDTH : integer := 1
+  );
+  port (
+     DO : out std_logic_vector(READ_WIDTH-1 downto 0);
+     ADDR : in std_logic_vector;
+     CLK : in std_ulogic;
+     DI : in std_logic_vector(WRITE_WIDTH-1 downto 0);
+     EN : in std_ulogic;
+     REGCE : in std_ulogic;
+     RST : in std_ulogic;
+     WE : in std_logic_vector
+  );
+end component;
+
+----- component BRAM_TDP_MACRO -----
+component BRAM_TDP_MACRO
+  generic (
+     BRAM_SIZE : string := "18Kb";
+     DEVICE : string := "VIRTEX5";
+     DOA_REG : integer := 0;
+     DOB_REG : integer := 0;
+     INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INITP_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_04 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_05 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_06 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_07 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_08 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_09 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_0F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_10 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_11 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_12 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_13 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_14 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_15 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_16 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_17 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_18 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_19 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_1F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_20 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_21 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_22 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_23 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_24 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_25 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_26 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_27 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_28 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_29 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_2F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_30 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_31 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_32 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_33 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_34 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_35 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_36 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_37 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_38 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_39 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_3F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_40 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_41 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_42 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_43 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_44 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_45 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_46 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_47 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_48 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_49 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_4F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_50 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_51 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_52 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_53 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_54 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_55 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_56 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_57 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_58 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_59 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_5F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_60 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_61 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_62 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_63 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_64 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_65 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_66 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_67 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_68 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_69 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_6F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_70 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_71 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_72 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_73 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_74 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_75 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_76 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_77 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_78 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_79 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7A : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7B : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7C : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7D : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7E : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_7F : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000";
+     INIT_A : bit_vector := X"000000000";
+     INIT_B : bit_vector := X"000000000";
+     INIT_FILE : string := "NONE";
+     READ_WIDTH_A : integer := 1;
+     READ_WIDTH_B : integer := 1;
+     SIM_COLLISION_CHECK : string := "ALL";
+     SIM_MODE : string := "SAFE";
+     SRVAL_A : bit_vector := X"000000000";
+     SRVAL_B : bit_vector := X"000000000";
+     WRITE_MODE_A : string := "WRITE_FIRST";
+     WRITE_MODE_B : string := "WRITE_FIRST";
+     WRITE_WIDTH_A : integer := 1;
+     WRITE_WIDTH_B : integer := 1
+  );
+  port (
+     DOA : out std_logic_vector(READ_WIDTH_A-1 downto 0);
+     DOB : out std_logic_vector(READ_WIDTH_B-1 downto 0);
+     ADDRA : in std_logic_vector;
+     ADDRB : in std_logic_vector;
+     CLKA : in std_ulogic;
+     CLKB : in std_ulogic;
+     DIA : in std_logic_vector(WRITE_WIDTH_A-1 downto 0);
+     DIB : in std_logic_vector(WRITE_WIDTH_B-1 downto 0);
+     ENA : in std_ulogic;
+     ENB : in std_ulogic;
+     REGCEA : in std_ulogic;
+     REGCEB : in std_ulogic;
+     RSTA : in std_ulogic;
+     RSTB : in std_ulogic;
+     WEA : in std_logic_vector;
+     WEB : in std_logic_vector
+  );
+end component;
+
+----- component COUNTER_LOAD_MACRO -----
+component COUNTER_LOAD_MACRO
+  generic (
+     COUNT_BY : std_logic_vector := X"000000000001";
+     DEVICE : string := "VIRTEX5";
+     STYLE : string := "AUTO";
+     WIDTH_DATA : integer := 48
+  );
+  port (
+     Q : out std_logic_vector(WIDTH_DATA-1 downto 0);
+     CE : in std_logic;
+     CLK : in std_logic;
+     DIRECTION : in std_logic;
+     LOAD : in std_logic;
+     LOAD_DATA : in std_logic_vector(WIDTH_DATA-1 downto 0);
+     RST : in std_logic
+  );
+end component;
+
+----- component COUNTER_TC_MACRO -----
+component COUNTER_TC_MACRO
+  generic (
+     COUNT_BY : std_logic_vector := X"000000000001";
+     DEVICE : string := "VIRTEX5";
+     DIRECTION : string := "UP";
+     RESET_UPON_TC : string := "FALSE";
+     STYLE : string := "AUTO";
+     TC_VALUE : std_logic_vector := X"000000000000";
+     WIDTH_DATA : integer := 48
+  );
+  port (
+     Q : out std_logic_vector(WIDTH_DATA-1 downto 0);
+     TC : out std_logic;
+     CE : in std_logic;
+     CLK : in std_logic;
+     RST : in std_logic
+  );
+end component;
+
+----- component EQ_COMPARE_MACRO -----
+component EQ_COMPARE_MACRO
+  generic (
+     DEVICE : string := "VIRTEX5";
+     LATENCY : integer := 2;
+     MASK : bit_vector := X"000000000000";
+     SEL_MASK : string := "MASK";
+     SEL_PATTERN : string := "DYNAMIC_PATTERN";
+     STATIC_PATTERN : bit_vector := X"000000000000";
+     WIDTH : integer := 48
+  );
+  port (
+     Q : out std_logic;
+     CE : in std_logic;
+     CLK : in std_logic;
+     DATA_IN : in std_logic_vector(WIDTH-1 downto 0);
+     DYNAMIC_PATTERN : in std_logic_vector(WIDTH-1 downto 0);
+     RST : in std_logic
+  );
+end component;
+
+----- component FIFO_DUALCLOCK_MACRO -----
+component FIFO_DUALCLOCK_MACRO
+  generic (
+     ALMOST_EMPTY_OFFSET : bit_vector := X"0080";
+     ALMOST_FULL_OFFSET : bit_vector := X"0080";
+     DATA_WIDTH : integer := 4;
+     DEVICE : string := "VIRTEX5";
+     FIFO_SIZE : string := "18Kb";
+     FIRST_WORD_FALL_THROUGH : boolean := FALSE;
+     INIT : bit_vector := X"000000000000000000";
+     SIM_MODE : string := "SAFE";
+     SRVAL : bit_vector := X"000000000000000000"
+  );
+  port (
+     ALMOSTEMPTY : out std_logic;
+     ALMOSTFULL : out std_logic;
+     DO : out std_logic_vector(DATA_WIDTH-1 downto 0);
+     EMPTY : out std_logic;
+     FULL : out std_logic;
+     RDCOUNT : out std_logic_vector (xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0);
+     RDERR : out std_logic;
+     WRCOUNT : out std_logic_vector (xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0);
+     WRERR : out std_logic;
+     DI : in std_logic_vector(DATA_WIDTH-1 downto 0);
+     RDCLK : in std_logic;
+     RDEN : in std_logic;
+     RST : in std_logic;
+     WRCLK : in std_logic;
+     WREN : in std_logic
+  );
+end component;
+
+----- component FIFO_SYNC_MACRO -----
+component FIFO_SYNC_MACRO
+  generic (
+     ALMOST_EMPTY_OFFSET : bit_vector := X"0080";
+     ALMOST_FULL_OFFSET : bit_vector := X"0080";
+     DATA_WIDTH : integer := 4;
+     DEVICE : string := "VIRTEX5";
+     DO_REG : integer := 0;
+     FIFO_SIZE : string := "18Kb";
+     INIT : bit_vector := X"000000000000000000";
+     SIM_MODE : string := "SAFE";
+     SRVAL : bit_vector := X"000000000000000000"
+  );
+  port (
+     ALMOSTEMPTY : out std_logic;
+     ALMOSTFULL : out std_logic;
+     DO : out std_logic_vector(DATA_WIDTH-1 downto 0);
+     EMPTY : out std_logic;
+     FULL : out std_logic;
+     RDCOUNT : out std_logic_vector (xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0);
+     RDERR : out std_logic;
+     WRCOUNT : out std_logic_vector (xil_UNM_GCW(DATA_WIDTH, FIFO_SIZE, DEVICE)-1 downto 0);
+     WRERR : out std_logic;
+     CLK : in std_logic;
+     DI : in std_logic_vector(DATA_WIDTH-1 downto 0);
+     RDEN : in std_logic;
+     RST : in std_logic;
+     WREN : in std_logic
+  );
+end component;
+
+----- component MACC_MACRO -----
+component MACC_MACRO
+  generic (
+     DEVICE : string := "VIRTEX5";
+     LATENCY : integer := 3;
+     WIDTH_A : integer := 25;
+     WIDTH_B : integer := 18;
+     WIDTH_P : integer := 48
+  );
+  port (
+     P : out std_logic_vector(WIDTH_P-1 downto 0);
+     A : in std_logic_vector(WIDTH_A-1 downto 0);
+     ADDSUB : in std_logic;
+     B : in std_logic_vector(WIDTH_B-1 downto 0);
+     CARRYIN : in std_logic;
+     CE : in std_logic;
+     CLK : in std_logic;
+     LOAD : in std_logic;
+     LOAD_DATA : in std_logic_vector(WIDTH_P-1 downto 0);
+     RST : in std_logic
+  );
+end component;
+
+----- component MULT_MACRO -----
+component MULT_MACRO
+  generic (
+     DEVICE : string := "VIRTEX5";
+     LATENCY : integer := 3;
+     STYLE : string := "DSP";
+     WIDTH_A : integer := 18;
+     WIDTH_B : integer := 18
+  );
+  port (
+     P : out std_logic_vector((WIDTH_A+WIDTH_B)-1 downto 0);
+     A : in std_logic_vector(WIDTH_A-1 downto 0);
+     B : in std_logic_vector(WIDTH_B-1 downto 0);
+     CE : in std_logic;
+     CLK : in std_logic;
+     RST : in std_logic
+  );
+end component;
+
+-- END COMPONENT
+
+end VCOMPONENTS;
+
+package body VCOMPONENTS is
+  
+  FUNCTION xil_UNM_GCW (
+    d_width : in integer;
+    fifo_size : in string;
+    device  : in string
+    ) return integer is
+    variable func_width : integer;
+  begin
+    if(device = "VIRTEX5" or device = "VIRTEX6" or device = "7SERIES") then
+      if(fifo_size = "18Kb") then
+        case d_width is
+          when 0|1|2|3|4 => func_width := 12;
+          when 5|6|7|8|9 => func_width := 11;
+          when 10 to 18 => func_width := 10;
+          when 19 to 36 => func_width := 9;
+          when others => func_width := 12;
+        end case;
+      elsif(fifo_size = "36Kb") then
+        case d_width is
+          when 0|1|2|3|4 => func_width := 13;
+          when 5|6|7|8|9 => func_width := 12;
+          when 10 to 18 => func_width := 11;
+          when 19 to 36 => func_width := 10;
+          when 37 to 72 => func_width := 9;
+          when others => func_width := 13;
+        end case;
+      end if;
+    else
+      func_width := 13;
+    end if;
+    return func_width;
+  end;
+
+end VCOMPONENTS;

resources/dide-lsp/static/vhdl_std_lib/unimacro/vhdl_analyze_order

@@ -0,0 +1,13 @@
+unimacro_VCOMP.vhd
+ADDMACC_MACRO.vhd
+ADDSUB_MACRO.vhd
+BRAM_SDP_MACRO.vhd
+BRAM_SINGLE_MACRO.vhd
+BRAM_TDP_MACRO.vhd
+COUNTER_LOAD_MACRO.vhd
+COUNTER_TC_MACRO.vhd
+EQ_COMPARE_MACRO.vhd
+FIFO_DUALCLOCK_MACRO.vhd
+FIFO_SYNC_MACRO.vhd
+MACC_MACRO.vhd
+MULT_MACRO.vhd

resources/dide-lsp/static/vhdl_std_lib/vhdl_ls.toml

@@ -0,0 +1,7 @@
+[libraries]
+
+std.files = ['std/*.vhd']
+std.is_third_party = true
+
+ieee.files = ['ieee_2008/*.vhdl', 'synopsys/*.vhd', 'vital2000/*.vhdl', 'unifast/primitive/*.vhd', 'unifast/secureip/*.vhd', 'unimacro/*.vhd']
+ieee.is_third_party = true