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89
.github/ISSUE_TEMPLATE/bug-report.cn.yaml vendored Normal file
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@ -0,0 +1,89 @@
name: 报告 Bug
description: 向我们报告 Bug。
title: "[Bug]: "
labels: ["bug"]
body:
- type: markdown
attributes:
value: |
投我以木桃，报之以琼瑶。
填写之前请阅读 [nc-ai | 关于反馈](https://nc-ai.cn/article/cxnqr517/#%E5%85%B3%E4%BA%8E%E5%8F%8D%E9%A6%88)
- type: dropdown
id: os
attributes:
label: 操作系统
description: 您在什么操作系统上运行？
options:
- Windows
- Mac
- Linux
- 其他
default: 0
validations:
required: true
- type: dropdown
id: chip
attributes:
label: 芯片架构
description: 您在什么架构的芯片上运行？
options:
- x86
- arm
- loongson
- 其他
default: 0
validations:
required: true
- type: dropdown
id: connect
attributes:
label: 运行方式
description: 您采用何种方式运行？
options:
- 桌面运行
- SSH 远程连接
- WSL2
- 虚拟机
- 其他
default: 0
validations:
required: true
- type: input
id: vscode-version
attributes:
label: Vscode / Vscodium 版本
placeholder: "1.96.2"
validations:
required: true
- type: input
id: dide-version
attributes:
label: Digital IDE 版本
placeholder: "0.4.0"
validations:
required: true
- type: textarea
id: meet-question
attributes:
label: 你遇到的问题
validations:
required: true
- type: textarea
id: expect
attributes:
label: 你希望的运行结果
validations:
required: false
- type: textarea
id: actual
attributes:
label: 实际的运行结果
validations:
required: false
- type: textarea
id: log
attributes:
label: 运行日志
render: shell
validations:
required: false

89
.github/ISSUE_TEMPLATE/bug-report.yaml vendored Normal file
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name: Bug Report
description: Report a bug to us.
title: "[Bug]: "
labels: ["bug"]
body:
- type: markdown
attributes:
value: |
"You give me a peach, I repay you with a jade."
Please read [nc-ai | About Feedback](https://nc-ai.cn/article/cxnqr517/#%E5%85%B3%E4%BA%8E%E5%8F%8D%E9%A6%88) before filling out this form.
- type: dropdown
id: os
attributes:
label: Operating System
description: What operating system are you running on?
options:
- Windows
- Mac
- Linux
- Other
default: 0
validations:
required: true
- type: dropdown
id: chip
attributes:
label: Chip Architecture
description: What chip architecture are you running on?
options:
- x86
- arm
- loongson
- Other
default: 0
validations:
required: true
- type: dropdown
id: connect
attributes:
label: Running Method
description: How are you running the software?
options:
- Desktop
- SSH Remote Connection
- WSL2
- Virtual Machine
- Other
default: 0
validations:
required: true
- type: input
id: vscode-version
attributes:
label: Vscode / Vscodium Version
placeholder: "1.96.2"
validations:
required: true
- type: input
id: dide-version
attributes:
label: Digital IDE Version
placeholder: "0.4.0"
validations:
required: true
- type: textarea
id: meet-question
attributes:
label: Issue You Encountered
validations:
required: true
- type: textarea
id: expect
attributes:
label: Expected Result
validations:
required: false
- type: textarea
id: actual
attributes:
label: Actual Result
validations:
required: false
- type: textarea
id: log
attributes:
label: Runtime Log
render: shell
validations:
required: false

7
.gitignore vendored
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@ -11,8 +11,13 @@ parser_stuck.v
out-js/
*.pyc
*.pyd
*.zip
resources/hdlParser/parser.js
resources/hdlParser/parser.wasm
resources/dide-viewer/view/*
resources/dide-lsp/server/*
resources/dide-lsp/static/*
resources/dide-lsp/static/*
resources/dide-netlist/static/*
resources/dide-netlist/view/*
scripts/update-icon.py
scripts/vscode-package.py

11
.vscode/settings.json vendored
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@ -1,17 +1,20 @@
// Place your settings in this file to overwrite default and user settings.
{
"files.exclude": {
"out": false // set this to true to hide the "out" folder with the compiled JS files
"out": false
},
"search.exclude": {
"out": true // set this to false to include "out" folder in search results
"out": true
},
// Turn off tsc task auto detection since we have the necessary tasks as npm scripts
"typescript.tsc.autoDetect": "off",
"i18n-haru.root": "l10n",
"i18n-haru.main": "zh-cn",
<<<<<<< HEAD
"i18n-haru.line-hint-max-length": 20,
"i18n-haru.custom-language-mapping": {
"en": "l10n/bundle.l10n.json"
}
=======
"i18n-haru.display": "zh-cn",
"i18n-haru.line-hint-max-length": 20
>>>>>>> 9fe382446ba6ff3efd72dae6924a0c493b950c52
}

8
.vscodeignore
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@ -2,6 +2,8 @@
.gitignore
**/.gitignore
.git
.github
doc
**/*.map
.eslintrc.json
dist
@ -13,8 +15,12 @@ script
resources/**/*.js
resources/**/*.d.ts
resources/**/*.wasm
resources/**/*.tar.gz
resources/dide-lsp/server
tsconfig.json
design
lib
*.vcd
*.vcd
*.zip
figures
scripts

13
CHANGELOG.md
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@ -4,17 +4,17 @@ All notable changes to the "digital-ide" extension will be documented in this fi
Check [Keep a Changelog](http://keepachangelog.com/) for recommendations on how to structure this file.
## [0.4.0]
- 新的 VCD 波形渲染器
- 新的 Netlist 渲染器
- 新的 LSP 后端
## [0.3.4] - 2024-08-28
Feature
wave 渲染器 https://nc-ai-lab.feishu.cn/wiki/K7gVwwU02iNMc8krIHucPwhqnff#share-NjuodrRQAoxEotxRicOc7BXDnOh
---
VCA wave 渲染器 https://nc-ai-lab.feishu.cn/wiki/K7gVwwU02iNMc8krIHucPwhqnff#share-NjuodrRQAoxEotxRicOc7BXDnOh
## [0.3.3] - 2024-02-05
@ -33,7 +33,6 @@ Bug 修复
- 点击 Refuse 会在用户工作区创建 json 文件
---
## [0.3.2] - 2023-11-01
Feature
@ -151,4 +150,4 @@ Bug 修复
## [0.0.1] - 2020-02-15
- Initial Release
- Initial Release

74
README.md
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@ -1,53 +1,53 @@
<center>
<div align="center">
<img src="./images/icon.png"/>
</center>
# Digital IDE - version 0.3.3
## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development
![](https://img.shields.io/badge/version-0.3.3-blue)
![](https://img.shields.io/badge/engine-wasm-blue)
[Document (New)](https://nc-ai.cn/en/) | [中文文档 (New)](https://nc-ai.cn/) | [Bilibili Video](https://www.bilibili.com/video/BV1L19HYcEz6/?spm_id_from=333.1387.list.card_archive.click) | [Github](https://github.com/Digital-EDA/Digital-IDE)
![](https://img.shields.io/badge/version-0.4.2-purple)
![](https://img.shields.io/badge/Verilog-support-green)
![](https://img.shields.io/badge/VHDL-support-green)
![](https://img.shields.io/badge/SystemVerilog-building-black)
![](https://img.shields.io/badge/SystemVerilog-support-green)
- [Document (New)](https://sterben.nitcloud.cn/)
- [中文文档 (New)](https://sterben.nitcloud.cn/zh/)
- [Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
</div>
## Features
---
**Rewritten Parser and Language Services in Rust**: Supports Verilog, VHDL, and SystemVerilog with faster performance and more stable services.
## Feature
- 增加对于 vhdl 的 全面支持（文件树、LSP等）
- 增加对 XDC，TCL 等脚本的 LSP 支持
- 增加 verilog, vhdl, xdc, tcl, vvp, vcd 等语言或生成文件的工作区图标
- 增加对于 vivado, modelsim, verilator 的支持，用户可以通过设置 `function.lsp.linter.vhdl.diagnostor`(设置 vhdl) 和 `function.lsp.linter.vlog.diagnostor`(设置 verilog) 来使用这些第三方工具的仿真和自动纠错。
- 增加对于 TCL, XDC, VVP 等脚本的 LSP 和 语法高亮 支持。
![](./figures/lsp.png)
## Change
- 将插件的工作状态显示在 vscode 下侧的状态栏上，利于用户了解目前的设置状态
- 状态栏右下角现在可以看到目前选择的linter以及是否正常工作了
- 优化项目配置目录
- 优化自动补全的性能
**Improved Documentation**: Provides more direct and faster access to basic information and dependencies of the current HDL file. Supports Wavedrom-style comments and renders them into visual diagrams.
## Bug 修复
- 修复文档化 input, output 处注释无法正常显示到文档的 bug
- 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug
- 修复 iverilog 仿真功能中，将 <code>`include</code> 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性）
- 修复其他已知 bug
![](./figures/doc.png)
---
**New VCD Renderer**: Added top toolbar, system beacon, and other components; supports drag-and-drop and grouping of selected signals in the left panel, as well as selecting multiple signals by holding Shift for addition and deletion; supports establishing a relative coordinate system based on system beacons; the top toolbar supports base conversion for displayed numbers of selected signals, rendering mode switching, and rendering signals as analog values.
## develop
![](./figures/vcd.png)
```bash
python script/command/make_package.py
<<<<<<< HEAD
```
- Brand New Netlist Renderer
## library更新
![](./figures/netlist.png)
library的更新不会随着Digital-IDE的git一起保存，是专门去拉取更新的，但是打包要一起打包进插件之中。
=======
```
>>>>>>> 199b7a8af3ea01baea4b20c89273a490dc0dc9d2
## New 0.4.2
- Added comprehensive support for VHDL & SV (file tree, LSP, etc.)
- Added workspace icons for languages or generated files such as Verilog, VHDL, XDC, TCL, VVP, VCD, etc.
- Added support for Vivado, ModelSim, and Verilator. Users can use these third-party tools for simulation and auto-correction by setting `function.lsp.linter.vhdl.diagnostor` (for VHDL) and `function.lsp.linter.vlog.diagnostor` (for Verilog).
- Added LSP and syntax highlighting support for scripts like TCL, XDC, and VVP.
## Changes
- Display the plugin's working status in the status bar at the bottom of VSCode, making it easier for users to understand the current settings.
- The bottom-right corner of the status bar now shows the currently selected linter and whether it is functioning properly.
- Optimized project configuration directory.
- Improved auto-completion performance.
## Bug Fixes
- Fixed a bug where comments on `input` and `output` were not displayed correctly in the documentation.
- Fixed a bug in the Icarus Verilog simulation feature where duplicate paths were included as compilation parameters.
- Fixed a bug in the Icarus Verilog simulation feature where adding or removing <code>include</code> would cause simulation compilation to fail (the `instModPathStatus` property of the instance was not updated).
- Fixed simulation issues with Icarus Verilog version 12
- Fixed the issue of being unable to import Block Design (BD) during Vivado project generation
- Fixed the issue where libraries in custom mode could not be imported into Vivado
- Fixed other known bugs.

16
config/ignore.configuration.json Normal file
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@ -0,0 +1,16 @@
{
"comments": {
"lineComment": "#"
},
"brackets": [
["{", "}"],
["[", "]"],
["(", ")"]
],
"autoClosingPairs": [
{"open":"(", "close":")", "notIn":["string", "comment"]},
{"open":"[", "close":"]", "notIn":["string", "comment"]},
{"open":"{", "close":"}", "notIn":["string", "comment"]},
{"open":"\"", "close":"\"", "notIn":["string", "comment"]}
]
}

16
config/ys.configuration.json Normal file
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@ -0,0 +1,16 @@
{
"comments": {
"lineComment": "#"
},
"brackets": [
["{", "}"],
["[", "]"],
["(", ")"]
],
"autoClosingPairs": [
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{"open":"[", "close":"]", "notIn":["string", "comment"]},
{"open":"{", "close":"}", "notIn":["string", "comment"]},
{"open":"\"", "close":"\"", "notIn":["string", "comment"]}
]
}

120
design/lsp.drawio
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@ -1,120 +0,0 @@
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l10n/bundle.l10n.de.json
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@ -61,5 +61,79 @@
"info.dide-doc.source.cannot-find": "Nicht gefunden",
"info.command.instantiation.pick-title": "Select a Module",
"warn.command.clean.prjPath-is-workspace": "arch.prjPath is the same as the workspace path, the clean will delete the project, please check your arch.prjPath!",
<<<<<<< HEAD
"info.launch.launch-digital-lsp": "启动 Digital LSP 语言服务器"
=======
"info.monitor.ppy.impl-change-to-project": "Änderungen werden auf das {0}-Projekt angewendet",
"info.initialise.report.title": "Analyse von {0} HDL-Dateien abgeschlossen, {1} ungelöste Instanzmodule gefunden",
"info.launch.following-folder-tracked": "Die Dateien im folgenden Ordner werden kontinuierlich analysiert und vollständige LSP-Dienste bereitgestellt.",
"info.launch.search-and-parse": "Suche und analysiere HDL-Dateien aus dem untenstehenden Pfad",
"info.launch.digital-ide-current-version": "Digital-IDE wurde gestartet, aktuelle Version:",
"info.pl.xilinx.update-addfiles": "Datei zu Xilinx-Projekt hinzufügen",
"info.pl.xilinx.update-delfiles": "Löschen Sie die folgenden Dateien aus dem Xilinx-Projekt.",
"info.pl.xilinx.no-need-add-files": "Keine Dateien zum Hinzufügen zum Xilinx-Projekt",
"info.pl.xilinx.no-need-del-files": "Es müssen keine Dateien aus Xilinx gelöscht werden.",
"error.pl.launch.not-valid-vivado-path": "Fehler beim Starten des Vivado TCL-Skriptinterpreters: {0}. Bitte überprüfen Sie, ob der Startpfad für Vivado korrekt ist. Derzeit eingestellter Startordnerpfad für Vivado: {1}",
"info.pl.launch.set-vivado-path": "Zur Einstellung des Vivado-Installationspfads gehen",
"info.monitor.current-mode": "Aktueller Monitor-Modus: {0}",
"info.simulation.create-vvp": "VVP-Datei in {0} erstellen",
"error.simulation.reason": "Grund: {0}",
"info.simulate.vvp.vcd-generate": "vcd-Datei wurde erstellt in {0}",
"error.simluate.icarus.use-primitives": "Es wurde ein Primitiv {0} erkannt, aber Icarus iverilog unterstützt keine Primitiven.",
"error.simluate.icarus.use-ip": "Es wurde die IP {0} verwendet, aber Icarus iverilog unterstützt keine IP.",
"error.simulation.error-happen-run-command": "Fehler bei der Icarus-Simulation:",
"info.command.structure.transform-xilinx-to-standard": "Konvertiere Xilinx-Projektstruktur in Digital IDE-Standardstruktur",
"error.command.structure.not-valid-xilinx-project": "Das aktuelle Projekt ist kein gültiges Xilinx-Projekt, die Konvertierung ist fehlgeschlagen!",
"info.common.codedoc": "Code-Dokumentation",
"info.linter.pick-for-verilog": "Wählen Sie einen Diagnostiker für Verilog-Code aus",
"info.command.loading": "Wird geladen",
"info.linter.pick-for-system-verilog": "Wählen Sie einen Diagnostiker für System Verilog-Code",
"info.linter.pick-for-vhdl": "Wählen Sie einen Diagnostiker für VHDL-Code aus",
"info.linter.vivado.xvlog-name": "Vivado-Diagnosetools",
"info.common.some-is-ready": "{0} ist bereit",
"info.common.not-available": "{0} ist derzeit nicht verfügbar",
"info.common.linter-name": "Diagnosetools",
"info.linter.finish-init": "Initialisierung des Diagnosewerkzeugs {0} abgeschlossen, aktueller Name des Diagnosewerkzeugs {1}",
"error.linter.status-bar.tooltip": "Kann Diagnose für {0} nicht abrufen",
"info.linter.status-bar.tooltip": "Diagnosegerät {0} arbeitet",
"warning.linter.cannot-get-valid-linter-invoker": "Die digitale IDE kann keinen Aufrufpfad für {0} abrufen. Bitte installieren Sie den entsprechenden Diagnose-Tool und konfigurieren Sie ihn entweder in der Umgebungsvariablen PATH oder im digitalen IDE-Diagnosetool-Installationspfad.",
"info.linter.config-linter-install-path": "Installationsverzeichnis konfigurieren",
"info.progress.doing-diagnostic": "Diagnostizierung",
"error.common.fail-to-launch-lsp": "Start des Sprachservers fehlgeschlagen!",
"info.netlist.launch-netlist": "Netlist wird gestartet",
"info.netlist.not-found-payload": "Die Lastressource des Netlists konnte nicht gefunden werden. Bitte überprüfen Sie, ob das Installationsverzeichnis beschädigt ist!",
"info.netlist.not-support-vhdl": "Das aktuelle Netlist unterstützt vorübergehend kein VHDL und andere Sprachen!",
"info.netlist.generate-network": "Netzwerktopologie wird generiert",
"error.cannot-gen-netlist": "Netlist-Datei konnte nicht generiert werden!",
"info.common.confirm": "Bestätigen",
"info.command.structure.reload-vscode": "Vscode neu starten",
"error.look-up-log": "Fehlerprotokoll anzeigen",
"netlist.save-as-svg": "Als SVG speichern",
"svg-file": "SVG-Datei",
"toolbar.save-as-svg": "Aktuelle Ansicht als SVG speichern",
"toolbar.save-as-pdf": "Aktuelle Ansicht als PDF speichern",
"pdf-file": "PDF-Datei",
"export-pdf": "PDF wird exportiert",
"info.process-killed": "Prozess {0} wurde zerstört",
"info.addDevice.placeholder": "Bitte geben Sie den Namen des Geräts ein",
"warning.addDevice.name-taken": "Der Name des Geräts {0} ist bereits vergeben",
"info.addDevice.add-success": "Gerät {0} wurde erfolgreich hinzugefügt",
"info.delDevice.placeholder": "Wählen Sie das zu löschende Gerät aus",
"info.delDevice.del-success": "Gerät {0} wurde erfolgreich gelöscht",
"info.progress.launch-lsp": "Starten Sie den Digital LSP-Sprachserver",
"info.choose.digital-lsp-targz": "Wählen Sie das Digital LSP-Archiv aus",
"info.digital-lsp.targz": "Digitales LSP-Paket",
"error.digital-lsp.incorrect-filename": "Die von Ihnen bereitgestellte Digital-LSP-Archivdatei {0} entspricht nicht der aktuellen Systemarchitektur. Bitte laden Sie die Archivdatei mit dem Namen {1} herunter!",
"error.not-valid-browser": "{0} ist kein gültiger Browser-Pfad!",
"info.config-browser-path": "Browser-Pfad konfigurieren",
"info.pdf.exporting": "PDF wird nach {0} exportiert",
"info.generate-pdf-to": "PDF wurde unter {0} generiert",
"info.vivado-gui.started": "Vivado GUI wird gestartet, bitte warten Sie einen Moment",
"ok": "Gut",
"netlist.save-as-markdown": "Als Markdown speichern",
"markdown-file": "Markdown-Datei",
"toolbar.save-as-html": "Als HTML speichern",
"html-file": "HTML-Datei",
"dide-doc.error.loading-html": "Digital CodeDoc-Ressourcen konnten nicht geladen werden, das Installationsverzeichnis ist beschädigt. Bitte installieren Sie das Programm neu!"
>>>>>>> 9fe382446ba6ff3efd72dae6924a0c493b950c52
}

74
l10n/bundle.l10n.ja.json
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@ -61,5 +61,79 @@
"info.dide-doc.source.cannot-find": "見つかりません",
"info.command.instantiation.pick-title": "Select a Module",
"warn.command.clean.prjPath-is-workspace": "arch.prjPath is the same as the workspace path, the clean will delete the project, please check your arch.prjPath!",
<<<<<<< HEAD
"info.launch.launch-digital-lsp": "启动 Digital LSP 语言服务器"
=======
"info.monitor.ppy.impl-change-to-project": "{0} プロジェクトに変更を適用しています",
"info.initialise.report.title": "{0} 個のHDLファイルの解析が完了し、{1} 個の未解決のインスタンスモジュールが見つかりました",
"info.launch.following-folder-tracked": "以下のフォルダ内のファイルは継続的に解析され、完全なLSPサービスが提供されます。",
"info.launch.search-and-parse": "以下のパスからHDLファイルを検索して解析します",
"info.launch.digital-ide-current-version": "Digital-IDEが起動しました、現在のバージョン：",
"info.pl.xilinx.update-addfiles": "ファイルを Xilinx プロジェクトに追加",
"info.pl.xilinx.update-delfiles": "以下のファイルをXilinxプロジェクトから削除してください。",
"info.pl.xilinx.no-need-add-files": "Xilinx プロジェクトに追加するファイルはありません",
"info.pl.xilinx.no-need-del-files": "Xilinx から削除するファイルはありません。",
"error.pl.launch.not-valid-vivado-path": "Vivado TCL スクリプトインタプリタの起動中にエラーが発生しました：{0}。Vivado の起動パスが正しいか確認してください。現在設定されている Vivado 起動フォルダパス：{1}",
"info.pl.launch.set-vivado-path": "Vivado インストールパスの設定に移動",
"info.monitor.current-mode": "現在のモニターモード：{0}",
"info.simulation.create-vvp": "{0} で VVP ファイルを作成",
"error.simulation.reason": "理由: {0}",
"info.simulate.vvp.vcd-generate": "vcdファイルが生成されました: {0}",
"error.simluate.icarus.use-primitives": "プリミティブ {0} が検出されましたが、Icarus iverilog はプリミティブをサポートしていません。",
"error.simluate.icarus.use-ip": "IP {0} が使用されていますが、Icarus iverilog は IP をサポートしていません。",
"error.simulation.error-happen-run-command": "Icarusシミュレーション中にエラーが発生しました：",
"info.command.structure.transform-xilinx-to-standard": "Xilinx プロジェクト構造を Digital IDE 標準構造に変換しています",
"error.command.structure.not-valid-xilinx-project": "現在のプロジェクトは有効なXilinxプロジェクトではありません、変換に失敗しました！",
"info.common.codedoc": "コードドキュメント",
"info.linter.pick-for-verilog": "Verilogコードの診断機能を選択してください",
"info.command.loading": "読み込み中",
"info.linter.pick-for-system-verilog": "System Verilog コードの診断機能を選択",
"info.linter.pick-for-vhdl": "VHDLコードの診断機能を選択してください",
"info.linter.vivado.xvlog-name": "Vivado診断ツール",
"info.common.some-is-ready": "{0} は準備ができています",
"info.common.not-available": "{0} は現在使用できません",
"info.common.linter-name": "診断ツール",
"info.linter.finish-init": "{0} 診断ツールの初期化が完了しました。現在の診断ツールの名前は {1} です",
"error.linter.status-bar.tooltip": "{0} 診断機能を取得できません",
"info.linter.status-bar.tooltip": "診断ツール {0} が作動中",
"warning.linter.cannot-get-valid-linter-invoker": "デジタルIDEは{0}の呼び出しパスを取得できません。対応する診断ツールをインストールし、環境変数PATHに設定するか、デジタルIDEの診断ツールインストールパスを設定してください。",
"info.linter.config-linter-install-path": "インストールディレクトリを設定",
"info.progress.doing-diagnostic": "診断中",
"error.common.fail-to-launch-lsp": "言語サーバーの起動に失敗しました！",
"info.netlist.launch-netlist": "Netlistを起動中",
"info.netlist.not-found-payload": "ネットリストのロードリソースが見つかりません。インストールディレクトリが破損していないか確認してください！",
"info.netlist.not-support-vhdl": "現在のネットリストは一時的にVHDLやその他の言語をサポートしていません！",
"info.netlist.generate-network": "ネットワークトポロジを生成中",
"error.cannot-gen-netlist": "ネットリストファイルを生成できません！",
"info.common.confirm": "確認",
"info.command.structure.reload-vscode": "Vscodeを再起動",
"error.look-up-log": "エラーログを表示",
"netlist.save-as-svg": "SVGとして保存",
"svg-file": "SVGファイル",
"toolbar.save-as-svg": "現在のビューをSVGとして保存",
"toolbar.save-as-pdf": "現在のビューをPDFとして保存",
"pdf-file": "PDFファイル",
"export-pdf": "PDFをエクスポート中",
"info.process-killed": "プロセス {0} は破棄されました",
"info.addDevice.placeholder": "デバイスの名前を入力してください",
"warning.addDevice.name-taken": "デバイス {0} の名前は既に使用されています",
"info.addDevice.add-success": "デバイス {0} が正常に追加されました",
"info.delDevice.placeholder": "削除するデバイスを選択してください",
"info.delDevice.del-success": "デバイス {0} は正常に削除されました",
"info.progress.launch-lsp": "Digital LSP 言語サーバーを起動する",
"info.choose.digital-lsp-targz": "Digital LSPのアーカイブを選択してください",
"info.digital-lsp.targz": "デジタルLSPパッケージ",
"error.digital-lsp.incorrect-filename": "提供されたデジタルLSPアーカイブファイル{0}は、現在のシステムアーキテクチャに適合していません。{1}という名前のアーカイブファイルをダウンロードしてください！",
"error.not-valid-browser": "{0} は有効なブラウザのパスではありません！",
"info.config-browser-path": "ブラウザのパスを設定",
"info.pdf.exporting": "PDFを{0}にエクスポート中",
"info.generate-pdf-to": "PDFは{0}に生成されました",
"info.vivado-gui.started": "Vivado GUI を起動しています、少々お待ちください",
"ok": "良い",
"netlist.save-as-markdown": "Markdownとして保存",
"markdown-file": "Markdownファイル",
"toolbar.save-as-html": "HTMLとして保存",
"html-file": "HTMLファイル",
"dide-doc.error.loading-html": "Digital CodeDoc リソースの読み込みに失敗しました。インストールディレクトリが破損しています。再インストールしてください！"
>>>>>>> 9fe382446ba6ff3efd72dae6924a0c493b950c52
}

74
l10n/bundle.l10n.json
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@ -61,5 +61,79 @@
"info.dide-doc.source.cannot-find": "Cannot find",
"info.command.instantiation.pick-title": "Select a Module",
"warn.command.clean.prjPath-is-workspace": "arch.prjPath is the same as the workspace path, the clean will delete the project, please check your arch.prjPath!",
<<<<<<< HEAD:l10n/bundle.l10n.json
"info.launch.launch-digital-lsp": "启动 Digital LSP 语言服务器"
=======
"info.monitor.ppy.impl-change-to-project": "Applying changes to the {0} project",
"info.initialise.report.title": "Completed parsing {0} HDL files, found {1} unresolved instantiation modules",
"info.launch.following-folder-tracked": "The files in the folder below will be continuously parsed and full LSP services will be provided.",
"info.launch.search-and-parse": "Search and parse HDL files from the path below",
"info.launch.digital-ide-current-version": "Digital-IDE has been launched, current version:",
"info.pl.xilinx.update-addfiles": "Add file to Xilinx project",
"info.pl.xilinx.update-delfiles": "Delete the following files from the Xilinx project.",
"info.pl.xilinx.no-need-add-files": "No files need to be added to the Xilinx project",
"info.pl.xilinx.no-need-del-files": "There are no files to be deleted from Xilinx.",
"error.pl.launch.not-valid-vivado-path": "Error encountered while starting the Vivado TCL script interpreter: {0}. Please check if your Vivado startup path is correct. Currently set Vivado startup folder path: {1}",
"info.pl.launch.set-vivado-path": "Go to set the Vivado installation path",
"info.monitor.current-mode": "Current monitor mode: {0}",
"info.simulation.create-vvp": "Create VVP file in {0}",
"error.simulation.reason": "Reason: {0}",
"info.simulate.vvp.vcd-generate": "vcd file has been generated to {0}",
"error.simluate.icarus.use-primitives": "Primitive {0} detected, but Icarus iverilog does not support primitives.",
"error.simluate.icarus.use-ip": "Detected the use of IP {0}, but Icarus iverilog does not support IP.",
"error.simulation.error-happen-run-command": "Error during Icarus simulation:",
"info.command.structure.transform-xilinx-to-standard": "Converting Xilinx project structure to Digital IDE standard structure",
"error.command.structure.not-valid-xilinx-project": "The current project is not a valid Xilinx project, the conversion failed!",
"info.common.codedoc": "Code Documentation",
"info.linter.pick-for-verilog": "Select a diagnostician for Verilog code",
"info.command.loading": "Loading",
"info.linter.pick-for-system-verilog": "Select a diagnostician for System Verilog code",
"info.linter.pick-for-vhdl": "Select a diagnostician for VHDL code",
"info.linter.vivado.xvlog-name": "Vivado diagnostic tools",
"info.common.some-is-ready": "{0} is ready",
"info.common.not-available": "{0} is currently unavailable",
"info.common.linter-name": "Diagnostic tools",
"info.linter.finish-init": "Completed initialization of the {0} diagnostic tool, current name of the diagnostic tool {1}",
"error.linter.status-bar.tooltip": "Unable to get {0} diagnoser",
"info.linter.status-bar.tooltip": "Diagnostics {0} is working",
"warning.linter.cannot-get-valid-linter-invoker": "The Digital IDE cannot retrieve the call path for {0}. Please install the corresponding diagnostic tool and configure it either in the environment variable PATH or in the Digital IDE's diagnostic tool installation path.",
"info.linter.config-linter-install-path": "Configure installation directory",
"info.progress.doing-diagnostic": "Diagnosing",
"error.common.fail-to-launch-lsp": "Language server startup failed!",
"info.netlist.launch-netlist": "Starting Netlist",
"info.netlist.not-found-payload": "Unable to find the load resource of the netlist, please check if the installation directory is corrupted!",
"info.netlist.not-support-vhdl": "The current netlist temporarily does not support VHDL and other languages!",
"info.netlist.generate-network": "Generating network topology",
"error.cannot-gen-netlist": "Unable to generate Netlist file!",
"info.common.confirm": "Confirm",
"info.command.structure.reload-vscode": "Restart Vscode",
"error.look-up-log": "View error log",
"netlist.save-as-svg": "Save as SVG",
"svg-file": "SVG file",
"toolbar.save-as-svg": "Save current view as SVG",
"toolbar.save-as-pdf": "Save current view as PDF",
"pdf-file": "PDF file",
"export-pdf": "Exporting PDF",
"info.process-killed": "Process {0} has been destroyed",
"info.addDevice.placeholder": "Please enter the name of the device",
"warning.addDevice.name-taken": "The name of device {0} is already taken",
"info.addDevice.add-success": "Device {0} has been successfully added",
"info.delDevice.placeholder": "Select the device to delete",
"info.delDevice.del-success": "Device {0} has been successfully deleted",
"info.progress.launch-lsp": "Start the Digital LSP language server",
"info.choose.digital-lsp-targz": "Select the Digital LSP archive",
"info.digital-lsp.targz": "Digital LSP Package",
"error.digital-lsp.incorrect-filename": "The digital LSP archive file {0} you provided does not match the current system architecture. Please download the archive file named {1}!",
"error.not-valid-browser": "{0} is not a valid browser path!",
"info.config-browser-path": "Configure browser path",
"info.pdf.exporting": "Exporting PDF to {0}",
"info.generate-pdf-to": "PDF has been generated to {0}",
"info.vivado-gui.started": "Vivado GUI is starting, please wait a moment",
"ok": "Good",
"netlist.save-as-markdown": "Save as Markdown",
"markdown-file": "Markdown file",
"toolbar.save-as-html": "Save as HTML",
"html-file": "HTML file",
"dide-doc.error.loading-html": "Digital CodeDoc resource loading failed, the installation directory is corrupted, please reinstall!"
>>>>>>> 9fe382446ba6ff3efd72dae6924a0c493b950c52:l10n/bundle.l10n.en.json
}

74
l10n/bundle.l10n.zh-cn.json
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@ -61,5 +61,79 @@
"info.dide-doc.source.cannot-find": "无法找到",
"info.command.instantiation.pick-title": "选择一个模块",
"warn.command.clean.prjPath-is-workspace": "arch.prjPath 和当前的工作区目录相同， clean 功能可能会删除整个项目，请检查你的 arch.prjPath ！",
<<<<<<< HEAD
"info.launch.launch-digital-lsp": "启动 Digital LSP 语言服务器"
=======
"info.monitor.ppy.impl-change-to-project": "正在将修改应用于 {0} 项目中",
"info.initialise.report.title": "完成 {0} 个 HDL 文件的解析，发现 {1} 个未解决的例化模块",
"info.launch.following-folder-tracked": "下方文件夹中的文件将被持续解析并提供完整的 LSP 服务",
"info.launch.search-and-parse": "从下方路径中搜索并解析 HDL 文件",
"info.launch.digital-ide-current-version": "Digital-IDE 已经启动，当前版本：",
"info.pl.xilinx.update-addfiles": "添加文件到 Xilinx 工程",
"info.pl.xilinx.update-delfiles": "将下方文件从 Xilinx 工程中删除",
"info.pl.xilinx.no-need-add-files": "没有需要添加到 Xilinx 工程的文件",
"info.pl.xilinx.no-need-del-files": "没有需要从 Xilinx 中删除的文件",
"error.pl.launch.not-valid-vivado-path": "启动 Vivado TCL 脚本解释器遇到错误：{0} 。请检查你的 Vivado 启动路径是否正确，当前设置的 Vivado 启动文件夹路径：{1}",
"info.pl.launch.set-vivado-path": "前往设置 Vivado 安装路径",
"info.monitor.current-mode": "当前监视器模式：{0}",
"info.simulation.create-vvp": "在 {0} 创建 VVP 文件",
"error.simulation.reason": "原因: {0}",
"info.simulate.vvp.vcd-generate": "vcd 文件已经生成至 {0}",
"error.simluate.icarus.use-primitives": "检测到使用了原语 {0}，但是 Icarus iverilog 并不支持原语",
"error.simluate.icarus.use-ip": "检测到使用了 IP {0}，但是 Icarus iverilog 并不支持 IP",
"error.simulation.error-happen-run-command": "Icarus 仿真时，出现错误：",
"info.command.structure.transform-xilinx-to-standard": "正在将 Xilinx 项目结构转变为 Digital IDE 标准结构",
"error.command.structure.not-valid-xilinx-project": "当前项目不是一个有效的 Xilinx 项目，转换失败！",
"info.common.codedoc": "代码文档",
"info.linter.pick-for-verilog": "为 Verilog 代码选择一个诊断器",
"info.command.loading": "加载中",
"info.linter.pick-for-system-verilog": "为 System Verilog 代码选择一个诊断器",
"info.linter.pick-for-vhdl": "为 VHDL 代码选择一个诊断器",
"info.linter.vivado.xvlog-name": "vivado 诊断工具",
"info.common.some-is-ready": "{0} 已经准备就绪",
"info.common.not-available": "{0} 目前不可用",
"info.common.linter-name": "诊断工具",
"info.linter.finish-init": "完成 {0} 诊断器的初始化，当前诊断器的名字 {1}",
"error.linter.status-bar.tooltip": "无法获取 {0} 诊断器",
"info.linter.status-bar.tooltip": "诊断器 {0} 正在工作",
"warning.linter.cannot-get-valid-linter-invoker": "Digital IDE 无法获取到关于 {0} 的调用路径，请安装对应诊断器后，配置到环境变量 PATH 或者配置 Digital IDE 对应的诊断工具安装路径",
"info.linter.config-linter-install-path": "配置安装目录",
"info.progress.doing-diagnostic": "诊断中",
"error.common.fail-to-launch-lsp": "语言服务器启动失败！",
"info.netlist.launch-netlist": "正在启动 Netlist",
"info.netlist.not-found-payload": "无法找到 netlist 的负载资源，请检查安装目录是否损坏！",
"info.netlist.not-support-vhdl": "当前 netlist 暂时不支持 VHDL 和其他语言！",
"info.netlist.generate-network": "正在生成网络拓扑",
"error.cannot-gen-netlist": "无法生成 Netlist 文件！",
"info.common.confirm": "确认",
"info.command.structure.reload-vscode": "重启 Vscode",
"error.look-up-log": "查看错误日志",
"netlist.save-as-svg": "保存为 Svg",
"svg-file": "svg 文件",
"toolbar.save-as-svg": "将当前视图保存为 svg",
"toolbar.save-as-pdf": "将当前视图保存为 pdf",
"pdf-file": "pdf 文件",
"export-pdf": "正在导出 pdf",
"info.process-killed": "进程 {0} 已经被销毁",
"info.addDevice.placeholder": "请输入 device 的名字",
"warning.addDevice.name-taken": "device {0} 的名字已经被占用",
"info.addDevice.add-success": "device {0} 已被成功添加",
"info.delDevice.placeholder": "选择需要删除的 device",
"info.delDevice.del-success": "device {0} 已被成功删除",
"info.progress.launch-lsp": "启动 Digital LSP 语言服务器",
"info.choose.digital-lsp-targz": "选择 Digital LSP 的压缩包",
"info.digital-lsp.targz": "Digital LSP 压缩包",
"error.digital-lsp.incorrect-filename": "您提供的 digital lsp 压缩包文件 {0} 并不是一个符合当前系统架构的，请下载名为 {1} 的压缩包文件！",
"error.not-valid-browser": "{0} 并不是一个有效的浏览器路径！",
"info.config-browser-path": "配置浏览器路径",
"info.pdf.exporting": "正在导出 pdf 到 {0}",
"info.generate-pdf-to": "pdf 已经生成至 {0}",
"info.vivado-gui.started": "Vivado GUI 正在启动中，稍等片刻",
"ok": "好的",
"netlist.save-as-markdown": "保存为 Markdown",
"markdown-file": "Markdown 文件",
"toolbar.save-as-html": "保存为 HTML",
"html-file": "HTML 文件",
"dide-doc.error.loading-html": "Digital CodeDoc 资源加载失败，安装目录已经损坏，请重新安装！"
>>>>>>> 9fe382446ba6ff3efd72dae6924a0c493b950c52
}

74
l10n/bundle.l10n.zh-tw.json
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@ -61,5 +61,79 @@
"info.dide-doc.source.cannot-find": "無法找到",
"info.command.instantiation.pick-title": "Select a Module",
"warn.command.clean.prjPath-is-workspace": "arch.prjPath is the same as the workspace path, the clean will delete the project, please check your arch.prjPath!",
<<<<<<< HEAD
"info.launch.launch-digital-lsp": "启动 Digital LSP 语言服务器"
=======
"info.monitor.ppy.impl-change-to-project": "正在將修改應用於 {0} 專案中",
"info.initialise.report.title": "完成 {0} 個 HDL 檔案的解析，發現 {1} 個未解決的例化模組",
"info.launch.following-folder-tracked": "下方資料夾中的檔案將被持續解析並提供完整的LSP服務。",
"info.launch.search-and-parse": "從下方路徑中搜尋並解析 HDL 檔案",
"info.launch.digital-ide-current-version": "Digital-IDE 已啟動，目前版本：",
"info.pl.xilinx.update-addfiles": "將檔案新增到 Xilinx 專案",
"info.pl.xilinx.update-delfiles": "從 Xilinx 專案中刪除以下檔案。",
"info.pl.xilinx.no-need-add-files": "沒有需要添加到 Xilinx 工程的文件",
"info.pl.xilinx.no-need-del-files": "沒有需要從 Xilinx 中刪除的檔案。",
"error.pl.launch.not-valid-vivado-path": "啟動 Vivado TCL 腳本解釋器遇到錯誤：{0} 。請檢查你的 Vivado 啟動路徑是否正確，目前設定的 Vivado 啟動資料夾路徑：{1}",
"info.pl.launch.set-vivado-path": "前往設定 Vivado 安裝路徑",
"info.monitor.current-mode": "目前監視器模式：{0}",
"info.simulation.create-vvp": "在 {0} 建立 VVP 檔案",
"error.simulation.reason": "原因: {0}",
"info.simulate.vvp.vcd-generate": "vcd 檔案已生成至 {0}",
"error.simluate.icarus.use-primitives": "偵測到使用了原語 {0}，但是 Icarus iverilog 並不支援原語。",
"error.simluate.icarus.use-ip": "偵測到使用了 IP {0}，但是 Icarus iverilog 並不支援 IP。",
"error.simulation.error-happen-run-command": "Icarus 模擬時，出現錯誤：",
"info.command.structure.transform-xilinx-to-standard": "正在將 Xilinx 專案結構轉變為 Digital IDE 標準結構",
"error.command.structure.not-valid-xilinx-project": "當前專案不是一個有效的 Xilinx 專案，轉換失敗！",
"info.common.codedoc": "程式碼文件",
"info.linter.pick-for-verilog": "為 Verilog 程式碼選擇一個診斷器",
"info.command.loading": "載入中",
"info.linter.pick-for-system-verilog": "為 System Verilog 程式碼選擇一個診斷器",
"info.linter.pick-for-vhdl": "為VHDL代碼選擇一個診斷器",
"info.linter.vivado.xvlog-name": "Vivado診斷工具",
"info.common.some-is-ready": "{0} 已經準備就緒",
"info.common.not-available": "{0} 目前無法使用",
"info.common.linter-name": "診斷工具",
"info.linter.finish-init": "完成 {0} 診斷器的初始化，當前診斷器的名字 {1}",
"error.linter.status-bar.tooltip": "無法取得 {0} 診斷器",
"info.linter.status-bar.tooltip": "診斷器 {0} 正在運作",
"warning.linter.cannot-get-valid-linter-invoker": "Digital IDE 無法取得關於 {0} 的呼叫路徑，請安裝對應診斷器後，配置到環境變數 PATH 或者配置 Digital IDE 對應的診斷工具安裝路徑。",
"info.linter.config-linter-install-path": "配置安裝目錄",
"info.progress.doing-diagnostic": "診斷中",
"error.common.fail-to-launch-lsp": "語言伺服器啟動失敗！",
"info.netlist.launch-netlist": "正在啟動Netlist",
"info.netlist.not-found-payload": "無法找到 netlist 的負載資源，請檢查安裝目錄是否損壞！",
"info.netlist.not-support-vhdl": "當前 netlist 暫時不支援 VHDL 和其他語言！",
"info.netlist.generate-network": "正在生成網路拓撲",
"error.cannot-gen-netlist": "無法生成Netlist檔案！",
"info.common.confirm": "確認",
"info.command.structure.reload-vscode": "重啟 Vscode",
"error.look-up-log": "查看錯誤日誌",
"netlist.save-as-svg": "保存為Svg",
"svg-file": "SVG 檔案",
"toolbar.save-as-svg": "將目前視圖儲存為SVG",
"toolbar.save-as-pdf": "將目前視圖儲存為PDF",
"pdf-file": "PDF檔案",
"export-pdf": "正在匯出PDF",
"info.process-killed": "進程 {0} 已經被銷毀",
"info.addDevice.placeholder": "請輸入設備的名稱",
"warning.addDevice.name-taken": "設備 {0} 的名字已經被佔用",
"info.addDevice.add-success": "設備 {0} 已成功添加",
"info.delDevice.placeholder": "選擇需要刪除的設備",
"info.delDevice.del-success": "設備 {0} 已被成功刪除",
"info.progress.launch-lsp": "啟動 Digital LSP 語言伺服器",
"info.choose.digital-lsp-targz": "選擇 Digital LSP 的壓縮包",
"info.digital-lsp.targz": "數位LSP壓縮包",
"error.digital-lsp.incorrect-filename": "您提供的 digital lsp 壓縮包文件 {0} 並不是一個符合當前系統架構的，請下載名為 {1} 的壓縮包文件！",
"error.not-valid-browser": "{0} 並不是一個有效的瀏覽器路徑！",
"info.config-browser-path": "配置瀏覽器路徑",
"info.pdf.exporting": "正在導出PDF到{0}",
"info.generate-pdf-to": "PDF 已生成至 {0}",
"info.vivado-gui.started": "Vivado GUI 正在啟動中，稍等片刻",
"ok": "好的",
"netlist.save-as-markdown": "儲存為 Markdown",
"markdown-file": "Markdown 檔案",
"toolbar.save-as-html": "保存為HTML",
"html-file": "HTML檔案",
"dide-doc.error.loading-html": "Digital CodeDoc 資源加載失敗，安裝目錄已經損壞，請重新安裝！"
>>>>>>> 9fe382446ba6ff3efd72dae6924a0c493b950c52
}

3540
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339
package.json
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@ -4,12 +4,12 @@
"description": "all in one vscode plugin for Verilog/VHDL development",
"publisher": "sterben",
"homepage": "https://digital-eda.github.io/DIDE-doc-Cn",
"version": "0.4.0",
"version": "0.4.3",
"main": "./out/extension",
"l10n": "./l10n",
"icon": "images/icon.png",
"engines": {
"vscode": "^1.95.0"
"vscode": "^1.85.0"
},
"keywords": [
"FPGA Develop Support",
@ -65,11 +65,26 @@
"default": "C:/Xilinx/Vivado/2018.3/bin",
"description": "%digital-ide.prj.vivado.install.path.title%"
},
"digital-ide.prj.efinix.install.path": {
"type": "string",
"default": "C:/Efinity/2023.2/bin",
"description": "%digital-ide.prj.efinix.install.path.title%"
},
"digital-ide.prj.modelsim.install.path": {
"type": "string",
"default": "C:/modeltech64_10.4/win64",
"description": "%digital-ide.prj.modelsim.install.path.title%"
},
"digital-ide.prj.verible.install.path": {
"type": "string",
"default": "",
"description": "%digital-ide.prj.verible.install.path.title%"
},
"digital-ide.prj.verilator.install.path": {
"type": "string",
"default": "",
"description": "%digital-ide.prj.verilator.install.path.title%"
},
"digital-ide.prj.xilinx.IP.repo.path": {
"type": "string",
"default": "",
@ -150,9 +165,9 @@
"default": "<div style=\"font-size: 9px; margin-left: 1cm;\"> <span class='title'></span></div> <div style=\"font-size: 9px; margin-left: auto; margin-right: 1cm; \"> <span class='date'></span></div>",
"description": "%digital-ide.function.doc.pdf.footerTemplate.title%"
},
"digital-ide.function.simulate.icarus.installPath": {
"digital-ide.prj.iverilog.install.path": {
"type": "string",
"description": "%digital-ide.function.simulate.icarus.installPath.title%"
"description": "%digital-ide.prj.iverilog.install.path.title%"
},
"digital-ide.function.simulate.simulationHome": {
"type": "string",
@ -225,66 +240,83 @@
"type": "boolean",
"default": true
},
"digital-ide.function.lsp.linter.vlog.diagnostor": {
"digital-ide.function.lsp.linter.verilog.diagnostor": {
"type": "string",
"enumDescriptions": [
"use diagnostor in vivado",
"use diagnostor in modelsim",
"use our buildin diagnostor"
"iverilog (© Icarus Verilog Project)",
"xvlog (© Xilinx, Inc.)",
"vlog (© Mentor Graphics Corporation)",
"verilator (© Verilator Project)",
"verible-verilog-syntax (© Google LLC)"
],
"enum": [
"iverilog",
"vivado",
"modelsim",
"default"
"verilator",
"verible"
],
"default": "default",
"description": "%digital-ide.function.lsp.linter.vlog.diagnostor.title%"
},
"digital-ide.function.lsp.linter.svlog.diagnostor": {
"type": "string",
"enumDescriptions": [
"use diagnostor in vivado",
"use diagnostor in modelsim",
"use our buildin diagnostor"
],
"enum": [
"vivado",
"modelsim",
"default"
],
"default": "default",
"description": "%digital-ide.function.lsp.linter.svlog.diagnostor.title%"
},
"digital-ide.function.lsp.linter.vhdl.diagnostor": {
"type": "string",
"enumDescriptions": [
"use diagnostor in vivado",
"use diagnostor in modelsim",
"use our buildin diagnostor"
],
"enum": [
"vivado",
"modelsim",
"default"
],
"default": "default",
"description": "%digital-ide.function.lsp.linter.vhdl.diagnostor.title%"
"default": "vivado",
"description": "%digital-ide.function.lsp.linter.verilog.diagnostor.title%"
},
"digital-ide.function.lsp.linter.systemverilog.diagnostor": {
"type": "string",
"enumDescriptions": [
"use diagnostor in vivado",
"use diagnostor in modelsim",
"use our buildin diagnostor"
"xvlog (© Xilinx, Inc.)",
"vlog (© Mentor Graphics Corporation)",
"verilator (© Verilator Project)",
"verible-verilog-syntax (© Google LLC)"
],
"enum": [
"vivado",
"modelsim",
"default"
"verilator",
"verible"
],
"default": "default",
"default": "vivado",
"description": "%digital-ide.function.lsp.linter.systemverilog.diagnostor.title%"
},
"digital-ide.function.lsp.linter.vhdl.diagnostor": {
"type": "string",
"enumDescriptions": [
"xvlog (© Xilinx, Inc.)",
"vlog (© Mentor Graphics Corporation)"
],
"enum": [
"vivado",
"modelsim"
],
"default": "vivado",
"description": "%digital-ide.function.lsp.linter.vhdl.diagnostor.title%"
},
"digital-ide.function.lsp.linter.mode": {
"type": "string",
"enumDescriptions": [
"%digital-ide.function.lsp.linter.mode.0.title%",
"%digital-ide.function.lsp.linter.mode.1.title%",
"%digital-ide.function.lsp.linter.mode.2.title%"
],
"enum": [
"full",
"common",
"shutdown"
],
"default": "full",
"description": "%digital-ide.function.lsp.linter.mode.title%"
},
"digital-ide.function.lsp.linter.linter-level": {
"type": "string",
"enumDescriptions": [
"%digital-ide.function.lsp.linter.linter-level.error.title%",
"%digital-ide.function.lsp.linter.linter-level.warning.title%"
],
"enum": [
"error",
"warning"
],
"default": "warning",
"description": "%digital-ide.function.lsp.linter.linter-level.title%"
},
"digital-ide.function.instantiation.addComment": {
"description": "%digital-ide.function.instantiation.addComment.title%",
"type": "boolean",
@ -306,6 +338,21 @@
"type": "integer",
"default": 1,
"description": "%digital-ide.function.lsp.file-parse-maxsize.title%"
},
"digital-ide.function.netlist.schema-mode": {
"type": "string",
"default": "before",
"enum": [
"before",
"after",
"RTL"
],
"enumDescriptions": [
"%digital-ide.function.netlist.schema-mode.0.title%",
"%digital-ide.function.netlist.schema-mode.1.title%",
"%digital-ide.function.netlist.schema-mode.2.title%"
],
"description": "%digital-ide.function.netlist.schema-mode.title%"
}
}
},
@ -378,130 +425,130 @@
},
{
"command": "digital-ide.treeView.arch.expand",
"category": "tool",
"category": "Digital-IDE",
"icon": "$(expand-all)",
"title": "%digital-ide.treeView.arch.expand.title%"
},
{
"command": "digital-ide.treeView.arch.collapse",
"category": "tool",
"category": "Digital-IDE",
"icon": "$(collapse-all)",
"title": "%digital-ide.treeView.arch.collapse.title%"
},
{
"command": "digital-ide.treeView.arch.refresh",
"category": "tool",
"category": "Digital-IDE",
"icon": "$(refresh)",
"title": "%digital-ide.treeView.arch.refresh.title%"
},
{
"command": "digital-ide.treeView.arch.openFile",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.treeView.arch.openFile.title%"
},
{
"command": "digital-ide.soft.launch",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.soft.launch.title%"
},
{
"command": "digital-ide.soft.build",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.soft.build.title%"
},
{
"command": "digital-ide.soft.download",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.soft.download.title%"
},
{
"command": "digital-ide.hard.launch",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.launch.title%"
},
{
"command": "digital-ide.hard.simulate",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.simulate.title%"
},
{
"command": "digital-ide.hard.simulate.cli",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.simulate.cli.title%"
},
{
"command": "digital-ide.hard.simulate.gui",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.simulate.gui.title%"
},
{
"command": "digital-ide.hard.refresh",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.refresh.title%"
},
{
"command": "digital-ide.hard.build",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.build.title%"
},
{
"command": "digital-ide.hard.build.synth",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.build.synth.title%"
},
{
"command": "digital-ide.hard.build.impl",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.build.impl.title%"
},
{
"command": "digital-ide.hard.build.bitstream",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.build.bitstream.title%"
},
{
"command": "digital-ide.hard.program",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.program.title%"
},
{
"command": "digital-ide.hard.gui",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.gui.title%"
},
{
"command": "digital-ide.hard.exit",
"category": "tool",
"category": "Digital-IDE",
"title": "%digital-ide.hard.exit.title%"
},
{
"command": "digital-ide.pl.setSrcTop",
"category": "pl",
"category": "Digital-IDE",
"title": "%digital-ide.pl.setSrcTop.title%"
},
{
"command": "digital-ide.pl.setSimTop",
"category": "pl",
"category": "Digital-IDE",
"title": "%digital-ide.pl.setSimTop.title%"
},
{
"command": "digital-ide.pl.addDevice",
"category": "pl",
"category": "Digital-IDE",
"title": "%digital-ide.pl.addDevice.title%"
},
{
"command": "digital-ide.pl.delDevice",
"category": "pl",
"category": "Digital-IDE",
"title": "%digital-ide.pl.delDevice.title%"
},
{
"command": "digital-ide.pl.addFile",
"category": "pl",
"category": "Digital-IDE",
"title": "%digital-ide.pl.addFile.title%"
},
{
"command": "digital-ide.pl.delFile",
"category": "pl",
"category": "Digital-IDE",
"title": "%digital-ide.pl.delFile.title%"
},
{
@ -513,6 +560,15 @@
"category": "Digital-IDE",
"title": "%digital-ide.netlist.title%"
},
{
"command": "digital-ide.netlist.run-ys",
"icon": {
"light": "images/svg/light/ys.svg",
"dark": "images/svg/dark/ys.svg"
},
"category": "Digital-IDE",
"title": "%digital-ide.run-ys.title%"
},
{
"command": "digital-ide.fsm",
"icon": {
@ -557,6 +613,11 @@
"category": "Digital-IDE",
"title": "%digital-ide.digital-lsp.download.title%"
},
{
"command": "digital-ide.digital-lsp.install",
"category": "Digital-IDE",
"title": "%digital-ide.digital-lsp.install.title%"
},
{
"command": "digital-ide.vhdl2vlog",
"title": "%digital-ide.vhdl2vlog.title%",
@ -584,6 +645,15 @@
"category": "Digital-IDE",
"title": "%digital-ide.netlist.show.title%"
},
{
"command": "digital-ide.netlist.treeview",
"icon": {
"light": "images/svg/light/netlist.svg",
"dark": "images/svg/dark/netlist.svg"
},
"category": "Digital-IDE",
"title": "test"
},
{
"command": "digital-ide.waveviewer.show",
"icon": {
@ -597,6 +667,11 @@
"command": "digital-ide.tool.clean",
"category": "Digital-IDE",
"title": "%digital-ide.tool.clean.title%"
},
{
"command": "digital-ide.structure.from-xilinx-to-standard",
"category": "Digital-IDE",
"title": "%digital-ide.structure.from-xilinx-to-standard.title%"
}
],
"menus": {
@ -627,9 +702,12 @@
}
},
{
"command": "digital-ide.netlist.show",
"command": "digital-ide.netlist.treeview",
"group": "inline@3",
"when": "view == digital-ide-treeView-arch && viewItem == file"
"when": "view == digital-ide-treeView-arch && viewItem == file",
"args": {
"file": "${viewItem}"
}
},
{
"command": "digital-ide.pl.setSrcTop",
@ -664,16 +742,6 @@
"command": "digital-ide.tool.icarus.simulateFile",
"group": "navigation@1"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.fsm.show",
"group": "navigation@2"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.netlist.show",
"group": "navigation@3"
},
{
"when": "editorLangId == vcd || editorLangId == view",
"command": "digital-ide.waveviewer.show",
@ -688,49 +756,19 @@
"when": "resourceLangId == vhdl",
"command": "digital-ide.vhdl2vlog",
"group": "navigation@6"
},
{
"when": "editorLangId == ys",
"command": "digital-ide.netlist.run-ys",
"group": "navigation@1"
}
],
"editor/context": [
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.pl.setSrcTop",
"group": "navigation@1"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.pl.setSimTop",
"group": "navigation@2"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.tool.instance",
"group": "navigation@3"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.tool.testbench",
"group": "navigation@4"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.tool.icarus.simulateFile",
"group": "navigation@5"
},
{
"when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl",
"command": "digital-ide.netlist.show",
"group": "navigation@6"
},
{
"when": "resourceLangId == vcd || resourceLangId == vcd",
"command": "digital-ide.waveviewer.show",
"group": "navigation@7"
},
{
"when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl",
"command": "digital-ide.fsm.show",
"group": "navigation@8"
},
{
"when": "resourceLangId == vhdl",
"command": "digital-ide.vhdl2vlog",
@ -753,31 +791,16 @@
"command": "digital-ide.pl.setSimTop",
"group": "navigation@6"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.tool.testbench",
"group": "navigation@7"
},
{
"when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl",
"command": "digital-ide.tool.instance",
"group": "navigation@8"
},
{
"when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl",
"command": "digital-ide.netlist.show",
"group": "navigation@9"
},
{
"when": "resourceLangId == vcd || resourceLangId == view",
"command": "digital-ide.waveviewer.show",
"group": "navigation@10"
},
{
"when": "resourceLangId == verilog || resourceLangId == systemverilog || resourceLangId == vhdl",
"command": "digital-ide.fsm.show",
"group": "navigation@11"
},
{
"when": "resourceLangId == vhdl",
"command": "digital-ide.vhdl2vlog",
@ -818,15 +841,18 @@
"TreeView": [
{
"id": "digital-ide-treeView-arch",
"name": "architecture"
"name": "architecture",
"icon": "images/svg/view.svg"
},
{
"id": "digital-ide-treeView-tool",
"name": "TOOL Options"
"name": "TOOL Options",
"icon": "images/svg/view.svg"
},
{
"id": "digital-ide-treeView-hardware",
"name": "HARD Options"
"name": "HARD Options",
"icon": "images/svg/view.svg"
}
]
},
@ -990,6 +1016,28 @@
"light": "./images/svg/light/view.svg"
}
},
{
"id": "dideignore",
"filenames": [
".dideignore"
],
"icon": {
"dark": "./images/icon.svg",
"light": "./images/icon.svg"
},
"configuration": "./config/ignore.configuration.json"
},
{
"id": "ys",
"extensions": [
".ys"
],
"icon": {
"dark": "./images/svg/dark/ys.svg",
"light": "./images/svg/dark/ys.svg"
},
"configuration": "./config/ys.configuration.json"
},
{
"id": "digital-ide-output",
"mimetypes": [
@ -1043,6 +1091,16 @@
"language": "digital-ide-output",
"scopeName": "digital-ide.output",
"path": "./syntaxes/digital-ide-output.json"
},
{
"language": "dideignore",
"scopeName": "source.dideignore",
"path": "./syntaxes/ignore.json"
},
{
"language": "ys",
"scopeName": "source.ys",
"path": "./syntaxes/ys.json"
}
],
"snippets": [
@ -1201,16 +1259,15 @@
"test": "node ./out/test/runTest.js"
},
"devDependencies": {
"@types/glob": "^8.0.0",
"@types/mocha": "^10.0.0",
"@types/node": "16.x",
"@types/pako": "^2.0.3",
"@types/showdown": "^2.0.0",
"@types/vscode": "^1.72.0",
"@typescript-eslint/eslint-plugin": "^5.42.0",
"@typescript-eslint/parser": "^5.42.0",
"@vscode/test-electron": "^2.2.0",
"eslint": "^8.26.0",
"glob": "^8.0.3",
"mocha": "^10.1.0",
"typescript": "^4.8.4",
"webpack-cli": "^5.1.4"
@ -1218,7 +1275,9 @@
"dependencies": {
"axios": "^1.7.7",
"bson": "^6.8.0",
"chokidar": "^3.5.3",
"chokidar": "^4.0.1",
"minimatch": "^10.0.1",
"pako": "^2.1.0",
"puppeteer-core": "^19.4.1",
"showdown": "^2.1.0",
"state-machine-cat": "^9.2.5",
@ -1230,4 +1289,4 @@
"wavedrom": "^2.9.1",
"zlib": "^1.0.5"
}
}
}

25
package.nls.de.json
View File

@ -71,7 +71,7 @@
"digital-ide.function.doc.pdf.margin.left.title": "top margin of exported pdf, unit cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "html template of header, if displayHeaderFooter is set to false, this setting will be ignored",
"digital-ide.function.doc.pdf.footerTemplate.title": "html template of footer, if displayHeaderFooter is set to false, this setting will be ignored",
"digital-ide.function.simulate.icarus.installPath.title": "Path of install path of iverilog components, if set to \"\", then iverilog and vvp in environment will be used for simulation. Otherwise, ones that in the install path will be used.",
"digital-ide.prj.iverilog.install.path.title": "Path of install path of iverilog components, if set to \"\", then iverilog and vvp in environment will be used for simulation. Otherwise, ones that in the install path will be used.",
"digital-ide.function.simulate.simulationHome.title": "Path of simulation folder, .vvp and other file during simulation will be generated here",
"digital-ide.function.simulate.gtkwavePath.title": "Absolute path of launch path of gtkwave software",
"digital-ide.function.simulate.xilinxLibPath.title": "Path of Xilinx library for simulation",
@ -84,12 +84,27 @@
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "Indentation",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "`include \"xxx.v\" will be added to the top of the file automatically",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "complete everything invoking a module needs including paramters and ports",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "choose diagnostor to do linter in editing verilog",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "choose diagnostor to do linter in editing verilog",
"digital-ide.function.lsp.linter.verilog.diagnostor.title": "choose diagnostor to do linter in editing verilog",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "choose diagnostor to do linter in editing verilog",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "choose diagnostor to do linter in editing vhdl",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "choose diagnostor to do linter in editing systemverilog",
"digital-ide.function.instantiation.addComment.title": "add comment like // ports, // input, // output when doing instantiation, including completion for module invoking",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "auto declare output type nets in the scope when instantiation happens.",
"fpga-support.onTypeFormattingTriggerCharacters.title": "Trigger characters for onTypeFormatting",
"digital-ide.function.lsp.file-parse-maxsize.title": ""
"digital-ide.function.lsp.file-parse-maxsize.title": "",
"digital-ide.structure.from-xilinx-to-standard.title": "Konvertieren Sie Xilinx-Projekte in die Digital IDE-Standardprojektstruktur",
"digital-ide.prj.verible.install.path.title": "Installationsverzeichnispfad für verible, also der absolute Pfad des Ordners, der die ausführbare Datei verible-verilog-syntax enthält. Wenn nicht angegeben, wird standardmäßig verible-verilog-syntax für die Diagnose verwendet.",
"digital-ide.prj.verilator.install.path.title": "Installationsverzeichnispfad für verilator, also der absolute Pfad des Ordners, der die ausführbare Datei verilator enthält. Wenn nicht angegeben, wird standardmäßig verilator für die Diagnose verwendet.",
"digital-ide.function.lsp.linter.mode.title": "Diagnosemodus des Linters festlegen",
"digital-ide.function.lsp.linter.mode.0.title": "Diagnostizieren Sie alle Designquellen direkt und melden Sie Fehler, unabhängig davon, ob die Dateien geöffnet sind.",
"digital-ide.function.lsp.linter.mode.1.title": "Wenn eine einzelne Datei geschlossen ist, wird der entsprechende Fehler entfernt, und nur die geöffnete Datei wird diagnostiziert.",
"digital-ide.function.lsp.linter.mode.2.title": "Global deaktiviert, d.h. für das gesamte Projekt werden keine Projektfehler gemeldet.",
"digital-ide.function.lsp.linter.linter-level.title": "Diagnoselevel-Einstellungen des Linters",
"digital-ide.function.lsp.linter.linter-level.error.title": "Nur Fehler anzeigen",
"digital-ide.function.lsp.linter.linter-level.warning.title": "Fehler und Warnungen anzeigen",
"digital-ide.function.netlist.schema-mode.title": "Netlist-Synthesemodus auswählen",
"digital-ide.function.netlist.schema-mode.0.title": "Prä-Verhaltenssynthese",
"digital-ide.function.netlist.schema-mode.1.title": "Post-Verhaltenssynthese",
"digital-ide.function.netlist.schema-mode.2.title": "Post-RTL-Synthese",
"digital-ide.run-ys.title": "yosys-Skript ausführen",
"digital-ide.digital-lsp.install.title": "Digital LSP-Sprachserver installieren"
}

25
package.nls.ja.json
View File

@ -71,7 +71,7 @@
"digital-ide.function.doc.pdf.margin.left.title": "エクスポートされた PDF の左余白、単位 cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "ヘッダーの HTML テンプレート、displayHeaderFooter が false に設定されている場合、この設定は無視されます",
"digital-ide.function.doc.pdf.footerTemplate.title": "フッターの HTML テンプレート、displayHeaderFooter が false に設定されている場合、この設定は無視されます",
"digital-ide.function.simulate.icarus.installPath.title": "Icarus Verilog コンポーネントのインストールパス、空に設定されている場合、環境の iverilog と vvp がシミュレーションに使用されます。それ以外の場合、インストールパスのコンポーネントが使用されます。",
"digital-ide.prj.iverilog.install.path.title": "Icarus Verilog コンポーネントのインストールパス、空に設定されている場合、環境の iverilog と vvp がシミュレーションに使用されます。それ以外の場合、インストールパスのコンポーネントが使用されます。",
"digital-ide.function.simulate.simulationHome.title": "シミュレーションフォルダのパス、シミュレーション中の .vvp およびその他のファイルがここに生成されます",
"digital-ide.function.simulate.gtkwavePath.title": "gtkwave ソフトウェアの起動パスの絶対パス",
"digital-ide.function.simulate.xilinxLibPath.title": "シミュレーション用の Xilinx ライブラリのパス",
@ -84,12 +84,27 @@
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "インデント",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "モジュールの自動補完をトリガーするとき、トップの include マクロにインスタンス化されたモジュールがあるファイルが含まれていない場合、ファイルの先頭に `include \"xxx.v\" を自動的に追加します",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "モジュールの自動補完をトリガーするとき、インスタンス化されたモジュールの上に output タイプの信号の宣言を自動的に生成します",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "Verilog 編集時のリンターを行う診断器を選択します",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "SystemVerilog 編集時のリンターを行う診断器を選択します",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "VHDL 編集時のリンターを行う診断器を選択します",
"digital-ide.function.lsp.linter.verilog.diagnostor.title": "Verilog 編集時のリンターを行う診断器を選択します",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "SystemVerilog 編集時のリンターを行う診断器を選択します",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "VHDL 編集時のリンターを行う診断器を選択します",
"digital-ide.function.instantiation.addComment.title": "インスタンス化時に // ポート, // 入力, // 出力 のようなコメントを追加し、モジュール呼び出しの補完を含みます",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "インスタンス化が発生したときにスコープ内で出力タイプのネットを自動的に宣言します。",
"fpga-support.onTypeFormattingTriggerCharacters.title": "onTypeFormatting のトリガー文字",
"digital-ide.function.lsp.file-parse-maxsize.title": ""
"digital-ide.function.lsp.file-parse-maxsize.title": "",
"digital-ide.structure.from-xilinx-to-standard.title": "Xilinx プロジェクトを Digital IDE 標準プロジェクト構造に変換する",
"digital-ide.prj.verible.install.path.title": "verible のインストールディレクトリパス。つまり、verible-verilog-syntax 実行ファイルを含むフォルダの絶対パス。指定しない場合、デフォルトで verible-verilog-syntax が診断に使用されます。",
"digital-ide.prj.verilator.install.path.title": "verilator のインストールディレクトリパス。つまり、verilator 実行ファイルを含むフォルダの絶対パス。指定しない場合、デフォルトで verilator が診断に使用されます。",
"digital-ide.function.lsp.linter.mode.title": "リンターの診断モードを指定",
"digital-ide.function.lsp.linter.mode.0.title": "すべての設計ソースを直接診断し、エラーを報告します。ファイルが開いているかどうかに関係なく。",
"digital-ide.function.lsp.linter.mode.1.title": "単一のファイルが閉じられた場合、対応するエラーが削除され、開いているファイルのみが診断されます。",
"digital-ide.function.lsp.linter.mode.2.title": "グローバルに無効化され、プロジェクト全体でプロジェクトエラーが報告されません。",
"digital-ide.function.lsp.linter.linter-level.title": "診断器の診断レベル設定",
"digital-ide.function.lsp.linter.linter-level.error.title": "エラーのみ表示",
"digital-ide.function.lsp.linter.linter-level.warning.title": "エラーと警告を表示",
"digital-ide.function.netlist.schema-mode.title": "Netlist 合成モードを選択",
"digital-ide.function.netlist.schema-mode.0.title": "ビヘイビア前合成",
"digital-ide.function.netlist.schema-mode.1.title": "ビヘイビア後合成",
"digital-ide.function.netlist.schema-mode.2.title": "RTL後合成",
"digital-ide.run-ys.title": "yosys スクリプトを実行",
"digital-ide.digital-lsp.install.title": "Digital LSP 言語サーバーをインストール"
}

27
package.nls.json
View File

@ -6,7 +6,7 @@
"digital-ide.hdlDoc.showWebview.title": "Show the document of current file in a webview",
"digital-ide.tool.instance.title": "Generate instance template from selected module",
"digital-ide.tool.testbench.title": "Generate testbench template from current file",
"digital-ide.tool.icarus.simulateFile.title": "Do simulation for current file",
"digital-ide.tool.icarus.simulateFile.title": "Do simulation for current module",
"digital-ide.treeView.arch.expand.title": "Expand all the items in tree view",
"digital-ide.treeView.arch.collapse.title": "Collapse all the items in tree view",
"digital-ide.treeView.arch.refresh.title": "Refresh the tree view",
@ -71,7 +71,7 @@
"digital-ide.function.doc.pdf.margin.left.title": "Left margin of the exported PDF, unit cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "HTML template of the header, if displayHeaderFooter is set to false, this setting will be ignored",
"digital-ide.function.doc.pdf.footerTemplate.title": "HTML template of the footer, if displayHeaderFooter is set to false, this setting will be ignored",
"digital-ide.function.simulate.icarus.installPath.title": "Installation path of Icarus Verilog components, if set to empty, the iverilog and vvp in the environment will be used for simulation. Otherwise, the components in the installation path will be used.",
"digital-ide.prj.iverilog.install.path.title": "Installation path of Icarus Verilog components, if set to empty, the iverilog and vvp in the environment will be used for simulation. Otherwise, the components in the installation path will be used.",
"digital-ide.function.simulate.simulationHome.title": "Path of the simulation folder, .vvp and other files during simulation will be generated here",
"digital-ide.function.simulate.gtkwavePath.title": "Absolute path of the launch path of the gtkwave software",
"digital-ide.function.simulate.xilinxLibPath.title": "Path of the Xilinx library for simulation",
@ -84,12 +84,27 @@
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "Indentation",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "When triggering module auto-completion, if the top include macro does not include the file where the instantiated module is located, automatically add `include \"xxx.v\" at the top of the file",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "When triggering module auto-completion, automatically generate the declaration of output type signals above the instantiated module",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "Choose the diagnostor to do linter in editing Verilog",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "Choose the diagnostor to do linter in editing SystemVerilog",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "Choose the diagnostor to do linter in editing VHDL",
"digital-ide.function.lsp.linter.verilog.diagnostor.title": "Choose the diagnostor to do linter in editing Verilog",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "Choose the diagnostor to do linter in editing SystemVerilog",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "Choose the diagnostor to do linter in editing VHDL",
"digital-ide.function.instantiation.addComment.title": "Add comments like // ports, // input, // output when doing instantiation, including completion for module invoking",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "Automatically declare output type nets in the scope when instantiation happens.",
"fpga-support.onTypeFormattingTriggerCharacters.title": "Trigger characters for onTypeFormatting",
"digital-ide.function.lsp.file-parse-maxsize.title": ""
"digital-ide.function.lsp.file-parse-maxsize.title": "",
"digital-ide.structure.from-xilinx-to-standard.title": "Convert Xilinx projects to Digital IDE standard project structure",
"digital-ide.prj.verible.install.path.title": "Installation directory path for verible, which is the absolute path of the folder containing the verible-verilog-syntax executable. If not specified, verible-verilog-syntax will be used for diagnostics by default.",
"digital-ide.prj.verilator.install.path.title": "Installation directory path for verilator, which is the absolute path of the folder containing the verilator executable. If not specified, verilator will be used for diagnostics by default.",
"digital-ide.function.lsp.linter.mode.title": "Specify the diagnostic mode of the linter",
"digital-ide.function.lsp.linter.mode.0.title": "Diagnose all design sources directly and report errors, regardless of whether the files are open.",
"digital-ide.function.lsp.linter.mode.1.title": "When a single file is closed, the corresponding error is removed, and only the file that is opened is diagnosed.",
"digital-ide.function.lsp.linter.mode.2.title": "Globally disabled, meaning no project errors are reported for the entire project.",
"digital-ide.function.lsp.linter.linter-level.title": "Diagnostic Level Settings for the Linter",
"digital-ide.function.lsp.linter.linter-level.error.title": "Show Only Errors",
"digital-ide.function.lsp.linter.linter-level.warning.title": "Show Errors and Warnings",
"digital-ide.function.netlist.schema-mode.title": "Select Netlist Synthesis Mode",
"digital-ide.function.netlist.schema-mode.0.title": "Pre-Behavioral Synthesis",
"digital-ide.function.netlist.schema-mode.1.title": "Post-Behavioral Synthesis",
"digital-ide.function.netlist.schema-mode.2.title": "Post-RTL Synthesis",
"digital-ide.run-ys.title": "Run yosys script",
"digital-ide.digital-lsp.install.title": "Install Digital LSP Language Server"
}

27
package.nls.zh-cn.json
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@ -6,7 +6,7 @@
"digital-ide.hdlDoc.showWebview.title": "在 webview 中展示文档",
"digital-ide.tool.instance.title": "生成选中 module 的例化模板",
"digital-ide.tool.testbench.title": "从当前文件中选择 module 生成 testbench",
"digital-ide.tool.icarus.simulateFile.title": "对当前文件进行仿真",
"digital-ide.tool.icarus.simulateFile.title": "对当前模块进行仿真",
"digital-ide.treeView.arch.expand.title": "展开视图中的所有项目",
"digital-ide.treeView.arch.collapse.title": "收起视图中的所有项目",
"digital-ide.treeView.arch.refresh.title": "刷新树视图",
@ -71,7 +71,7 @@
"digital-ide.function.doc.pdf.margin.left.title": "导出的 PDF 的左边距，单位 cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "页眉的 HTML 模板，如果 displayHeaderFooter 设置为 false，则此设置将被忽略",
"digital-ide.function.doc.pdf.footerTemplate.title": "页脚的 HTML 模板，如果 displayHeaderFooter 设置为 false，则此设置将被忽略",
"digital-ide.function.simulate.icarus.installPath.title": "Icarus Verilog 组件的安装路径，如果设置为空，则使用环境中的 iverilog 和 vvp 进行仿真。否则，将使用安装路径中的组件。",
"digital-ide.prj.iverilog.install.path.title": "Icarus Verilog 组件的安装路径，如果设置为空，则使用环境中的 iverilog 和 vvp 进行仿真。否则，将使用安装路径中的组件。",
"digital-ide.function.simulate.simulationHome.title": "仿真文件夹路径，仿真期间的 .vvp 和其他文件将生成在此处",
"digital-ide.function.simulate.gtkwavePath.title": "gtkwave 软件的启动路径的绝对路径",
"digital-ide.function.simulate.xilinxLibPath.title": "仿真用 Xilinx 库的路径",
@ -84,12 +84,27 @@
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "缩进",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "触发模块的自动补全时，如果顶部 include 宏中没有包含被例化模块所在的文件，则自动在文件顶部添加 `include \"xxx.v\"",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "触发模块的自动补全时，在例化模块上方自动生成 output 类型信号的申明",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "选择编辑 Verilog 时的诊断器进行语法检查",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "选择编辑 SystemVerilog 时的诊断器进行语法检查",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "选择编辑 VHDL 时的诊断器进行语法检查",
"digital-ide.function.lsp.linter.verilog.diagnostor.title": "选择编辑 Verilog 时的诊断器进行语法检查",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "选择编辑 SystemVerilog 时的诊断器进行语法检查",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "选择编辑 VHDL 时的诊断器进行语法检查",
"digital-ide.function.instantiation.addComment.title": "在进行实例化时添加注释，如 // 端口, // 输入, // 输出，包括模块调用的完成",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "在实例化发生时自动在作用域中声明输出类型的网络。",
"fpga-support.onTypeFormattingTriggerCharacters.title": "onTypeFormatting 的触发字符",
"digital-ide.function.lsp.file-parse-maxsize.title": "最大解析的文件阈值，大小超出这个值的文件不会被解析。单位为 MB，必须是整数。默认为 1MB"
"digital-ide.function.lsp.file-parse-maxsize.title": "最大解析的文件阈值，大小超出这个值的文件不会被解析。单位为 MB，必须是整数。默认为 1MB",
"digital-ide.structure.from-xilinx-to-standard.title": "将 Xilinx 项目转换成 Digital IDE 标准项目结构",
"digital-ide.prj.verible.install.path.title": "verible 的安装目录路径，也就是包含 verible-verilog-syntax 可执行文件的文件夹的绝对路径。如果不指定，默认采用 verible-verilog-syntax 执行诊断。",
"digital-ide.prj.verilator.install.path.title": "verilator 的安装目录路径，也就是包含了 verilator 可执行文件的文件夹的绝对路径。如果不指定，默认采用 verilator 执行诊断。",
"digital-ide.function.lsp.linter.mode.title": "指定诊断器的诊断模式",
"digital-ide.function.lsp.linter.mode.0.title": "将所有设计源直接进行诊断，并报错，无论文件是否打开。",
"digital-ide.function.lsp.linter.mode.1.title": "单文件关闭时，对应报错去除，打开哪个文件就对哪个文件进行诊断。",
"digital-ide.function.lsp.linter.mode.2.title": "全局关闭，即整个工程都不进行工程报错。",
"digital-ide.function.lsp.linter.linter-level.title": "诊断器诊断等级设置",
"digital-ide.function.lsp.linter.linter-level.error.title": "只显示错误",
"digital-ide.function.lsp.linter.linter-level.warning.title": "显示错误和警告",
"digital-ide.function.netlist.schema-mode.title": "选择 Netlist 综合模式",
"digital-ide.function.netlist.schema-mode.0.title": "行为前综合",
"digital-ide.function.netlist.schema-mode.1.title": "行为后综合",
"digital-ide.function.netlist.schema-mode.2.title": "RTL后综合",
"digital-ide.run-ys.title": "运行 yosys 脚本",
"digital-ide.digital-lsp.install.title": "安装 Digital LSP 语言服务器"
}

27
package.nls.zh-tw.json
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@ -6,7 +6,7 @@
"digital-ide.hdlDoc.showWebview.title": "在 webview 中展示文檔",
"digital-ide.tool.instance.title": "生成選中 module 的例化模板",
"digital-ide.tool.testbench.title": "從當前文件中選擇 module 生成 testbench",
"digital-ide.tool.icarus.simulateFile.title": "對當前文件進行仿真",
"digital-ide.tool.icarus.simulateFile.title": "對當前文模块進行仿真",
"digital-ide.treeView.arch.expand.title": "展開視圖中的所有項目",
"digital-ide.treeView.arch.collapse.title": "收起視圖中的所有項目",
"digital-ide.treeView.arch.refresh.title": "刷新樹視圖",
@ -71,7 +71,7 @@
"digital-ide.function.doc.pdf.margin.left.title": "導出的 PDF 的左邊距，單位 cm",
"digital-ide.function.doc.pdf.headerTemplate.title": "頁眉的 HTML 模板，如果 displayHeaderFooter 設置為 false，則此設置將被忽略",
"digital-ide.function.doc.pdf.footerTemplate.title": "頁腳的 HTML 模板，如果 displayHeaderFooter 設置為 false，則此設置將被忽略",
"digital-ide.function.simulate.icarus.installPath.title": "Icarus Verilog 組件的安裝路徑，如果設置為空，則使用環境中的 iverilog 和 vvp 進行仿真。否則，將使用安裝路徑中的組件。",
"digital-ide.prj.iverilog.install.path.title": "Icarus Verilog 組件的安裝路徑，如果設置為空，則使用環境中的 iverilog 和 vvp 進行仿真。否則，將使用安裝路徑中的組件。",
"digital-ide.function.simulate.simulationHome.title": "仿真文件夾路徑，仿真期間的 .vvp 和其他文件將生成在此處",
"digital-ide.function.simulate.gtkwavePath.title": "gtkwave 軟件的啟動路徑的絕對路徑",
"digital-ide.function.simulate.xilinxLibPath.title": "仿真用 Xilinx 庫的路徑",
@ -84,12 +84,27 @@
"digital-ide.function.lsp.formatter.vhdl.default.indentation.title": "縮進",
"digital-ide.function.lsp.completion.vlog.auto-add-include.title": "觸發模塊的自動補全時，如果頂部 include 宏中沒有包含被例化模塊所在的文件，則自動在文件頂部添加 `include \"xxx.v\"",
"digital-ide.function.lsp.completion.vlog.auto-add-output-declaration.title": "觸發模塊的自動補全時，在例化模塊上方自動生成 output 類型信號的申明",
"digital-ide.function.lsp.linter.vlog.diagnostor.title": "選擇編輯 Verilog 時的診斷器進行語法檢查",
"digital-ide.function.lsp.linter.svlog.diagnostor.title": "選擇編輯 SystemVerilog 時的診斷器進行語法檢查",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "選擇編輯 VHDL 時的診斷器進行語法檢查",
"digital-ide.function.lsp.linter.verilog.diagnostor.title": "選擇編輯 Verilog 時的診斷器進行語法檢查",
"digital-ide.function.lsp.linter.systemverilog.diagnostor.title": "選擇編輯 SystemVerilog 時的診斷器進行語法檢查",
"digital-ide.function.lsp.linter.vhdl.diagnostor.title": "選擇編輯 VHDL 時的診斷器進行語法檢查",
"digital-ide.function.instantiation.addComment.title": "在進行實例化時添加註釋，如 // 端口, // 輸入, // 輸出，包括模塊調用的完成",
"digital-ide.function.instantiation.autoNetOutputDeclaration.title": "在實例化發生時自動在作用域中聲明輸出類型的網絡。",
"fpga-support.onTypeFormattingTriggerCharacters.title": "onTypeFormatting 的觸發字符",
"digital-ide.function.lsp.file-parse-maxsize.title": ""
"digital-ide.function.lsp.file-parse-maxsize.title": "",
"digital-ide.structure.from-xilinx-to-standard.title": "將 Xilinx 專案轉換成 Digital IDE 標準專案結構",
"digital-ide.prj.verible.install.path.title": "verible 的安裝目錄路徑，也就是包含 verible-verilog-syntax 可執行文件的文件夾的絕對路徑。如果不指定，默認採用 verible-verilog-syntax 執行診斷。",
"digital-ide.prj.verilator.install.path.title": "verilator 的安裝目錄路徑，也就是包含了 verilator 可執行文件的文件夾的絕對路徑。如果不指定，默認採用 verilator 執行診斷。",
"digital-ide.function.lsp.linter.mode.title": "指定診斷器的診斷模式",
"digital-ide.function.lsp.linter.mode.0.title": "將所有設計源直接進行診斷，並報錯，無論文件是否打開。",
"digital-ide.function.lsp.linter.mode.1.title": "單文件關閉時，對應報錯去除，打開哪個文件就對哪個文件進行診斷。",
"digital-ide.function.lsp.linter.mode.2.title": "全局關閉，即整個工程都不進行工程報錯。",
"digital-ide.function.lsp.linter.linter-level.title": "診斷器診斷等級設置",
"digital-ide.function.lsp.linter.linter-level.error.title": "只顯示錯誤",
"digital-ide.function.lsp.linter.linter-level.warning.title": "顯示錯誤和警告",
"digital-ide.function.netlist.schema-mode.title": "選擇 Netlist 綜合模式",
"digital-ide.function.netlist.schema-mode.0.title": "行為前綜合",
"digital-ide.function.netlist.schema-mode.1.title": "行為後綜合",
"digital-ide.function.netlist.schema-mode.2.title": "RTL後綜合",
"digital-ide.run-ys.title": "運行 yosys 腳本",
"digital-ide.digital-lsp.install.title": "安裝 Digital LSP 語言伺服器"
}

1
project/property-init.json
View File

@ -6,6 +6,5 @@
"soc": {
"core": "none"
},
"enableShowLog": false,
"device": "none"
}

22
project/property-schema.json
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@ -8,7 +8,7 @@
"description": "The tool chain you need",
"enum": [
"xilinx",
"efinity"
"efinity"
]
},
"prjName": {
@ -198,24 +198,10 @@
"xc7a35tftg256-1",
"xc7a35tcsg324-1",
"xc7z035ffg676-2",
"xc7z020clg484-1"
"xc7z020clg484-1",
"Ti60F100S3F2-C4"
]
},
"iverilogCompileOptions": {
"type": "object",
"description": "options to define iverilog arguments",
"properties": {
"standard": {
"type": "string",
"description": "value of argument -g, default is -g2012",
"default": "2012"
},
"includes": {
"type": "array",
"description": "value of argument -I"
}
}
}
}
},
"required": [
"toolChain",

6
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@ -0,0 +1,6 @@
dide-doc
- view
- index.html
- css
- js
- ...

43
resources/dide-doc/iconfont.css
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@ -1,43 +0,0 @@
@font-face {
font-family: "iconfont"; /* Project id 4748764 */
src: url('iconfont.woff2?t=1731914985969') format('woff2'),
url('iconfont.woff?t=1731914985969') format('woff'),
url('iconfont.ttf?t=1731914985969') format('truetype');
}
.iconfont {
font-family: "iconfont" !important;
font-style: normal;
-webkit-font-smoothing: antialiased;
-moz-osx-font-smoothing: grayscale;
}
.icon-tree:before {
content: "\e601";
}
.icon-verilog:before {
content: "\e634";
}
.icon-top-module:before {
content: "\e682";
}
.icon-top:before {
content: "\e600";
}
.icon-parameter:before {
content: "\e655";
}
.icon-unknown:before {
content: "\e62a";
}
.icon-port:before {
content: "\e638";
}

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64
resources/dide-doc/index.html
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@ -1,64 +0,0 @@
<!DOCTYPE html>
<html lang="en">
<head>
<meta charset="UTF-8">
<meta http-equiv="X-UA-Compatible" content="IE=edge">
<meta name="viewport" content="width=device-width, initial-scale=1.0">
<title>Digital IDE Document</title>
<link rel="stylesheet" href="documentation.css">
<link rel="stylesheet" href="iconfont.css">
</head>
<body>
<div id="wrapper">
<div id="write"></div>
</div>
</body>
<script>
const vscode = acquireVsCodeApi();
function enableHrefVscodeOpen() {
// 自定义超链接
document.querySelectorAll('a').forEach(link => {
link.addEventListener('click', (event) => {
event.preventDefault();
const href = link.getAttribute('href');
if (href.startsWith('file://')) {
vscode.postMessage({
command: 'openFile',
filePath: href
});
}
});
});
}
window.addEventListener('message', event => {
const response = event.data;
const { command, body } = response;
switch (command) {
case 'do-render':
doRender(body);
break;
default:
break;
}
});
window.onload = async () => {
vscode.postMessage({
command: 'do-render'
});
}
function doRender(body) {
document.getElementById('write').innerHTML = body;
enableHrefVscodeOpen();
}
</script>
</html>

42
resources/dide-doc/scripts/update_icon.py
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@ -1,42 +0,0 @@
import requests as r
import os
import shutil
import zipfile
# 下载 压缩包
headers = {
'User-Agent': 'Mozilla/5.0 (Windows NT 10.0; Win64; x64) AppleWebKit/537.36 (KHTML, like Gecko) Chrome/127.0.0.0 Safari/537.36',
'Cookie': 'cna=FeNcHjgPWA8CAXU/P9lD8IsF; EGG_SESS_ICONFONT=Hu68kBY7XO7C6Udp3T99M1asKmUZ0gxjps8xjTrjx4ZtNCIR_nFu9Li15nxoPAWLmGlcEMN2KEQyAvgBfASR3cSsmd2lhqg89lUmApzbWgBgCWjMwMzjawMqh2KNT8kCICxit3iWC7YLdUuCdUfXg_cGkRjPNvDohqyeHF27gTb5CloBSvLjqN45PcUvcUig; ctoken=Ku-GfnHTFQU6ObMjjX4rrwYn; u=10114852; u.sig=mv5vi-TPPlhvQJi2PMIC4VoPpD03Wc9UykMTMiG6ElA; xlly_s=1; tfstk=fSrIwBNqyBACtg2sZ2BZ5BUbpIn7PWsVNLM8n8KeeDnpwQex_JrEY887N5wxykyrvui717NU8DUUPYN4p7glKbl-N7y88OSV0J2nq0K5giSVfSIC9W9pv3B-6YMoT58eCJ2nqdvwwZzTKU6xnQBS27ntXvkj2HHKwO9tnfKKeHHJ6OMo6bn-9v39XxMD9e3Kpbdy1Y7IeJ69Kr6y7I-gLftJcKDKJZyez3-yav0nMVh62Arsd2GYpk3XwyMTblgq7L5ZX-4a9AifbenYCzFbk7b2SDw8J70_t1Ys_PE3eb3wenysPXaTvV9J2RmsN447O6Tn9yPsoA39FiDagfe3vP6k6JFqODHt7iBbB4UaxqqF6HiYoJoUy7b2SDw8JcszunlfpXTWCqxSCjW1CUYrE4jk1CVx8l3KIvIVCOO6r2HiCjW1CUYoJADLuO661Uf..; isg=BCwsfWsQZki1QXEWw0jCCc4h_Qpe5dCP-aVamIZsF1d6kc6br_ZyHmFnsVkpGQjn',
'Pragma': 'no-cache',
'sec-fetch-mode': 'navigate'
}
url = 'https://www.iconfont.cn/api/project/download.zip?spm=a313x.manage_type_myprojects.i1.d7543c303.21213a81tE9WyY&pid=4748764&ctoken=QcRJGHx0m7kL39pW1Slgy_E8'
res = r.get(url, headers=headers)
if res.status_code:
with open('./script/tmp.zip', 'wb') as fp:
fp.write(res.content)
# 解压文件
with zipfile.ZipFile('./script/tmp.zip', 'r') as zipf:
zipf.extractall('./script/tmp')
# 将文件搬运至工作区，我的 css 全放在 public 下面了，你的视情况而定
for parent, _, files in os.walk('./script/tmp'):
for file in files:
filepath = os.path.join(parent, file)
if file.startswith('demo'):
continue
if file.endswith('.css'):
content = open(filepath, 'r', encoding='utf-8').read().replace('font-size: 16px;', '')
open(filepath, 'w', encoding='utf-8').write(content)
shutil.move(filepath, os.path.join('./resources/dide-doc', file))
elif file.endswith('.woff2'):
shutil.move(filepath, os.path.join('./resources/dide-doc', file))
# 删除压缩包和解压区域
os.remove('./script/tmp.zip')
shutil.rmtree('./script/tmp')

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127
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@ -0,0 +1,127 @@
:root {
--main-during: 0.35s;
--fade-during: .5s;
}
.fade-animation-effect {
transition: var(--animation-5s);
-webkit-transition: var(--animation-5s);
-ms-transition: var(--animation-5s);
}
.easy-hidden {
visibility: hidden;
}
.main-fade-enter-from,
.main-fade-leave-to {
opacity: 0;
}
.main-fade-enter-to,
.main-fade-leave-from {
opacity: 1;
}
.main-fade-enter-active,
.main-fade-leave-active {
transition: opacity var(--main-during);
-moz-transition: opacity var(--main-during);
-webkit-transition: opacity var(--main-during);
}
.slide-enter-active,
.slide-leave-active {
transition: all .5s ease-out;
-moz-transition: all .5s ease-out;
-webkit-transition: all .5s ease-out;
}
.slide-enter-from {
position: relative;
transform: translateY(-100px);
opacity: 0%;
}
.slide-leave-to {
transform: translateY(100px);
opacity: 0%;
}
.slide-down-enter-active,
.slide-down-leave-active {
transition: all .5s ease-out;
-moz-transition: all .5s ease-out;
-webkit-transition: all .5s ease-out;
}
.slide-down-enter-from {
position: relative;
transform: translateY(100px);
opacity: 0%;
}
.slide-down-leave-to {
transform: translateY(100px);
opacity: 0%;
}
.slide-up-enter-active,
.slide-up-leave-active {
transition: all .5s ease-out;
-moz-transition: all .5s ease-out;
-webkit-transition: all .5s ease-out;
}
.slide-up-enter-from {
position: relative;
transform: translateY(-100px);
opacity: 0%;
}
.slide-up-leave-to {
transform: translateY(-100px);
opacity: 0%;
}
.collapse-from-top-enter-active,
.collapse-from-top-leave-active {
transition: var(--animation-3s);
-moz-transition: var(--animation-3s);
-webkit-transition: var(--animation-3s);
}
.collapse-from-top-enter-from {
transform: scaleY(0);
transform-origin: center top;
opacity: 0%;
}
.collapse-from-top-leave-to {
transform: scaleY(0);
transform-origin: center top;
opacity: 0%;
}
@keyframes loading-mask {
0% {
background-position: 100% 50%;
}
100% {
background-position: 0 50%;
}
}
@keyframes word-jump {
0% {
transform: translateY(0);
}
20% {
transform: translateY(-5px);
}
80% {
transform: translateY(2px);
}
100% {
transform: translateY(0px);
}
}
.fast-transition {
transition: var(--animation-3s);
}

281
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View File

@ -1,15 +1,138 @@
:root {
--dark-main-color : #df733d;
--light-main-color : #cc6633;
--display-signal-info-height: 50px;
--signal-default-color: #4CAF50;
--main-color: #CB81DA;
--main-transplate-color: rgba(203, 129, 208, 0.1);
--main-hover-color: rgba(203, 129, 208, 0.5);
--shadow-color: rgba(139, 73, 225, 0.99);
--main-dark-color: #2D323B;
--main-light-color: var(--main-color);
--monospace-font: "Cascadia code", monospace;
--dark-theme-border: 1px solid rgba(242, 242, 242, 0.3);
--light-theme-border: 1px solid rgba(142, 142, 142, 0.3);
/* css 动画属性 */
--animation-7s: .7s cubic-bezier(0.23,1,0.32,1);
--animation-5s: .5s cubic-bezier(0.23,1,0.32,1);
--animation-3s: .35s cubic-bezier(0.23,1,0.32,1);
--gray-box-shadow-0: 0 0 8px 3px rgba(182, 181, 182, 0.9);
--gray-box-shadow-1: 0 0 5px 1px rgba(16, 16, 16, 0.5);
}
@font-face {
font-family: "Cascadia code";
src: url("./CascadiaCode.woff2");
}
html, body {
background-color: var(--background);
color: var(--foreground);
}
*::selection {
background-color: var(--main-hover-color) !important;
}
body::-webkit-scrollbar {
width: 0;
}
* hr {
border: none;
background-color: var(--main-color);
height: 1.5px;
width: 95%;
}
/*
::-webkit-scrollbar {
width: 12px;
}
::-webkit-scrollbar-track {
background: var(--sidebar);
}
::-webkit-scrollbar-thumb {
background: var(--scrollbar-background);
border-radius: .3em;
}
::-webkit-scrollbar-thumb:hover {
background: var(--scrollbar-hover);
border-radius: .3em;
}
::-webkit-scrollbar-thumb:active {
background: var(--scrollbar-active);
border-radius: .3em;
}
::-webkit-scrollbar-button {
height: 0;
width: 0;
}
::-webkit-scrollbar-corner {
background: none;
display: none;
} */
.el-select__wrapper {
min-width: 100px;
padding: 13px;
color: var(--sidebar-item-text);
}
.el-select-group__title {
color: var(--main-color) !important;
}
.el-select__placeholder {
color: var(--sidebar-item-text) !important;
}
.el-select-dropdown {
background-color: var(--sidebar);
border: 1.0px solid var(--main-color);
}
.el-checkbox-button__inner {
font-size: 16px !important;
}
a {
color: var(--main-color);
}
.digital-ide-icon {
background-image: url(./icon.svg);
background-size: 100%;
height: 50px;
width: 50px;
}
.digital-ide-icon.big {
background-image: url(./icon.svg);
background-size: 100%;
height: 150px;
width: 150px;
}
.el-radio-button__original-radio:disabled:checked+.el-radio-button__inner {
opacity: 0.6;
}
.el-select__wrapper.is-disabled {
opacity: 0.6;
box-shadow: unset !important;
}
body {
-ms-text-size-adjust: 100%;
-webkit-text-size-adjust: 100%;
line-height: 1.5;
font-family: -apple-system, BlinkMacSystemFont, "Segoe UI", Roboto, Helvetica, Arial, sans-serif, "Apple Color Emoji", "Segoe UI Emoji", "Segoe UI Symbol";
font-size: 16px;
line-height: 1.5;
word-wrap: break-word;
background-attachment: fixed;
@ -37,8 +160,8 @@ a {
}
#write {
padding: 15px 30px;
width: 1000px;
padding: 10px;
width: 800px;
}
.ImgCaption {
@ -435,27 +558,6 @@ li+li {
margin-top: 0.25em;
}
/*
table {
display: block;
width: 100%;
overflow: auto;
}
table th {
font-weight: bold;
}
table th,
table td {
padding: 6px 13px;
border: .7px solid;
}
table tr {
border-top: .7px solid;
} */
img {
max-width: 100%;
@ -479,16 +581,13 @@ img {
#write table thead th {
/* background-color: var(--dark-main-color); */
font-size: 20px;
font-weight: bolder;
width: 100px;
text-align: center;
vertical-align: middle;
padding: 10px;
}
.vscode-dark table {
color: #F0F0F0;
color: var(--vscode-foreground);
}
.vscode-light table {
@ -595,7 +694,7 @@ img {
padding-left: 0;
padding: 20px 0px;
margin: 10px 0 10px 0px;
width: 105px;
width: 95px;
}
.diagram-container .arrow-wrapper {
@ -651,6 +750,20 @@ img {
background-color: rgb(53,59,140);
}
#write .source-ip-tag {
font-size: 0.85rem;
padding: 3px 4px;
border-radius: .5em;
background-color: rgb(24, 91, 149);
}
#write .source-primitive-tag {
font-size: 0.85rem;
padding: 3px 4px;
border-radius: .5em;
background-color: rgb(108, 53, 140);
}
#write .source-unk-tag {
font-size: 0.85rem;
padding: 3px 4px;
@ -658,6 +771,106 @@ img {
background-color: #a09c9c;
}
#write table, th, td {
border: 1px solid var(--vscode-foreground) !important;
}
.vscode-dark table, th, td {
border: 1px solid rgba(242, 242, 242, 0.1) !important;
}
.vscode-light table, th, td {
border: 1px solid rgba(142, 142, 142, 0.1) !important;
}
/* #write table, th {
border-bottom: 1px solid rgb(76, 55, 114) !important;
} */
/* #write table, td {
border-bottom: 1px solid rgba(242, 242, 242, 0.3) !important;
} */
#write table {
border-radius: .3em;
}
.left-align {
text-align: left;
}
.markdown-ext-block {
border-radius: .3em;
border: 1px solid var(--main-color);
background-color: var(--main-transplate-color);
padding: 3px 15px;
margin-bottom: 25px;
}
.markdown-ext-block .iconfont {
font-size: 1.2rem;
margin-right: .7rem;
color: var(--main-color);
}
.markdown-ext-block .title {
color: var(--main-color);
font-weight: 700;
font-size: 1.3rem;
letter-spacing: unset;
line-height: unset;
}
.markdown-ext-block .desc {
color: black;
font-weight: 700;
margin-left: .7rem;
}
.pre-dot::before {
content: "";
display: inline-table;
width: 12px;
height: 12px;
margin-right: 7px;
background-color: var(--main-color);
border-radius: .5em;
}
pre {
-webkit-overflow-scrolling: touch;
font-family: var(--monospace-font), "Courier New", monospace;
font-size: 0.9em;
margin: 0 0 2em 0;
position: relative;
}
pre > code {
display: block;
line-height: 1.75;
padding: 1em 1.5em;
overflow-x: auto;
border-top: rgba(230, 235, 237, 0) solid 35px;
background-color: var(--vscode-textCodeBlock-background);
border-radius: .3em;
font-family: var(--monospace-font), "Courier New", monospace;
font-size: 15px;
margin: 0 0.25em;
transition: all 0.3s linear;
-moz-transition: all 0.3s linear;
-webkit-transition: all 0.3s linear;
}
pre > code:before {
content: "";
background: var(--shadow-color);
box-shadow: 23px 0 #b6bdc9, 45px 0 #b6bdc9;
border-radius: 50%;
margin-top: -36px;
margin-left: -6px;
position: absolute;
height: 13px;
width: 13px;
}
.el-popper {
color: white !important;
}

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42
resources/dide-doc/view/icon.svg Normal file
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@ -0,0 +1,42 @@
<svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" version="1.1"
width="126px" height="126px" viewBox="-0.5 -0.5 126 126"
content="&lt;mxfile&gt;&lt;diagram id=&quot;E9SxX19eNgA6MUTyjjO6&quot; name=&quot;Icon-黑白&quot;&gt;7VnbktsoEP0aP0YlhG5+HF/GqVSS8pZrd2f3xcVIWGJXEiqEx3K+fsFCN8sXORnNuJL1g003TQN9DtDgEZzG+YKhNPxCfRyNDN3PR3A2MgzoOOJbKvaFwjDNQhEw4hcqUCtW5BtWSl1pt8THWcuQUxpxkraVHk0S7PGWDjFGd22zDY3avaYowB3FykNRV/sn8XmotMAe1xUfMQlC1bVrqAnHqDRWM8lC5NNdQwXnIzhllPKiFOdTHMnYlXHxJ7s5fqSf7OfpbvVp7cXpYv2hcPZ4S5NqCgwn/HVdw8L1C4q2Kl5qrnxfBnAXEo5XKfKkvBMcGcFJyONISEAUUZYWsG1IjkVXkw2JoimNKDs0h8YMGnAi9Bln9N8KA0ta0oQ3LDeHT2VZ1iQ0ET1PGN0mvuyg6JV5imrAFWLPAKlAvmDGcd6ghwrYAtMYc7YXJqrWtBX2JflLedegUsmPsMGiSokUfYPKdw2RKCiUbkDMfC/EYG/ERM104oLZwwXYLH1I2FyoOVYbuYaqAZ5jaFYXvVr76vDZ1+ETXsTmKDl/K5BtwIwutBUs5wELGPIJrmFWy2+4FeZobaSgVWmaq+wETGAokJx7B2koNCzrDtFw/0ejPn/eEo08X23Th+zzxPqbzBe7cGIbf/TZwAKx6adVXDrzrXI99Fy20G8J4fm9ZHzEXb17WlsnYgWHYu74eqxkdIjIVj+jZxwtaUY4oYmoeqac01jSrsw65YHpoyw8HKZSQBEJpKknYoZZm+el2wdlw2la+Eplv3EeyFxfw5FAgUk7LaIB8dYB4jhrlEUbmmKG1KBQMtySuUi23kumjLBiADA1B9quKW4jlmFDYHf4AOGJteNqVQvLccdD0QOA6/y4OZcTGdojikkkIzClMfGEvxVKMvHzZaUMVA7mdsAER2D6eIO2ER8CsOb+BU5gAIYKuvELB708RgzNAWNj7BqmZQNTh2b3THlTTJzuie6LW7wSKeMhDWiConmtbdws9DY8OCf8Sall+S9Zlsl/Ic7yRt1s3xCWmBExIbmXFrpETO6p9CqFwpVVirWrg1T6uoUOAB6a+w/yqaNOt4XmkcggHhye30e7e/FtnMnolnn4+hHGEQvwxZNZrSKJ20UKMhyJ4+Sl/TrzI4zS7309j2QiIj+nkKxqfsK1fvfH2zsh8wahPznCIR77XhuP3rnjiWtFP4juB48hnvJ+Bjzef+c6OVpriCSlLDcyi/M5SpmPVELRyriWkByk4+zmVqq8fpJylCt8P2F65xSHpmIWaN8wSClJeNbwvJSK+k4J7KNXGFuTbLR011H8bFLrenMw1mxzDAzD1R0dOJZpHVGzGOAZb6DHUKqpFemdcnFhjMfX5rEGWzdgs+22yAY7bg+rqoKl10Lzflt8s5++muuPH5bW+vf863LzT59z6h4e/K7seN/zgNV5DB/0wU+I9b+XBXj1X8Bw/h8=&lt;/diagram&gt;&lt;diagram id=&quot;2oZjiazD9LnPP1Vpl2Fo&quot; name=&quot;第 2 页&quot;&gt;5ZZdb4IwFEB/DY8m0DLQV5m6h7nEuGXPDVToVigpVXC/fkUuX+Lilui2RF+k515u29ObBgN7cbGQJI2WIqDcQGZQGPjeQAiZeKL/SrKviGU6qCKhZAGwFqzZB60TgW5ZQLNeohKCK5b2oS+ShPqqx4iUIu+nbQTvz5qSEGY0W7D2CaeDtFcWqKiiY+S2/IGyMKpnthzYcUzqZCicRSQQeQfhmYE9KYSqnuLCo7y0V3up3pt/EW0WJmmivvNCulw+b3YrwlZPycub9Tgd52oEVXaEb2HDsFi1rw1IsU0CWhaxDDzNI6boOiV+Gc31oWsWqZhDeMM49wQXUo8TkeikaaakeG/kIVuj4dLrdVCpaNFBsJUFFTFVcq9TIDqyXPAKnYVtGOftMWEMLOocUQMJtEbYFG/t6QcQ+AOZ6NdlmheS6Y57Lm2MBi4t2xm6bODFXeLzLnUVfQvQ8x5JllZXw4YVpfsji+Mj1QbC88OvyTwVuUgP20c97A572D7Rwva1OvjuBqxP/plz5/acO+YfO3dvwPngdrmidT1sP2QOsc73IJ59Ag==&lt;/diagram&gt;&lt;/mxfile&gt;">
<defs />
<g>
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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file
-- shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title : Fixed Point and Floating Point types package
--
-- Library : This package shall be compiled into a library
-- symbolically named IEEE.
--
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
--
-- Purpose : Definitions for use in fixed point and floating point
-- arithmetic packages
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package fixed_float_types is
-- Types used for generics of fixed_generic_pkg
type fixed_round_style_type is (fixed_round, fixed_truncate);
type fixed_overflow_style_type is (fixed_saturate, fixed_wrap);
-- Type used for generics of float_generic_pkg
-- These are the same as the C FE_TONEAREST, FE_UPWARD, FE_DOWNWARD,
-- and FE_TOWARDZERO floating point rounding macros.
type round_type is (round_nearest, -- Default, nearest LSB '0'
round_inf, -- Round toward positive infinity
round_neginf, -- Round toward negative infinity
round_zero); -- Round toward zero (truncate)
end package fixed_float_types;

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file
-- shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title : Fixed-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary fixed point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
package fixed_pkg is new IEEE.fixed_generic_pkg
generic map (
fixed_round_style => IEEE.fixed_float_types.fixed_round,
fixed_overflow_style => IEEE.fixed_float_types.fixed_saturate,
fixed_guard_bits => 3,
no_warning => false
);

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file
-- shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title : Floating-point package (Instantiated package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines basic binary floating point
-- : arithmetic functions
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
package float_pkg is new IEEE.float_generic_pkg
generic map (
float_exponent_width => 8, -- float32'high
float_fraction_width => 23, -- -float32'low
float_round_style => IEEE.fixed_float_types.round_nearest, -- round nearest algorithm
float_denormalize => true, -- Use IEEE extended floating
float_check_error => true, -- Turn on NAN and overflow processing
float_guard_bits => 3, -- number of guard bits
no_warning => false, -- show warnings
fixed_pkg => IEEE.fixed_pkg
);

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file
-- shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title : Standard VHDL Mathematical Packages
-- : (MATH_REAL package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE DASC VHDL Mathematical Packages Working Group
-- :
-- Purpose : This package defines a standard for designers to use in
-- : describing VHDL models that make use of common REAL
-- : constants and common REAL elementary mathematical
-- : functions.
-- :
-- Limitation: The values generated by the functions in this package
-- : may vary from platform to platform, and the precision
-- : of results is only guaranteed to be the minimum required
-- : by IEEE Std 1076-2008.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package MATH_REAL is
constant CopyRightNotice : STRING
:= "Copyright 2008 IEEE. All rights reserved.";
--
-- Constant Definitions
--
constant MATH_E : REAL := 2.71828_18284_59045_23536;
-- Value of e
constant MATH_1_OVER_E : REAL := 0.36787_94411_71442_32160;
-- Value of 1/e
constant MATH_PI : REAL := 3.14159_26535_89793_23846;
-- Value of pi
constant MATH_2_PI : REAL := 6.28318_53071_79586_47693;
-- Value of 2*pi
constant MATH_1_OVER_PI : REAL := 0.31830_98861_83790_67154;
-- Value of 1/pi
constant MATH_PI_OVER_2 : REAL := 1.57079_63267_94896_61923;
-- Value of pi/2
constant MATH_PI_OVER_3 : REAL := 1.04719_75511_96597_74615;
-- Value of pi/3
constant MATH_PI_OVER_4 : REAL := 0.78539_81633_97448_30962;
-- Value of pi/4
constant MATH_3_PI_OVER_2 : REAL := 4.71238_89803_84689_85769;
-- Value 3*pi/2
constant MATH_LOG_OF_2 : REAL := 0.69314_71805_59945_30942;
-- Natural log of 2
constant MATH_LOG_OF_10 : REAL := 2.30258_50929_94045_68402;
-- Natural log of 10
constant MATH_LOG2_OF_E : REAL := 1.44269_50408_88963_4074;
-- Log base 2 of e
constant MATH_LOG10_OF_E : REAL := 0.43429_44819_03251_82765;
-- Log base 10 of e
constant MATH_SQRT_2 : REAL := 1.41421_35623_73095_04880;
-- square root of 2
constant MATH_1_OVER_SQRT_2 : REAL := 0.70710_67811_86547_52440;
-- square root of 1/2
constant MATH_SQRT_PI : REAL := 1.77245_38509_05516_02730;
-- square root of pi
constant MATH_DEG_TO_RAD : REAL := 0.01745_32925_19943_29577;
-- Conversion factor from degree to radian
constant MATH_RAD_TO_DEG : REAL := 57.29577_95130_82320_87680;
-- Conversion factor from radian to degree
--
-- Function Declarations
--
function SIGN (X : in REAL) return REAL;
-- Purpose:
-- Returns 1.0 if X > 0.0; 0.0 if X = 0.0; -1.0 if X < 0.0
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIGN(X)) <= 1.0
-- Notes:
-- None
function CEIL (X : in REAL) return REAL;
-- Purpose:
-- Returns smallest INTEGER value (as REAL) not less than X
-- Special values:
-- None
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CEIL(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function FLOOR (X : in REAL) return REAL;
-- Purpose:
-- Returns largest INTEGER value (as REAL) not greater than X
-- Special values:
-- FLOOR(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- FLOOR(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function ROUND (X : in REAL) return REAL;
-- Purpose:
-- Rounds X to the nearest integer value (as real). If X is
-- halfway between two integers, rounding is away from 0.0
-- Special values:
-- ROUND(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ROUND(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function TRUNC (X : in REAL) return REAL;
-- Purpose:
-- Truncates X towards 0.0 and returns truncated value
-- Special values:
-- TRUNC(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- TRUNC(X) is mathematically unbounded
-- Notes:
-- a) Implementations have to support at least the domain
-- ABS(X) < REAL(INTEGER'HIGH)
function "MOD" (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns floating point modulus of X/Y, with the same sign as
-- Y, and absolute value less than the absolute value of Y, and
-- for some INTEGER value N the result satisfies the relation
-- X = Y*N + MOD(X,Y)
-- Special values:
-- None
-- Domain:
-- X in REAL; Y in REAL and Y /= 0.0
-- Error conditions:
-- Error if Y = 0.0
-- Range:
-- ABS(MOD(X,Y)) < ABS(Y)
-- Notes:
-- None
function REALMAX (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically larger of X and Y
-- Special values:
-- REALMAX(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMAX(X,Y) is mathematically unbounded
-- Notes:
-- None
function REALMIN (X, Y : in REAL) return REAL;
-- Purpose:
-- Returns the algebraically smaller of X and Y
-- Special values:
-- REALMIN(X,Y) = X when X = Y
-- Domain:
-- X in REAL; Y in REAL
-- Error conditions:
-- None
-- Range:
-- REALMIN(X,Y) is mathematically unbounded
-- Notes:
-- None
procedure UNIFORM(variable SEED1, SEED2 : inout POSITIVE; variable X : out REAL);
-- Purpose:
-- Returns, in X, a pseudo-random number with uniform
-- distribution in the open interval (0.0, 1.0).
-- Special values:
-- None
-- Domain:
-- 1 <= SEED1 <= 2147483562; 1 <= SEED2 <= 2147483398
-- Error conditions:
-- Error if SEED1 or SEED2 outside of valid domain
-- Range:
-- 0.0 < X < 1.0
-- Notes:
-- a) The semantics for this function are described by the
-- algorithm published by Pierre L'Ecuyer in "Communications
-- of the ACM," vol. 31, no. 6, June 1988, pp. 742-774.
-- The algorithm is based on the combination of two
-- multiplicative linear congruential generators for 32-bit
-- platforms.
--
-- b) Before the first call to UNIFORM, the seed values
-- (SEED1, SEED2) have to be initialized to values in the range
-- [1, 2147483562] and [1, 2147483398] respectively. The
-- seed values are modified after each call to UNIFORM.
--
-- c) This random number generator is portable for 32-bit
-- computers, and it has a period of ~2.30584*(10**18) for each
-- set of seed values.
--
-- d) For information on spectral tests for the algorithm, refer
-- to the L'Ecuyer article.
function SQRT (X : in REAL) return REAL;
-- Purpose:
-- Returns square root of X
-- Special values:
-- SQRT(0.0) = 0.0
-- SQRT(1.0) = 1.0
-- Domain:
-- X >= 0.0
-- Error conditions:
-- Error if X < 0.0
-- Range:
-- SQRT(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of SQRT is
-- approximately given by:
-- SQRT(X) <= SQRT(REAL'HIGH)
function CBRT (X : in REAL) return REAL;
-- Purpose:
-- Returns cube root of X
-- Special values:
-- CBRT(0.0) = 0.0
-- CBRT(1.0) = 1.0
-- CBRT(-1.0) = -1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- CBRT(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of CBRT is approximately given by:
-- ABS(CBRT(X)) <= CBRT(REAL'HIGH)
function "**" (X : in INTEGER; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0
-- 0**Y = 0.0; Y > 0.0
-- X**1.0 = REAL(X); X >= 0
-- 1**Y = 1.0
-- Domain:
-- X > 0
-- X = 0 for Y > 0.0
-- X < 0 for Y = 0.0
-- Error conditions:
-- Error if X < 0 and Y /= 0.0
-- Error if X = 0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function "**" (X : in REAL; Y : in REAL) return REAL;
-- Purpose:
-- Returns Y power of X ==> X**Y
-- Special values:
-- X**0.0 = 1.0; X /= 0.0
-- 0.0**Y = 0.0; Y > 0.0
-- X**1.0 = X; X >= 0.0
-- 1.0**Y = 1.0
-- Domain:
-- X > 0.0
-- X = 0.0 for Y > 0.0
-- X < 0.0 for Y = 0.0
-- Error conditions:
-- Error if X < 0.0 and Y /= 0.0
-- Error if X = 0.0 and Y <= 0.0
-- Range:
-- X**Y >= 0.0
-- Notes:
-- a) The upper bound of the reachable range for "**" is
-- approximately given by:
-- X**Y <= REAL'HIGH
function EXP (X : in REAL) return REAL;
-- Purpose:
-- Returns e**X; where e = MATH_E
-- Special values:
-- EXP(0.0) = 1.0
-- EXP(1.0) = MATH_E
-- EXP(-1.0) = MATH_1_OVER_E
-- EXP(X) = 0.0 for X <= -LOG(REAL'HIGH)
-- Domain:
-- X in REAL such that EXP(X) <= REAL'HIGH
-- Error conditions:
-- Error if X > LOG(REAL'HIGH)
-- Range:
-- EXP(X) >= 0.0
-- Notes:
-- a) The usable domain of EXP is approximately given by:
-- X <= LOG(REAL'HIGH)
function LOG (X : in REAL) return REAL;
-- Purpose:
-- Returns natural logarithm of X
-- Special values:
-- LOG(1.0) = 0.0
-- LOG(MATH_E) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG is approximately given by:
-- LOG(0+) <= LOG(X) <= LOG(REAL'HIGH)
function LOG2 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 2 of X
-- Special values:
-- LOG2(1.0) = 0.0
-- LOG2(2.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG2(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG2 is approximately given by:
-- LOG2(0+) <= LOG2(X) <= LOG2(REAL'HIGH)
function LOG10 (X : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base 10 of X
-- Special values:
-- LOG10(1.0) = 0.0
-- LOG10(10.0) = 1.0
-- Domain:
-- X > 0.0
-- Error conditions:
-- Error if X <= 0.0
-- Range:
-- LOG10(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of LOG10 is approximately given by:
-- LOG10(0+) <= LOG10(X) <= LOG10(REAL'HIGH)
function LOG (X : in REAL; BASE : in REAL) return REAL;
-- Purpose:
-- Returns logarithm base BASE of X
-- Special values:
-- LOG(1.0, BASE) = 0.0
-- LOG(BASE, BASE) = 1.0
-- Domain:
-- X > 0.0
-- BASE > 0.0
-- BASE /= 1.0
-- Error conditions:
-- Error if X <= 0.0
-- Error if BASE <= 0.0
-- Error if BASE = 1.0
-- Range:
-- LOG(X, BASE) is mathematically unbounded
-- Notes:
-- a) When BASE > 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(0+, BASE) <= LOG(X, BASE) <= LOG(REAL'HIGH, BASE)
-- b) When 0.0 < BASE < 1.0, the reachable range of LOG is
-- approximately given by:
-- LOG(REAL'HIGH, BASE) <= LOG(X, BASE) <= LOG(0+, BASE)
function SIN (X : in REAL) return REAL;
-- Purpose:
-- Returns sine of X; X in radians
-- Special values:
-- SIN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- SIN(X) = 1.0 for X = (4*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- SIN(X) = -1.0 for X = (4*k+3)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(SIN(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function COS (X : in REAL) return REAL;
-- Purpose:
-- Returns cosine of X; X in radians
-- Special values:
-- COS(X) = 0.0 for X = (2*k+1)*MATH_PI_OVER_2, where k is an
-- INTEGER
-- COS(X) = 1.0 for X = (2*k)*MATH_PI, where k is an INTEGER
-- COS(X) = -1.0 for X = (2*k+1)*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(COS(X)) <= 1.0
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function TAN (X : in REAL) return REAL;
-- Purpose:
-- Returns tangent of X; X in radians
-- Special values:
-- TAN(X) = 0.0 for X = k*MATH_PI, where k is an INTEGER
-- Domain:
-- X in REAL and
-- X /= (2*k+1)*MATH_PI_OVER_2, where k is an INTEGER
-- Error conditions:
-- Error if X = ((2*k+1) * MATH_PI_OVER_2), where k is an
-- INTEGER
-- Range:
-- TAN(X) is mathematically unbounded
-- Notes:
-- a) For larger values of ABS(X), degraded accuracy is allowed.
function ARCSIN (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse sine of X
-- Special values:
-- ARCSIN(0.0) = 0.0
-- ARCSIN(1.0) = MATH_PI_OVER_2
-- ARCSIN(-1.0) = -MATH_PI_OVER_2
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- ABS(ARCSIN(X) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCCOS (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse cosine of X
-- Special values:
-- ARCCOS(1.0) = 0.0
-- ARCCOS(0.0) = MATH_PI_OVER_2
-- ARCCOS(-1.0) = MATH_PI
-- Domain:
-- ABS(X) <= 1.0
-- Error conditions:
-- Error if ABS(X) > 1.0
-- Range:
-- 0.0 <= ARCCOS(X) <= MATH_PI
-- Notes:
-- None
function ARCTAN (Y : in REAL) return REAL;
-- Purpose:
-- Returns the value of the angle in radians of the point
-- (1.0, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0) = 0.0
-- Domain:
-- Y in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(ARCTAN(Y)) <= MATH_PI_OVER_2
-- Notes:
-- None
function ARCTAN (Y : in REAL; X : in REAL) return REAL;
-- Purpose:
-- Returns the principal value of the angle in radians of
-- the point (X, Y), which is in rectangular coordinates
-- Special values:
-- ARCTAN(0.0, X) = 0.0 if X > 0.0
-- ARCTAN(0.0, X) = MATH_PI if X < 0.0
-- ARCTAN(Y, 0.0) = MATH_PI_OVER_2 if Y > 0.0
-- ARCTAN(Y, 0.0) = -MATH_PI_OVER_2 if Y < 0.0
-- Domain:
-- Y in REAL
-- X in REAL, X /= 0.0 when Y = 0.0
-- Error conditions:
-- Error if X = 0.0 and Y = 0.0
-- Range:
-- -MATH_PI < ARCTAN(Y,X) <= MATH_PI
-- Notes:
-- None
function SINH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic sine of X
-- Special values:
-- SINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- SINH(X) is mathematically unbounded
-- Notes:
-- a) The usable domain of SINH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function COSH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic cosine of X
-- Special values:
-- COSH(0.0) = 1.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- COSH(X) >= 1.0
-- Notes:
-- a) The usable domain of COSH is approximately given by:
-- ABS(X) <= LOG(REAL'HIGH)
function TANH (X : in REAL) return REAL;
-- Purpose:
-- Returns hyperbolic tangent of X
-- Special values:
-- TANH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ABS(TANH(X)) <= 1.0
-- Notes:
-- None
function ARCSINH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic sine of X
-- Special values:
-- ARCSINH(0.0) = 0.0
-- Domain:
-- X in REAL
-- Error conditions:
-- None
-- Range:
-- ARCSINH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCSINH is approximately given by:
-- ABS(ARCSINH(X)) <= LOG(REAL'HIGH)
function ARCCOSH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic cosine of X
-- Special values:
-- ARCCOSH(1.0) = 0.0
-- Domain:
-- X >= 1.0
-- Error conditions:
-- Error if X < 1.0
-- Range:
-- ARCCOSH(X) >= 0.0
-- Notes:
-- a) The upper bound of the reachable range of ARCCOSH is
-- approximately given by: ARCCOSH(X) <= LOG(REAL'HIGH)
function ARCTANH (X : in REAL) return REAL;
-- Purpose:
-- Returns inverse hyperbolic tangent of X
-- Special values:
-- ARCTANH(0.0) = 0.0
-- Domain:
-- ABS(X) < 1.0
-- Error conditions:
-- Error if ABS(X) >= 1.0
-- Range:
-- ARCTANH(X) is mathematically unbounded
-- Notes:
-- a) The reachable range of ARCTANH is approximately given by:
-- ABS(ARCTANH(X)) < LOG(REAL'HIGH)
attribute foreign of MATH_REAL: package is "NO C code generation";
attribute foreign of sign[real return real]:function is "ieee_math_real_sign";
attribute foreign of ceil[real return real]:function is "ieee_math_real_ceil";
attribute foreign of floor[real return real]:function is "ieee_math_real_floor";
attribute foreign of trunc[real return real]:function is "ieee_math_real_trunc";
attribute foreign of round[real return real]:function is "ieee_math_real_round";
attribute foreign of "MOD"[real, real return real]:function is "ieee_math_real_mod";
attribute foreign of realmax[real, real return real]:function is "ieee_math_real_realmax";
attribute foreign of realmin[real, real return real]:function is "ieee_math_real_realmin";
attribute foreign of uniform[positive, positive,real]:procedure is "ieee_math_real_uniform";
attribute foreign of sqrt[real return real]:function is "ieee_math_real_sqrt";
attribute foreign of cbrt[real return real]:function is "ieee_math_real_cbrt";
attribute foreign of "**"[integer, real return real]:function is "ieee_math_real_pow_int";
attribute foreign of "**"[real, real return real]:function is "ieee_math_real_pow_real";
attribute foreign of exp[real return real]:function is "ieee_math_real_exp";
attribute foreign of log[real return real]:function is "ieee_math_real_log";
attribute foreign of log2[real return real]:function is "ieee_math_real_log2";
attribute foreign of log10[real return real]:function is "ieee_math_real_log10";
attribute foreign of log[real, real return real]:function is "ieee_math_real_log_base";
attribute foreign of sin[real return real]:function is "ieee_math_real_sin";
attribute foreign of cos[real return real]:function is "ieee_math_real_cos";
attribute foreign of tan[real return real]:function is "ieee_math_real_tan";
attribute foreign of arcsin[real return real]:function is "ieee_math_real_arcsin";
attribute foreign of arccos[real return real]:function is "ieee_math_real_arccos";
attribute foreign of arctan[real return real]:function is "ieee_math_real_arctan";
attribute foreign of arctan[real,real return real]:function is "ieee_math_real_arctan2";
attribute foreign of sinh[real return real]:function is "ieee_math_real_sinh";
attribute foreign of cosh[real return real]:function is "ieee_math_real_cosh";
attribute foreign of tanh[real return real]:function is "ieee_math_real_tanh";
attribute foreign of arcsinh[real return real]:function is "ieee_math_real_arcsinh";
attribute foreign of arccosh[real return real]:function is "ieee_math_real_arccosh";
attribute foreign of arctanh[real return real]:function is "ieee_math_real_arctanh";
end package MATH_REAL;

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file
-- shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
use ieee.numeric_bit.all;
package body NUMERIC_BIT_UNSIGNED is
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (L mod UNSIGNED(R));
end function "mod";
--============================================================================
-- Id: A.39
function find_leftmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: BIT_VECTOR; Y: BIT) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: BIT_VECTOR; R: NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function "?>" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?> UNSIGNED(R);
end function "?>";
-- Id: C.51
function "?>" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?> UNSIGNED(R);
end function "?>";
-- Id: C.53
function "?>" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?> R;
end function "?>";
--============================================================================
-- Id: C.55
function "?<" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?< UNSIGNED(R);
end function "?<";
-- Id: C.57
function "?<" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?< UNSIGNED(R);
end function "?<";
-- Id: C.59
function "?<" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?< R;
end function "?<";
--============================================================================
-- Id: C.61
function "?<=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.63
function "?<=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.65
function "?<=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?<= R;
end function "?<=";
--============================================================================
-- Id: C.67
function "?>=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.69
function "?>=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.71
function "?>=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?>= R;
end function "?>=";
--============================================================================
-- Id: C.73
function "?=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?= UNSIGNED(R);
end function "?=";
-- Id: C.75
function "?=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?= UNSIGNED(R);
end function "?=";
-- Id: C.77
function "?=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?= R;
end function "?=";
--============================================================================
-- Id: C.79
function "?/=" (L, R: BIT_VECTOR) return BIT is
begin
return UNSIGNED(L) ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.81
function "?/=" (L: NATURAL; R: BIT_VECTOR) return BIT is
begin
return L ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.83
function "?/=" (L: BIT_VECTOR; R: NATURAL) return BIT is
begin
return UNSIGNED(L) ?/= R;
end function "?/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (shift_left (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (shift_right (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (rotate_left (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (rotate_right (ARG => UNSIGNED(ARG),
COUNT => COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.9
function "sll" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sll COUNT);
end function "sll";
-- Id: S.11
function "srl" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) srl COUNT);
end function "srl";
-- Id: S.13
function "rol" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) rol COUNT);
end function "rol";
-- Id: S.15
function "ror" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) ror COUNT);
end function "ror";
-- Id: S.17
function "sla" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: BIT_VECTOR; COUNT: INTEGER) return BIT_VECTOR is
begin
return BIT_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (
resize (arg => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR is
begin
return BIT_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL is
begin
return TO_INTEGER (UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR is
begin
return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE));
end function To_BitVector;
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR is
begin
return BIT_VECTOR (TO_UNSIGNED(ARG, SIZE_RES'length));
end function To_BitVector;
end package body NUMERIC_BIT_UNSIGNED;

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file
-- shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_BIT_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type BIT_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the BIT_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
package NUMERIC_BIT_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2008 IEEE. All rights reserved.";
-- Id: A.3
function "+" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit bit_vector
-- Id: A.3L
function "+"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : BIT_VECTOR; R : BIT) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : BIT; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: bit_vector(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : BIT_VECTOR; Y : BIT) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : BIT_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : BIT_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : BIT_VECTOR; R : NATURAL) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : BIT_VECTOR) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : BIT_VECTOR; R : NATURAL) return BIT;
-- Result subtype: BIT
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : BIT_VECTOR; COUNT : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.9 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.9
function "sll" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.11 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.11
function "srl" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.13 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.13
function "rol" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.15 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.15
function "ror" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: ROTATE_RIGHT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : BIT_VECTOR; COUNT : INTEGER) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : BIT_VECTOR; NEW_SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : BIT_VECTOR) return BIT_VECTOR;
-- Result subtype: BIT_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : BIT_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_BitVector (ARG, SIZE : NATURAL) return BIT_VECTOR;
-- Result subtype: bit_vector(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified size.
function To_BitVector (ARG : NATURAL; SIZE_RES : BIT_VECTOR)
return BIT_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
-- begin LCS-2006-130
alias To_Bit_Vector is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, NATURAL return BIT_VECTOR];
alias To_Bit_Vector is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
alias To_BV is
To_BitVector[NATURAL, BIT_VECTOR return BIT_VECTOR];
end package NUMERIC_BIT_UNSIGNED;

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file
-- shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD_UNSIGNED package body)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the STD_ULOGIC_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library ieee;
use ieee.numeric_std.all;
package body NUMERIC_STD_UNSIGNED is
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + UNSIGNED(R));
end function "+";
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) + R);
end function "+";
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L + UNSIGNED(R));
end function "+";
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - UNSIGNED(R));
end function "-";
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) - R);
end function "-";
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L - UNSIGNED(R));
end function "-";
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * UNSIGNED(R));
end function "*";
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) * R);
end function "*";
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L * UNSIGNED(R));
end function "*";
--============================================================================
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / UNSIGNED(R));
end function "/";
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) / R);
end function "/";
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L / UNSIGNED(R));
end function "/";
--============================================================================
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem UNSIGNED(R));
end function "rem";
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) rem R);
end function "rem";
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L rem UNSIGNED(R));
end function "rem";
--============================================================================
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod UNSIGNED(R));
end function "mod";
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(L) mod R);
end function "mod";
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (L mod UNSIGNED(R));
end function "mod";
--============================================================================
-- Id: A.39
function find_leftmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_leftmost(UNSIGNED(ARG), Y);
end function find_leftmost;
-- Id: A.41
function find_rightmost (ARG: STD_ULOGIC_VECTOR; Y: STD_ULOGIC) return INTEGER is
begin
return find_rightmost(UNSIGNED(ARG), Y);
end function find_rightmost;
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) > UNSIGNED(R);
end function ">";
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L > UNSIGNED(R);
end function ">";
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) > R;
end function ">";
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) < UNSIGNED(R);
end function "<";
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L < UNSIGNED(R);
end function "<";
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) < R;
end function "<";
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) <= UNSIGNED(R);
end function "<=";
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L <= UNSIGNED(R);
end function "<=";
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) <= R;
end function "<=";
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) >= UNSIGNED(R);
end function ">=";
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L >= UNSIGNED(R);
end function ">=";
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) >= R;
end function ">=";
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end function "=";
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end function "=";
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end function "=";
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end function "/=";
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end function "/=";
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end function "/=";
--============================================================================
-- Id: C.37
function MINIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MINIMUM;
-- Id: C.39
function MINIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(L, UNSIGNED(R)));
end function MINIMUM;
-- Id: C.41
function MINIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MINIMUM(UNSIGNED(L), R));
end function MINIMUM;
--============================================================================
-- Id: C.43
function MAXIMUM (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.45
function MAXIMUM (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(L, UNSIGNED(R)));
end function MAXIMUM;
-- Id: C.47
function MAXIMUM (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (MAXIMUM(UNSIGNED(L), R));
end function MAXIMUM;
--============================================================================
-- Id: C.49
function "?>" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?> UNSIGNED(R);
end function "?>";
-- Id: C.51
function "?>" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?> UNSIGNED(R);
end function "?>";
-- Id: C.53
function "?>" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?> R;
end function "?>";
--============================================================================
-- Id: C.55
function "?<" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?< UNSIGNED(R);
end function "?<";
-- Id: C.57
function "?<" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?< UNSIGNED(R);
end function "?<";
-- Id: C.59
function "?<" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?< R;
end function "?<";
--============================================================================
-- Id: C.61
function "?<=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.63
function "?<=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?<= UNSIGNED(R);
end function "?<=";
-- Id: C.65
function "?<=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?<= R;
end function "?<=";
--============================================================================
-- Id: C.67
function "?>=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.69
function "?>=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?>= UNSIGNED(R);
end function "?>=";
-- Id: C.71
function "?>=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?>= R;
end function "?>=";
--============================================================================
-- Id: C.73
function "?=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?= UNSIGNED(R);
end function "?=";
-- Id: C.75
function "?=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?= UNSIGNED(R);
end function "?=";
-- Id: C.77
function "?=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?= R;
end function "?=";
--============================================================================
-- Id: C.79
function "?/=" (L, R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return UNSIGNED(L) ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.81
function "?/=" (L: NATURAL; R: STD_ULOGIC_VECTOR) return STD_ULOGIC is
begin
return L ?/= UNSIGNED(R);
end function "?/=";
-- Id: C.83
function "?/=" (L: STD_ULOGIC_VECTOR; R: NATURAL) return STD_ULOGIC is
begin
return UNSIGNED(L) ?/= R;
end function "?/=";
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (SHIFT_LEFT(unsigned(ARG), COUNT));
end function SHIFT_LEFT;
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (SHIFT_RIGHT(unsigned(ARG), COUNT));
end function SHIFT_RIGHT;
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (ROTATE_LEFT(unsigned(ARG), COUNT));
end function ROTATE_LEFT;
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return std_logic_vector (ROTATE_RIGHT(unsigned(ARG), COUNT));
end function ROTATE_RIGHT;
--============================================================================
-- Id: S.17
function "sla" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sla COUNT);
end function "sla";
-- Id: S.19
function "sra" (ARG: STD_ULOGIC_VECTOR; COUNT: INTEGER)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (UNSIGNED(ARG) sra COUNT);
end function "sra";
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => NEW_SIZE));
end function RESIZE;
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (
RESIZE (ARG => UNSIGNED(ARG),
NEW_SIZE => SIZE_RES'length));
end function RESIZE;
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL is
begin
return TO_INTEGER(UNSIGNED(ARG));
end function TO_INTEGER;
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdLogicVector;
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED(ARG => ARG,
SIZE => SIZE));
end function To_StdULogicVector;
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_LOGIC_VECTOR)
return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR (TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdLogicVector;
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR is
begin
return STD_ULOGIC_VECTOR (TO_UNSIGNED (ARG => ARG,
SIZE => SIZE_RES'length));
end function To_StdULogicVector;
end package body NUMERIC_STD_UNSIGNED;

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of this
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- This source file is provided on an AS IS basis. The IEEE disclaims ANY
-- WARRANTY EXPRESS OR IMPLIED INCLUDING ANY WARRANTY OF MERCHANTABILITY
-- AND FITNESS FOR USE FOR A PARTICULAR PURPOSE. The user of the source file
-- shall indemnify and hold IEEE harmless from any damages or liability
-- arising out of the use thereof.
--
-- Title : Standard VHDL Synthesis Packages
-- : (NUMERIC_STD_UNSIGNED package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Values of type STD_ULOGIC_VECTOR
-- : are interpreted as unsigned numbers in vector form.
-- : The leftmost bit is treated as the most significant bit.
-- : This package contains overloaded arithmetic operators on
-- : the STD_ULOGIC_VECTOR type. The package also contains
-- : useful type conversions functions, clock detection
-- : functions, and other utility functions.
-- :
-- : If any argument to a function is a null array, a null array
-- : is returned (exceptions, if any, are noted individually).
--
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1220 $
-- $Date: 2008-04-10 17:16:09 +0930 (Thu, 10 Apr 2008) $
-- --------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package NUMERIC_STD_UNSIGNED is
constant CopyRightNotice : STRING :=
"Copyright 2008 IEEE. All rights reserved.";
-- Id: A.3
function "+" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.3R
function "+"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.3 where R is a one bit STD_ULOGIC_VECTOR
-- Id: A.3L
function "+"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.3 where L is a one bit UNSIGNED
-- Id: A.5
function "+" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
--============================================================================
-- Id: A.9
function "-" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(MAXIMUM(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.9R
function "-"(L : STD_ULOGIC_VECTOR; R : STD_ULOGIC) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Similar to A.9 where R is a one bit UNSIGNED
-- Id: A.9L
function "-"(L : STD_ULOGIC; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Similar to A.9 where L is a one bit UNSIGNED
-- Id: A.11
function "-" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+R'LENGTH-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.17
function "*" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((L'LENGTH+L'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'LENGTH before multiplication.
-- Id: A.18
function "*" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR((R'LENGTH+R'LENGTH-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'LENGTH before multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.23
function "/" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.24
function "/" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.29
function "rem" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.30
function "rem" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.35
function "mod" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, result is truncated to L'LENGTH.
-- Id: A.36
function "mod" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, result is truncated to R'LENGTH.
--============================================================================
-- Id: A.39
function find_leftmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
-- Id: A.41
function find_rightmost (ARG : STD_ULOGIC_VECTOR; Y : STD_ULOGIC) return INTEGER;
-- Result subtype: INTEGER
-- Result: Finds the leftmost occurrence of the value of Y in ARG.
-- Returns the index of the occurrence if it exists, or -1 otherwise.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.5
function ">" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.7
function "<" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.11
function "<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.17
function "<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.23
function ">=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.25
function "=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.29
function "=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L, R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.35
function "/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
--============================================================================
-- Id: C.37
function MINIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.39
function MINIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.41
function MINIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the lesser of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.43
function MAXIMUM (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of two UNSIGNED vectors that may be
-- of different lengths.
-- Id: C.45
function MAXIMUM (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of a nonnegative INTEGER, L, and
-- an UNSIGNED vector, R.
-- Id: C.47
function MAXIMUM (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR
-- Result: Returns the greater of an UNSIGNED vector, L, and
-- a nonnegative INTEGER, R.
--============================================================================
-- Id: C.49
function "?>" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.51
function "?>" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.53
function "?>" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.55
function "?<" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.57
function "?<" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.59
function "?<" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.61
function "?<=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.63
function "?<=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.65
function "?<=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.67
function "?>=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.69
function "?>=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.71
function "?>=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.73
function "?=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.75
function "?=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.77
function "?=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Id: C.79
function "?/=" (L, R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.81
function "?/=" (L : NATURAL; R : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is a nonnegative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.83
function "?/=" (L : STD_ULOGIC_VECTOR; R : NATURAL) return STD_ULOGIC;
-- Result subtype: STD_ULOGIC
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a nonnegative INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function SHIFT_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT leftmost elements are lost.
-- Id: S.2
function SHIFT_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with '0'.
-- The COUNT rightmost elements are lost.
--============================================================================
-- Id: S.5
function ROTATE_LEFT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-left of an UNSIGNED vector COUNT times.
-- Id: S.6
function ROTATE_RIGHT (ARG : STD_ULOGIC_VECTOR; COUNT : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate-right of an UNSIGNED vector COUNT times.
--============================================================================
------------------------------------------------------------------------------
-- Note: Function S.17 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.17
function "sla" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_LEFT(ARG, COUNT)
------------------------------------------------------------------------------
-- Note: Function S.19 is not compatible with IEEE Std 1076-1987. Comment
-- out the function (declaration and body) for IEEE Std 1076-1987 compatibility.
------------------------------------------------------------------------------
-- Id: S.19
function "sra" (ARG : STD_ULOGIC_VECTOR; COUNT : INTEGER) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(ARG'LENGTH-1 downto 0)
-- Result: SHIFT_RIGHT(ARG, COUNT)
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.2
function RESIZE (ARG : STD_ULOGIC_VECTOR; NEW_SIZE : NATURAL)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(NEW_SIZE-1 downto 0)
-- Result: Resizes the UNSIGNED vector ARG to the specified size.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
function RESIZE (ARG, SIZE_RES : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR (SIZE_RES'length-1 downto 0)
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER (ARG : STD_ULOGIC_VECTOR) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.3
function To_StdLogicVector (ARG, SIZE : NATURAL) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
function To_StdLogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, NATURAL return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
-- Id: D.5
function To_StdULogicVector (ARG, SIZE : NATURAL) return STD_ULOGIC_VECTOR;
-- Result subtype: STD_ULOGIC_VECTOR(SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
function To_StdULogicVector (ARG : NATURAL; SIZE_RES : STD_ULOGIC_VECTOR)
return STD_ULOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR(SIZE_RES'length-1 downto 0)
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, NATURAL return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[NATURAL, STD_ULOGIC_VECTOR return STD_ULOGIC_VECTOR];
end package NUMERIC_STD_UNSIGNED;

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_1164 package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (PAR 1164),
-- : Accellera VHDL-TC, and IEEE P1076 Working Group
-- :
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : This package may be modified to include additional data
-- : required by tools, but it must in no way change the
-- : external interfaces or simulation behavior of the
-- : description. It is permissible to add comments and/or
-- : attributes to the package declarations, but not to change
-- : or delete any original lines of the package declaration.
-- : The package body may be changed only in accordance with
-- : the terms of Clause 16 of this standard.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1.5 $
-- $Date: 2016/04/08 07:56:22 $
-- --------------------------------------------------------------------
use STD.TEXTIO.all;
package std_logic_1164 is
-------------------------------------------------------------------
-- logic state system (unresolved)
-------------------------------------------------------------------
type STD_ULOGIC is ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak Unknown
'L', -- Weak 0
'H', -- Weak 1
'-' -- Don't care
);
-------------------------------------------------------------------
-- Directives for synthesis of std_ulogic.
-- Declare the type encoding attribute and set the value for std_ulogic
-- Directives for the resolution function and all other function are
-- in the package body
-------------------------------------------------------------------
ATTRIBUTE logic_type_encoding : string ;
ATTRIBUTE logic_type_encoding of std_ulogic:type is
-- ('U','X','0','1','Z','W','L','H','-')
('X','X','0','1','Z','X','0','1','X') ;
-------------------------------------------------------------------
-- Declare the synthesis-directive attribute; to be set on
-- basic functions that are difficult for synthesis
-------------------------------------------------------------------
ATTRIBUTE synthesis_return : string ;
ATTRIBUTE is_signed : boolean ;
-------------------------------------------------------------------
-- unconstrained array of std_ulogic for use with the resolution function
-- and for use in declaring signal arrays of unresolved elements
-------------------------------------------------------------------
type STD_ULOGIC_VECTOR is array (NATURAL range <>) of STD_ULOGIC;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
function resolved (s : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- logic state system (resolved)
-------------------------------------------------------------------
subtype STD_LOGIC is resolved STD_ULOGIC;
-- Xilinx begin (160405)
-- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
type STD_LOGIC_VECTOR_93 is array (NATURAL range <>) of STD_LOGIC ;
-- Xilinx end (160405)
-------------------------------------------------------------------
-- unconstrained array of resolved std_ulogic for use in declaring
-- signal arrays of resolved elements
-------------------------------------------------------------------
subtype STD_LOGIC_VECTOR is (resolved) STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- common subtypes
-------------------------------------------------------------------
subtype X01 is resolved STD_ULOGIC range 'X' to '1'; -- ('X','0','1')
subtype X01Z is resolved STD_ULOGIC range 'X' to 'Z'; -- ('X','0','1','Z')
subtype UX01 is resolved STD_ULOGIC range 'U' to '1'; -- ('U','X','0','1')
subtype UX01Z is resolved STD_ULOGIC range 'U' to 'Z'; -- ('U','X','0','1','Z')
-------------------------------------------------------------------
-- overloaded logical operators
-------------------------------------------------------------------
function "and" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC) return UX01;
function "not" (l : STD_ULOGIC) return UX01;
-------------------------------------------------------------------
-- vectorized overloaded logical operators
-------------------------------------------------------------------
function "and" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "not" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nand" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "or" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "nor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC_VECTOR; r : STD_ULOGIC) return STD_ULOGIC_VECTOR;
function "xnor" (l : STD_ULOGIC; r : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function "and" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nand" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "or" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "nor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
function "xnor" (l : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-------------------------------------------------------------------
-- shift operators
-------------------------------------------------------------------
function "sll" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "srl" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "rol" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
function "ror" (l : STD_ULOGIC_VECTOR; r : INTEGER) return STD_ULOGIC_VECTOR;
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
function To_bit (s : STD_ULOGIC; xmap : BIT := '0') return BIT;
function To_bitvector (s : STD_ULOGIC_VECTOR; xmap : BIT := '0') return BIT_VECTOR;
function To_StdULogic (b : BIT) return STD_ULOGIC;
function To_StdLogicVector (b : BIT_VECTOR) return STD_LOGIC_VECTOR;
function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR;
function To_StdULogicVector (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_StdULogicVector (s : STD_LOGIC_VECTOR) return STD_ULOGIC_VECTOR;
alias To_Bit_Vector is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_BV is
To_bitvector[STD_ULOGIC_VECTOR, BIT return BIT_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[BIT_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_Logic_Vector is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_SLV is
To_StdLogicVector[STD_ULOGIC_VECTOR return STD_LOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[BIT_VECTOR return STD_ULOGIC_VECTOR];
alias To_Std_ULogic_Vector is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
alias To_SULV is
To_StdULogicVector[STD_LOGIC_VECTOR return STD_ULOGIC_VECTOR];
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
function TO_01 (s : STD_ULOGIC_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : STD_ULOGIC; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function TO_01 (s : BIT_VECTOR; xmap : STD_ULOGIC := '0')
return STD_ULOGIC_VECTOR;
function TO_01 (s : BIT; xmap : STD_ULOGIC := '0')
return STD_ULOGIC;
function To_X01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (s : STD_ULOGIC) return X01;
function To_X01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01 (b : BIT) return X01;
function To_X01Z (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (s : STD_ULOGIC) return X01Z;
function To_X01Z (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_X01Z (b : BIT) return X01Z;
function To_UX01 (s : STD_ULOGIC_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (s : STD_ULOGIC) return UX01;
function To_UX01 (b : BIT_VECTOR) return STD_ULOGIC_VECTOR;
function To_UX01 (b : BIT) return UX01;
function "??" (l : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
function rising_edge (signal s : STD_ULOGIC) return BOOLEAN;
function falling_edge (signal s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
function Is_X (s : STD_ULOGIC_VECTOR) return BOOLEAN;
function Is_X (s : STD_ULOGIC) return BOOLEAN;
-------------------------------------------------------------------
-- matching relational operators
-------------------------------------------------------------------
-- the following operations are predefined
-- function "?=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?/=" (l, r : STD_ULOGIC_VECTOR) return STD_ULOGIC;
-- function "?<" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?<=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>" (l, r : STD_ULOGIC) return STD_ULOGIC;
-- function "?>=" (l, r : STD_ULOGIC) return STD_ULOGIC;
-------------------------------------------------------------------
-- string conversion and write operations
-------------------------------------------------------------------
-- the following operations are predefined
-- function to_string (value : STD_ULOGIC) return STRING;
-- function to_string (value : STD_ULOGIC_VECTOR) return STRING;
-- explicitly defined operations
alias TO_BSTRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
alias TO_BINARY_STRING is TO_STRING [STD_ULOGIC_VECTOR return STRING];
function TO_OSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_OCTAL_STRING is TO_OSTRING [STD_ULOGIC_VECTOR return STRING];
function TO_HSTRING (VALUE : STD_ULOGIC_VECTOR) return STRING;
alias TO_HEX_STRING is TO_HSTRING [STD_ULOGIC_VECTOR return STRING];
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure READ (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
procedure WRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, STD_ULOGIC_VECTOR];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, STD_ULOGIC_VECTOR];
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure OREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, STD_ULOGIC_VECTOR];
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR; GOOD : out BOOLEAN);
procedure HREAD (L : inout LINE; VALUE : out STD_ULOGIC_VECTOR);
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, STD_ULOGIC_VECTOR];
alias BWRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure OWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
procedure HWRITE (L : inout LINE; VALUE : in STD_ULOGIC_VECTOR;
JUSTIFIED : in SIDE := right; FIELD : in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
-- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
-- Xilinx begin (160405)
-- type STD_LOGIC_VECTOR_93 is array (NATURAL range <>) of STD_LOGIC ;
-- Xilinx end (160405)
-- Viper #10710: Following two are redundant. To_StdULogicVector and
-- To_StdLogicVector already declared before w.r.t. STD_LOGIC_VECTOR
-- function To_StdULogicVector (s : STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR;
-- function To_StdLogicVector (s : STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93;
FUNCTION "and" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION "nand" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION "or" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION "nor" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION "xor" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION "xnor" ( l, r : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION "not" ( l : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION To_bitvector ( s : std_logic_vector_93 ; xmap : BIT := '0') RETURN BIT_VECTOR ;
FUNCTION To_X01 ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector_93 ;
FUNCTION To_X01Z ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector_93 ;
FUNCTION To_UX01 ( s : std_logic_vector_93 ) RETURN std_logic_vector_93 ;
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector_93 ;
FUNCTION Is_X ( s : std_logic_vector_93 ) RETURN BOOLEAN ;
-- Read and Write procedures for STD_LOGIC_VECTOR_93
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93);
procedure READ(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN);
procedure WRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93);
procedure HREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN);
procedure HWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93);
procedure OREAD(L:inout LINE; VALUE:out STD_LOGIC_VECTOR_93; GOOD: out BOOLEAN);
procedure OWRITE(L:inout LINE; VALUE:in STD_LOGIC_VECTOR_93;
JUSTIFIED:in SIDE := RIGHT; FIELD:in WIDTH := 0);
-- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
end package std_logic_1164;

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-- --------------------------------------------------------------------
--
-- Copyright © 2008 by IEEE. All rights reserved.
--
-- This source file is an essential part of IEEE Std 1076-2008,
-- IEEE Standard VHDL Language Reference Manual. Verbatim copies of This
-- source file may be used and distributed without restriction.
-- Modifications to this source file as permitted in IEEE Std 1076-2008
-- may also be made and distributed. All other uses require permission
-- from the IEEE Standards Department(stds-ipr@ieee.org).
-- All other rights reserved.
--
-- Title : Standard multivalue logic package
-- : (STD_LOGIC_TEXTIO package declaration)
-- :
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: Accellera VHDL-TC and IEEE P1076 Working Group
-- :
-- Purpose : This packages is provided as a replacement for non-standard
-- : implementations of the package provided by implementers of
-- : previous versions of this standard. The declarations that
-- : appeared in those non-standard implementations appear in the
-- : package STD_LOGIC_1164 in this standard.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package.
-- :
-- --------------------------------------------------------------------
-- $Revision: 1.3 $
-- $Date: 2016/04/07 08:10:20 $
-- --------------------------------------------------------------------
library ieee ; -- RD added.
use STD.TEXTIO.all;
use IEEE.std_logic_1164.all;
PACKAGE std_logic_textio IS
alias READ is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC];
alias READ is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC, BOOLEAN];
alias READ is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC_VECTOR];
alias READ is IEEE.std_logic_1164.READ [LINE, STD_LOGIC_VECTOR_93];
alias READ is IEEE.std_logic_1164.READ [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias READ is IEEE.std_logic_1164.READ [LINE, STD_LOGIC_VECTOR_93, BOOLEAN];
alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_ULOGIC, SIDE, WIDTH];
alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias WRITE is IEEE.std_logic_1164.WRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH];
alias HREAD is IEEE.std_logic_1164.HREAD [LINE, STD_ULOGIC_VECTOR];
alias HREAD is IEEE.std_logic_1164.HREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias HWRITE is IEEE.std_logic_1164.HWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias HREAD is IEEE.std_logic_1164.HREAD [LINE, STD_LOGIC_VECTOR_93];
alias HREAD is IEEE.std_logic_1164.HREAD [LINE, STD_LOGIC_VECTOR_93, BOOLEAN];
alias HWRITE is IEEE.std_logic_1164.HWRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH];
alias OREAD is IEEE.std_logic_1164.OREAD [LINE, STD_ULOGIC_VECTOR];
alias OREAD is IEEE.std_logic_1164.OREAD [LINE, STD_ULOGIC_VECTOR, BOOLEAN];
alias OWRITE is IEEE.std_logic_1164.OWRITE [LINE, STD_ULOGIC_VECTOR, SIDE, WIDTH];
alias OREAD is IEEE.std_logic_1164.OREAD [LINE, STD_LOGIC_VECTOR_93];
alias OREAD is IEEE.std_logic_1164.OREAD [LINE, STD_LOGIC_VECTOR_93, BOOLEAN];
alias OWRITE is IEEE.std_logic_1164.OWRITE [LINE, STD_LOGIC_VECTOR_93, SIDE, WIDTH];
END PACKAGE std_logic_textio;

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-- Package env as defined by IEEE 1076-2008
package env is
procedure stop(status : integer);
procedure stop;
procedure finish(status : integer);
procedure finish;
function resolution_limit return delay_length;
end package;

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-- Package standard as defined by IEEE 1076-2008
package standard is
-- Predefined enumeration types:
type BOOLEAN is (FALSE, TRUE);
type BIT is ('0', '1');
type CHARACTER is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL,
C128, C129, C130, C131, C132, C133, C134, C135,
C136, C137, C138, C139, C140, C141, C142, C143,
C144, C145, C146, C147, C148, C149, C150, C151,
C152, C153, C154, C155, C156, C157, C158, C159,
' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
'¨', '©', 'ª', '«', '¬', '­', '®', '¯',
'°', '±', '²', '³', '´', 'µ', '', '·',
'¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ');
type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);
type INTEGER is range -2147483647 to 2147483647;
type REAL is range -1.7976931348623157e308 to 1.7976931348623157e308;
type TIME is range -9223372036854775807 to 9223372036854775807
units
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 us; -- millisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr= 60 min; -- hour
end units;
subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
impure function NOW return DELAY_LENGTH;
subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
type STRING is array (POSITIVE range <>) of CHARACTER;
type BOOLEAN_VECTOR is array (NATURAL range <>) of BOOLEAN;
type BIT_VECTOR is array (NATURAL range <>) of BIT;
type INTEGER_VECTOR is array (NATURAL range <>) of INTEGER;
type REAL_VECTOR is array (NATURAL range <>) of REAL;
type TIME_VECTOR is array (NATURAL range <>) of TIME;
type FILE_OPEN_KIND is (READ_MODE,
WRITE_MODE,
APPEND_MODE);
type FILE_OPEN_STATUS is (OPEN_OK,
STATUS_ERROR,
NAME_ERROR,
MODE_ERROR);
attribute FOREIGN: STRING;
function RISING_EDGE(signal S: BOOLEAN) return BOOLEAN;
function RISING_EDGE(signal B: BIT) return BOOLEAN;
function FALLING_EDGE(signal S: BOOLEAN) return BOOLEAN;
function FALLING_EDGE(signal B: BIT) return BOOLEAN;
end package;

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-- Package texio as defined by IEEE 1076-2008
package textio is
type LINE is access STRING;
type TEXT is file of STRING;
procedure FILE_REWIND (file F: TEXT);
function FILE_MODE (file F: TEXT) return FILE_OPEN_KIND;
function FILE_SIZE (file F: TEXT) return INTEGER;
type SIDE is (RIGHT, LEFT);
subtype WIDTH is NATURAL; -- For specifying widths of output fields.
function JUSTIFY (VALUE: STRING; JUSTIFIED: SIDE := RIGHT; FIELD: WIDTH := 0 ) return STRING;
-- Standard text files:
file INPUT: TEXT open READ_MODE is "STD_INPUT";
file OUTPUT: TEXT open WRITE_MODE is "STD_OUTPUT";
-- Input routines for standard types:
procedure READLINE (file F: TEXT; L: inout LINE);
procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out BIT);
procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out BIT_VECTOR);
procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out CHARACTER);
procedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out INTEGER);
procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out REAL);
procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out STRING);
procedure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN);
procedure READ (L: inout LINE; VALUE: out TIME);
procedure SREAD (L: inout LINE; VALUE: out STRING; STRLEN: out NATURAL);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
-- Output routines for standard types:
procedure WRITELINE (file F: TEXT; L: inout LINE);
procedure TEE (file F: TEXT; L: inout LINE);
procedure WRITE (L: inout LINE; VALUE: in BIT; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in BOOLEAN; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in CHARACTER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in INTEGER; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in REAL; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; DIGITS: in NATURAL:= 0);
procedure WRITE (L: inout LINE; VALUE: in REAL; FORMAT: in STRING);
procedure WRITE (L: inout LINE; VALUE: in STRING; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);
procedure WRITE (L: inout LINE; VALUE: in TIME; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0; UNIT: in TIME:= ns);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE := RIGHT; FIELD: in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
end package;

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package ENV is
procedure STOP (STATUS: INTEGER);
procedure STOP;
procedure FINISH (STATUS: INTEGER);
procedure FINISH;
function RESOLUTION_LIMIT return DELAY_LENGTH;
attribute foreign of ENV: package is "NO C code generation";
attribute foreign of STOP[INTEGER] : procedure is "vhdl_stop";
attribute foreign of FINISH[INTEGER] : procedure is "vhdl_finish";
attribute foreign of RESOLUTION_LIMIT : function is "vhdl_resolution_limit";
end package ENV;
package body ENV is
procedure STOP (STATUS: INTEGER) is
begin
end;
procedure STOP is
begin
stop(0);
end;
procedure FINISH (STATUS: INTEGER) is
begin
end;
procedure FINISH is
begin
finish(0);
end;
function RESOLUTION_LIMIT return DELAY_LENGTH is
begin
return 0 ns;
end;
end package body ENV;

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-- $Id: standard.vhd,v 1.1 2003/01/17 19:41:54 kumar Exp $
package STANDARD is
-- predefined enumeration types:
type BOOLEAN is (FALSE, TRUE);
type BIT is ('0', '1');
type CHARACTER is (
NUL, SOH, STX, ETX, EOT, ENQ, ACK, BEL,
BS, HT, LF, VT, FF, CR, SO, SI,
DLE, DC1, DC2, DC3, DC4, NAK, SYN, ETB,
CAN, EM, SUB, ESC, FSP, GSP, RSP, USP,
' ', '!', '"', '#', '$', '%', '&', ''',
'(', ')', '*', '+', ',', '-', '.', '/',
'0', '1', '2', '3', '4', '5', '6', '7',
'8', '9', ':', ';', '<', '=', '>', '?',
'@', 'A', 'B', 'C', 'D', 'E', 'F', 'G',
'H', 'I', 'J', 'K', 'L', 'M', 'N', 'O',
'P', 'Q', 'R', 'S', 'T', 'U', 'V', 'W',
'X', 'Y', 'Z', '[', '\', ']', '^', '_',
'`', 'a', 'b', 'c', 'd', 'e', 'f', 'g',
'h', 'i', 'j', 'k', 'l', 'm', 'n', 'o',
'p', 'q', 'r', 's', 't', 'u', 'v', 'w',
'x', 'y', 'z', '{', '|', '}', '~', DEL,
C128, C129, C130, C131, C132, C133, C134, C135,
C136, C137, C138, C139, C140, C141, C142, C143,
C144, C145, C146, C147, C148, C149, C150, C151,
C152, C153, C154, C155, C156, C157, C158, C159,
' ', '¡', '¢', '£', '¤', '¥', '¦', '§',
'¨', '©', 'ª', '«', '¬', '­', '®', '¯',
'°', '±', '²', '³', '´', 'µ', '', '·',
'¸', '¹', 'º', '»', '¼', '½', '¾', '¿',
'À', 'Á', 'Â', 'Ã', 'Ä', 'Å', 'Æ', 'Ç',
'È', 'É', 'Ê', 'Ë', 'Ì', 'Í', 'Î', 'Ï',
'Ð', 'Ñ', 'Ò', 'Ó', 'Ô', 'Õ', 'Ö', '×',
'Ø', 'Ù', 'Ú', 'Û', 'Ü', 'Ý', 'Þ', 'ß',
'à', 'á', 'â', 'ã', 'ä', 'å', 'æ', 'ç',
'è', 'é', 'ê', 'ë', 'ì', 'í', 'î', 'ï',
'ð', 'ñ', 'ò', 'ó', 'ô', 'õ', 'ö', '÷',
'ø', 'ù', 'ú', 'û', 'ü', 'ý', 'þ', 'ÿ' );
type SEVERITY_LEVEL is (NOTE, WARNING, ERROR, FAILURE);
type FILE_OPEN_KIND is (READ_MODE, WRITE_MODE, APPEND_MODE);
type FILE_OPEN_STATUS is (OPEN_OK, STATUS_ERROR, NAME_ERROR, MODE_ERROR);
-- predefined numeric types:
type INTEGER is range -2147483648 to 2147483647;
type REAL is range -1.7014111e+308 to 1.7014111e+308;
-- predefined type TIME:
type TIME is range -2147483647 to 2147483647
-- this declaration is for the convenience of the parser. Internally
-- the parser treats it as if the range were:
-- range -9223372036854775807 to 9223372036854775807
units
fs; -- femtosecond
ps = 1000 fs; -- picosecond
ns = 1000 ps; -- nanosecond
us = 1000 ns; -- microsecond
ms = 1000 us; -- millisecond
sec = 1000 ms; -- second
min = 60 sec; -- minute
hr = 60 min; -- hour
end units;
subtype DELAY_LENGTH is TIME range 0 fs to TIME'HIGH;
-- function that returns the current simulation time:
function NOW return DELAY_LENGTH;
-- predefined numeric subtypes:
subtype NATURAL is INTEGER range 0 to INTEGER'HIGH;
subtype POSITIVE is INTEGER range 1 to INTEGER'HIGH;
-- predefined array types:
type STRING is array (POSITIVE range <>) of CHARACTER;
type BIT_VECTOR is array (NATURAL range <>) of BIT;
attribute FOREIGN: STRING;
--VHDL 2008
type boolean_vector is array (natural range <>) of boolean;
type integer_vector is array (natural range <>) of integer;
type real_vector is array (natural range <>) of real;
type time_vector is array (natural range <>) of time;
end STANDARD;

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---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- This is Package TEXTIO as defined in Chapter 16.4 of the
-- IEEE Standard VHDL Language Reference Manual (IEEE Std. 1076-2008)
----------------------------------------------------------------------------
--
-- Verific : Added body/pragma's to handle file interfacing functions for synthesis
--
---------------------------------------------------------------------------
---------------------------------------------------------------------------
package TEXTIO is
-- Type definitions for Text I/O
type LINE is access string;
type TEXT is file of string;
type SIDE is (right, left);
subtype WIDTH is natural;
function JUSTIFY(VALUE: STRING;
JUSTIFIED: SIDE := RIGHT;
FIELD: WIDTH := 0) return STRING;
-- Standard Text Files
file input : TEXT open READ_MODE is "STD_INPUT";
file output : TEXT open WRITE_MODE is "STD_OUTPUT";
-- Input Routines for Standard Types
procedure READLINE(file F: TEXT; L: out LINE);
procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit);
procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out bit_vector);
procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out character);
procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out integer);
procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out real);
procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out string);
procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN);
procedure READ(L:inout LINE; VALUE: out time);
procedure SREAD (L: inout LINE; VALUE: out STRING; STRLEN: out NATURAL);
alias STRING_READ is SREAD [LINE, STRING, NATURAL];
alias BREAD is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BREAD is READ [LINE, BIT_VECTOR];
alias BINARY_READ is READ [LINE, BIT_VECTOR, BOOLEAN];
alias BINARY_READ is READ [LINE, BIT_VECTOR];
procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
procedure OREAD (L: inout LINE; VALUE: out BIT_VECTOR);
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR, BOOLEAN];
alias OCTAL_READ is OREAD [LINE, BIT_VECTOR];
procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN);
procedure HREAD (L: inout LINE; VALUE: out BIT_VECTOR);
alias HEX_READ is HREAD [LINE, BIT_VECTOR, BOOLEAN];
alias HEX_READ is HREAD [LINE, BIT_VECTOR];
-- Output Routines for Standard Types
procedure WRITELINE(file F : TEXT; L : inout LINE);
procedure tee(file F: text; L: inout line);
procedure WRITE(L : inout LINE; VALUE : in bit;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in bit_vector;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in character;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in integer;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in real;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
DIGITS: in NATURAL := 0);
procedure WRITE(L : inout LINE; VALUE : in string;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0);
procedure WRITE(L : inout LINE; VALUE : in time;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
UNIT: in TIME := ns);
alias SWRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias STRING_WRITE is WRITE [LINE, STRING, SIDE, WIDTH];
alias BWRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
alias BINARY_WRITE is WRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure OWRITE (L: inout LINE; VALUE: in BIT_VECTOR;
JUSTIFIED: in SIDE := RIGHT;
FIELD: in WIDTH := 0);
alias OCTAL_WRITE is OWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
procedure HWRITE (L: inout LINE; VALUE: in BIT_VECTOR;
JUSTIFIED: in SIDE := RIGHT;
FIELD: in WIDTH := 0);
alias HEX_WRITE is HWRITE [LINE, BIT_VECTOR, SIDE, WIDTH];
-- File Position Predicates
-- function ENDLINE(variable L : in LINE) return BOOLEAN;
-- Function ENDLINE as declared cannot be legal VHDL, and
-- the entire function was deleted from the definition
-- by the Issues Screening and Analysis Committee (ISAC),
-- a subcommittee of the VHDL Analysis and Standardization
-- Group (VASG) on 10 November, 1988. See "The Sense of
-- the VASG", October, 1989, VHDL Issue Number 0032.
-- function ENDFILE (file f: TEXT) return BOOLEAN ;
-------------------------------------------------------------------
-- Declare the textio directive attribute; to be set on
-- basic functions that have a 'builtin' implementation for elaboration
-------------------------------------------------------------------
ATTRIBUTE synthesis_return : string ;
attribute foreign of TEXTIO: package is "NO C code generation";
-- File position Predicates predicate
attribute foreign of readline:procedure is "std_textio_readline";
attribute foreign of read[LINE,BIT,BOOLEAN] :procedure is "std_textio_read1";
attribute foreign of read[LINE,BIT]:procedure is "std_textio_read2";
attribute foreign of read[LINE,BIT_VECTOR, BOOLEAN]:procedure is "std_textio_read3";
attribute foreign of read[LINE,BIT_VECTOR]:procedure is "std_textio_read4";
attribute foreign of read[LINE,BOOLEAN, BOOLEAN]:procedure is "std_textio_read5";
attribute foreign of read[LINE,BOOLEAN]:procedure is "std_textio_read6";
attribute foreign of read[LINE,CHARACTER, BOOLEAN]:procedure is "std_textio_read7";
attribute foreign of read[LINE,CHARACTER]:procedure is "std_textio_read8";
attribute foreign of read[LINE,INTEGER, BOOLEAN]:procedure is "std_textio_read9";
attribute foreign of read[LINE,INTEGER]:procedure is "std_textio_read10";
attribute foreign of read[LINE,REAL, BOOLEAN]:procedure is "std_textio_read11";
attribute foreign of read[LINE,REAL]:procedure is "std_textio_read12";
attribute foreign of read[LINE,STRING, BOOLEAN]:procedure is "std_textio_read13";
attribute foreign of read[LINE,STRING]:procedure is "std_textio_read14";
attribute foreign of read[LINE,TIME, BOOLEAN]:procedure is "std_textio_read15";
attribute foreign of read[LINE,TIME]:procedure is "std_textio_read16";
attribute foreign of writeline:procedure is "std_textio_writeline";
attribute foreign of tee:procedure is "std_textio_tee";
attribute foreign of write[LINE, BIT, SIDE, WIDTH]:procedure is "std_textio_write1";
attribute foreign of write[LINE, BIT_VECTOR, SIDE, WIDTH]:procedure is "std_textio_write2";
attribute foreign of write[LINE, BOOLEAN, SIDE, WIDTH]:procedure is "std_textio_write3";
attribute foreign of write[LINE, CHARACTER, SIDE, WIDTH]:procedure is "std_textio_write4";
attribute foreign of write[LINE, INTEGER, SIDE, WIDTH]:procedure is "std_textio_write5";
attribute foreign of write[LINE, REAL, SIDE, WIDTH, NATURAL]:procedure is "std_textio_write6";
attribute foreign of write[LINE, STRING, SIDE, WIDTH]:procedure is "std_textio_write7";
attribute foreign of write[LINE, TIME, SIDE, WIDTH, TIME]:procedure is "std_textio_write8";
end;
package body TEXTIO is
-- The subprograms declared in the TEXTIO package are
-- ignored for synthesis.
-- Assertion warnings will be generated when these
-- functions are called unconditionally.
function JUSTIFY(VALUE: STRING;
JUSTIFIED: SIDE := RIGHT;
FIELD: WIDTH := 0) return STRING is
begin
return VALUE ; -- do nothing for now
end JUSTIFY ;
procedure READLINE(file f: TEXT; L: out LINE) is
ATTRIBUTE synthesis_return OF L:variable IS "readline" ;
-- verific synthesis readline
begin
assert (FALSE)
report "Procedure call to READLINE ignored for synthesis"
severity WARNING ;
end READLINE ;
procedure READ(L:inout LINE; VALUE: out bit; GOOD : out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out bit) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out bit_vector; GOOD : out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out bit_vector) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out BOOLEAN; GOOD : out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out character; GOOD : out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out character) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out integer; GOOD : out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out integer) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out real; GOOD : out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out real) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out string; GOOD : out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out string) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out time; GOOD : out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure READ(L:inout LINE; VALUE: out time) is
ATTRIBUTE synthesis_return OF L:variable IS "read" ;
-- verific synthesis read
begin
assert (FALSE)
report "Procedure call to READ ignored for synthesis"
severity WARNING ;
end READ ;
procedure OREAD(L:inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "oread" ;
-- verific synthesis oread
begin
assert (FALSE)
report "Procedure call to OREAD ignored for synthesis"
severity WARNING ;
end OREAD ;
procedure OREAD(L:inout LINE; VALUE: out BIT_VECTOR) is
ATTRIBUTE synthesis_return OF L:variable IS "oread" ;
-- verific synthesis oread
begin
assert (FALSE)
report "Procedure call to OREAD ignored for synthesis"
severity WARNING ;
end OREAD ;
procedure HREAD(L:inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN) is
ATTRIBUTE synthesis_return OF L:variable IS "hread" ;
-- verific synthesis hread
begin
assert (FALSE)
report "Procedure call to HREAD ignored for synthesis"
severity WARNING ;
end HREAD ;
procedure HREAD(L:inout LINE; VALUE: out BIT_VECTOR) is
ATTRIBUTE synthesis_return OF L:variable IS "hread" ;
-- verific synthesis hread
begin
assert (FALSE)
report "Procedure call to HREAD ignored for synthesis"
severity WARNING ;
end HREAD ;
procedure SREAD(L:inout LINE; VALUE: out STRING; STRLEN: out NATURAL) is
ATTRIBUTE synthesis_return OF L:variable IS "sread" ;
-- verific synthesis sread
begin
assert (FALSE)
report "Procedure call to SREAD ignored for synthesis"
severity WARNING ;
end SREAD ;
procedure WRITELINE(file F : TEXT; L : inout LINE) is
ATTRIBUTE synthesis_return OF L:variable IS "writeline" ;
-- verific synthesis writeline
begin
assert (FALSE)
report "Procedure call to WRITELINE ignored for synthesis"
severity WARNING ;
end WRITELINE ;
procedure tee(file F: text; L: inout line) is
ATTRIBUTE synthesis_return OF L:variable IS "tee" ;
-- verific synthesis writeline
begin
assert (FALSE)
report "Procedure call to TEE ignored for synthesis"
severity WARNING ;
end tee;
procedure WRITE(L : inout LINE; VALUE : in bit;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "write" ;
-- verific synthesis write
begin
assert (FALSE)
report "Procedure call to WRITE ignored for synthesis"
severity WARNING ;
end WRITE ;
procedure WRITE(L : inout LINE; VALUE : in bit_vector;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "write" ;
-- verific synthesis write
begin
assert (FALSE)
report "Procedure call to WRITE ignored for synthesis"
severity WARNING ;
end WRITE ;
procedure WRITE(L : inout LINE; VALUE : in BOOLEAN;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "write" ;
-- verific synthesis write
begin
assert (FALSE)
report "Procedure call to WRITE ignored for synthesis"
severity WARNING ;
end WRITE ;
procedure WRITE(L : inout LINE; VALUE : in character;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "write" ;
-- verific synthesis write
begin
assert (FALSE)
report "Procedure call to WRITE ignored for synthesis"
severity WARNING ;
end WRITE ;
procedure WRITE(L : inout LINE; VALUE : in integer;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "write" ;
-- verific synthesis write
begin
assert (FALSE)
report "Procedure call to WRITE ignored for synthesis"
severity WARNING ;
end WRITE ;
procedure WRITE(L : inout LINE; VALUE : in real;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
DIGITS: in NATURAL := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "write" ;
-- verific synthesis write
begin
assert (FALSE)
report "Procedure call to WRITE ignored for synthesis"
severity WARNING ;
end WRITE ;
procedure WRITE(L : inout LINE; VALUE : in string;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "write" ;
-- verific synthesis write
begin
assert (FALSE)
report "Procedure call to WRITE ignored for synthesis"
severity WARNING ;
end WRITE ;
procedure WRITE(L : inout LINE; VALUE : in time;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0;
UNIT: in TIME := ns) is
ATTRIBUTE synthesis_return OF L:variable IS "write" ;
-- verific synthesis write
begin
assert (FALSE)
report "Procedure call to WRITE ignored for synthesis"
severity WARNING ;
end WRITE ;
procedure OWRITE(L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "owrite" ;
-- verific synthesis owrite
begin
assert (FALSE)
report "Procedure call to OWRITE ignored for synthesis"
severity WARNING ;
end OWRITE ;
procedure HWRITE(L : inout LINE; VALUE : in BIT_VECTOR;
JUSTIFIED: in SIDE := right;
FIELD: in WIDTH := 0) is
ATTRIBUTE synthesis_return OF L:variable IS "hwrite" ;
-- verific synthesis hwrite
begin
assert (FALSE)
report "Procedure call to HWRITE ignored for synthesis"
severity WARNING ;
end HWRITE ;
-- function ENDFILE (f: in TEXT) return BOOLEAN is
-- begin
-- assert (FALSE)
-- report "Function call to ENDFILE returns TRUE for synthesis"
-- severity WARNING ;
-- return TRUE ;
-- end ENDFILE ;
end ;

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----------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: ATTRIBUTES
--
-- Purpose: This package defines the attributes associated with
-- the Synopsys VHDL System Simulator and the HDL compiler.
-- The simulator specific attributes are built into the
-- the analyzer, so this source should not be analyzed on
-- the Synopsys VHDL System Simulator. It is provided for
-- reference and portability to other systems.
--
-- Author: JT, PH, GWH, RV
--
-- Modified. Added translate_off and translate_on pairs because
-- HDL compiler does not use/support the simulator specific attributes
-- in this package.
--
-- Modified: Apr 30, 1996, PZ: Moved the three BC attributes
-- (dont_unroll, variables, synthesis_type) to this package.
-- Modified: Nov 25, 1996, PZ: Removed the three BC attributes
-- (dont_unroll, variables, synthesis_type) from this package.
-- They are now in the behavioral package again.
--
----------------------------------------------------------------------------
-- Simulator specific attributes
-----------------------------------------------------------------------
--
-- attributes for type conversion functions, SDF backannotation and
-- resolution functions
--
-----------------------------------------------------------------------
package ATTRIBUTES is
--synopsys translate_off
attribute CLOSELY_RELATED_TCF: boolean;
attribute PROPAGATE_VALUE: string;
attribute SDT_CONDITION: string;
attribute SDT_VALUE_NAME: string;
attribute SDT_VALUE: string;
attribute REFLEXIVE: boolean;
attribute COMMUTATIVE: boolean;
attribute ASSOCIATIVE: boolean;
attribute RESULT_INITIAL_VALUE: integer;
attribute TABLE_NAME: string;
attribute REAL_NAME: string;
attribute PRIVATE: boolean;
attribute UNPRIVATE: boolean;
attribute ASIC_CELL: boolean;
attribute DIVERT_MESSAGES: boolean;
-- Note: type BUILTIN_TYPE and attributes BUILTIN and EXTRA_SPACE
-- will be phased out after Elroy. This is to move towards
-- the upcoming '92 standard.
type BUILTIN_TYPE is (VHDL_SYSTEM_PRIMITIVE, LMSI, C_BEHAVIOR,
VHDL_SYSTEM_PRIMITIVE_STD_LOGIC);
attribute BUILTIN: BUILTIN_TYPE;
attribute EXTRA_SPACE: positive;
-- Note: ### For the '92 standard, attribute FOREIGN must be
-- moved to package STANDARD.
attribute FOREIGN : STRING;
-- CLI (C Language Interface) attributes
type CLI_PIN_SENSITIVITY is (CLI_PASSIVE, CLI_EVENT, CLI_ACTIVE);
attribute CLI_ELABORATE : STRING; -- components only
attribute CLI_EVALUATE : STRING; -- components only
attribute CLI_ERROR : STRING; -- components only
attribute CLI_CLOSE : STRING; -- components only
attribute CLI_PIN : CLI_PIN_SENSITIVITY; -- components only
attribute CLI_FUNCTION : STRING; -- functions only
attribute CLI_PROCEDURE : STRING; -- procedures only
attribute CLI_POSTPONED : BOOLEAN; -- components only
-- Logic Modeling Corporation (LMC) interface attributes:
type LMSI_DELAY_TYPE_TYPE is (TYPICAL, MINIMUM, MAXIMUM);
attribute LMSI_DELAY_TYPE : LMSI_DELAY_TYPE_TYPE;
type LMSI_TIMING_MEASUREMENT_TYPE is (DISABLED, ENABLED);
attribute LMSI_TIMING_MEASUREMENT: LMSI_TIMING_MEASUREMENT_TYPE;
type LMSI_LOG_TYPE is (DISABLED, ENABLED);
attribute LMSI_LOG: LMSI_LOG_TYPE;
type LMSI_DELAY_ED_TYPE is (ENABLED, DISABLED);
attribute LMSI_DELAY: LMSI_DELAY_ED_TYPE;
type LMSI_TIMING_VIOLATIONS_TYPE is (ENABLED, DISABLED);
attribute LMSI_TIMING_VIOLATIONS: LMSI_TIMING_VIOLATIONS_TYPE;
type LMSI_XPROP_TYPE is (DISABLED, ENABLED);
attribute LMSI_XPROP: LMSI_XPROP_TYPE;
type LMSI_XPROP_METHOD_TYPE is (PREVIOUS, HIGH, LOW, FLOAT);
attribute LMSI_XPROP_METHOD: LMSI_XPROP_METHOD_TYPE;
-- Zycad XP interface attributes:
type BACKPLANE_TYPE is (XP, VERILOG, VIP);
attribute BACKPLANE: BACKPLANE_TYPE;
-- Attribute to instantiate a Model Bank component in the Zycad
-- XP box.
type ENCRYPTION_TYPE is (MODELBANK);
attribute ENCRYPTION: ENCRYPTION_TYPE;
-- Attribute to specify the EDIF file for an architecture. This
-- attribute can be specified in architecture(s) where the structural
-- information is in EDIF and we want to use it. This should be used
-- in conjunction with BACKPLANE attribute.
attribute EDIF_FILE_FOR_THIS_ARCHITECTURE: string;
attribute VERILOG_FILES_FOR_THIS_ARCHITECTURE: string;
-- The following two attributes are used to specify the physical
-- filename of the EDIF file containing the definitions of cell(s) or
-- entity(s) from a package and the EDIF library name used in the
-- above EDIF file.
attribute EDIF_LIBRARY_FILENAME: string;
attribute EDIF_LIBRARY_NAME: string;
-- XPMSW
-- XP attribute for a component which is described by a ZYCAD
-- CBMOD.
attribute ZYCAD_XP_CBMOD : BOOLEAN;
-- This attribute is used to specify the initialization file for
-- RAM(s) and ROM(s).
attribute MVL7_MEM_INITFILE: string;
-- attributes for the function units bus (funbus)
type FUNBUS_TYPE is (LAI,CBMOD);
attribute FUNBUS : FUNBUS_TYPE;
attribute CHANGE_SIMPLE_NAME : string;
attribute CHECKOUT_LICENSE : string;
attribute COMPILED_SYSTEM : boolean;
attribute USE_FULL_NAME : boolean;
attribute USE_SIMPLE_NAME : boolean;
--synopsys translate_on
--------------------------------------------------------------------
-- HDL compiler specific Attributes
attribute async_set_reset : string;
attribute sync_set_reset : string;
attribute async_set_reset_local : string;
attribute sync_set_reset_local : string;
attribute async_set_reset_local_all : string;
attribute sync_set_reset_local_all : string;
attribute one_hot : string;
attribute one_cold : string;
attribute infer_mux : string;
--------------------------------------------------------------------
-- design compiler constraints and attributes
attribute ARRIVAL : REAL;
attribute DONT_TOUCH : BOOLEAN;
attribute DONT_TOUCH_NETWORK : BOOLEAN;
attribute DRIVE_STRENGTH : REAL;
attribute EQUAL : BOOLEAN;
attribute FALL_ARRIVAL : REAL;
attribute FALL_DRIVE : REAL;
attribute LOAD : REAL;
attribute LOGIC_ONE : BOOLEAN;
attribute LOGIC_ZERO : BOOLEAN;
attribute MAX_AREA : REAL;
attribute MAX_DELAY : REAL;
attribute MAX_FALL_DELAY : REAL;
attribute MAX_RISE_DELAY : REAL;
attribute MAX_TRANSITION : REAL;
attribute MIN_DELAY : REAL;
attribute MIN_FALL_DELAY : REAL;
attribute MIN_RISE_DELAY : REAL;
attribute OPPOSITE : BOOLEAN;
attribute RISE_ARRIVAL : REAL;
attribute RISE_DRIVE : REAL;
attribute UNCONNECTED : BOOLEAN;
attribute INFER_MULTIBIT : STRING;
-- state machine attributes
attribute STATE_VECTOR : STRING;
-- resource sharing attributes
subtype resource is integer;
attribute ADD_OPS : STRING;
attribute DONT_MERGE_WITH : STRING;
attribute MAP_TO_MODULE : STRING;
attribute IMPLEMENTATION : STRING;
attribute MAY_MERGE_WITH : STRING;
attribute OPS : STRING;
-- general attributes
attribute ENUM_ENCODING : STRING;
-- optimization attributes
attribute TRANSFORM_CONST_MULT : boolean;
--
end ATTRIBUTES;

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--------------------------------------------------------------------------
--
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. All rights reserved.
--
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains this copyright notice.
--
-- Package name: std_logic_misc
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions for the Std_logic_1164 Package.
--
-- Author: GWH
--
--------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
library SYNOPSYS;
use SYNOPSYS.attributes.all;
package std_logic_misc is
-- output-strength types
type STRENGTH is (strn_X01, strn_X0H, strn_XL1, strn_X0Z, strn_XZ1,
strn_WLH, strn_WLZ, strn_WZH, strn_W0H, strn_WL1);
--synopsys synthesis_off
type MINOMAX is array (1 to 3) of TIME;
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC;
---------------------------------------------------------------------
--
-- conversion functions for STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR
--
---------------------------------------------------------------------
-- STD_ULOGIC_VECTOR is the base type of STD_LOGIC_VECTOR in 2008
-- So following function is redundant
--synopsys synthesis_on
-- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93;
function Drive (V: STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR;
-- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
--synopsys synthesis_off
attribute CLOSELY_RELATED_TCF of Drive: function is TRUE;
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC) return STD_LOGIC;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR_93;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR;
-- function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC)
-- return STD_LOGIC_VECTOR_93;
-- function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC)
-- return STD_ULOGIC_VECTOR;
--synopsys synthesis_on
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_(U)LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_(U)LOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT;
--------------------------------------------------------------------
-- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
function AND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01;
-- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01;
function fun_WiredX(Input0, Input1: std_ulogic) return STD_LOGIC;
--synopsys synthesis_on
-- Synthesis Directive Attributes
attribute IS_SIGNED : BOOLEAN ;
attribute SYNTHESIS_RETURN : STRING ;
end;
package body std_logic_misc is
--synopsys synthesis_off
type STRN_STD_ULOGIC_TABLE is array (STD_ULOGIC,STRENGTH) of STD_ULOGIC;
--------------------------------------------------------------------
--
-- Truth tables for output strength --> STD_ULOGIC lookup
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
--------------------------------------------------------------------
--
-- Truth tables for strength --> STD_ULOGIC mapping ('Z' pass through)
--
--------------------------------------------------------------------
-- truth table for output strength --> STD_ULOGIC lookup
constant tbl_STRN_STD_ULOGIC_Z: STRN_STD_ULOGIC_TABLE :=
-- ------------------------------------------------------------------
-- | X01 X0H XL1 X0Z XZ1 WLH WLZ WZH W0H WL1 | strn/ output|
-- ------------------------------------------------------------------
(('U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U'), -- | U |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | X |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | 0 |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | 1 |
('Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z', 'Z'), -- | Z |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W'), -- | W |
('0', '0', 'L', '0', 'Z', 'L', 'L', 'Z', '0', 'L'), -- | L |
('1', 'H', '1', 'Z', '1', 'H', 'Z', 'H', 'H', '1'), -- | H |
('X', 'X', 'X', 'X', 'X', 'W', 'W', 'W', 'W', 'W')); -- | - |
---------------------------------------------------------------------
--
-- functions for mapping the STD_(U)LOGIC according to STRENGTH
--
---------------------------------------------------------------------
function strength_map(input: STD_ULOGIC; strn: STRENGTH) return STD_LOGIC is
begin
return tbl_STRN_STD_ULOGIC(input, strn);
end strength_map;
function strength_map_z(input:STD_ULOGIC; strn:STRENGTH) return STD_LOGIC is
begin
return tbl_STRN_STD_ULOGIC_Z(input, strn);
end strength_map_z;
---------------------------------------------------------------------
--
-- conversion functions for STD_LOGIC_VECTOR and STD_ULOGIC_VECTOR
--
---------------------------------------------------------------------
--synopsys synthesis_on
function Drive (V: STD_LOGIC_VECTOR_93) return STD_ULOGIC_VECTOR is
-- pragma built_in SYN_FEED_THRU
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V;
--synopsys synthesis_on
-- Added Synthesis Directive
variable result : STD_ULOGIC_VECTOR(V'length-1 downto 0) ;
attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
begin
--synopsys synthesis_off
result := STD_ULOGIC_VECTOR(Value);
return result ;
--synopsys synthesis_on
end Drive;
function Drive (V: STD_ULOGIC_VECTOR) return STD_LOGIC_VECTOR_93 is
-- pragma built_in SYN_FEED_THRU
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
-- Added Synthesis Directive
variable result : STD_LOGIC_VECTOR_93(V'length-1 downto 0) ;
attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
begin
--synopsys synthesis_off
result := STD_LOGIC_VECTOR_93(Value);
return result ;
--synopsys synthesis_on
end Drive;
--synopsys synthesis_off
---------------------------------------------------------------------
--
-- conversion functions for sensing various types
--
-- (the second argument allows the user to specify the value to
-- be returned when the network is undriven)
--
---------------------------------------------------------------------
function Sense (V: STD_ULOGIC; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC is
begin
if V = 'Z' then
return vZ;
else
return V;
end if;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_LOGIC_VECTOR_93 is
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_LOGIC_VECTOR_93 (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
function Sense (V: STD_ULOGIC_VECTOR; vZ, vU, vDC: STD_ULOGIC)
return STD_ULOGIC_VECTOR is
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
begin
for i in Value'range loop
if ( Value(i) = 'Z' ) then
Result(i) := vZ;
else
Result(i) := Value(i);
end if;
end loop;
return Result;
end Sense;
-- function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC)
-- return STD_LOGIC_VECTOR_93 is
-- alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V;
-- variable Result: STD_LOGIC_VECTOR_93 (V'length-1 downto 0);
-- begin
-- for i in Value'range loop
-- if ( Value(i) = 'Z' ) then
-- Result(i) := vZ;
-- else
-- Result(i) := Value(i);
-- end if;
-- end loop;
-- return Result;
-- end Sense;
-- function Sense (V: STD_LOGIC_VECTOR_93; vZ, vU, vDC: STD_ULOGIC)
-- return STD_ULOGIC_VECTOR is
-- alias Value: STD_LOGIC_VECTOR_93 (V'length-1 downto 0) is V;
-- variable Result: STD_ULOGIC_VECTOR (V'length-1 downto 0);
-- begin
-- for i in Value'range loop
-- if ( Value(i) = 'Z' ) then
-- Result(i) := vZ;
-- else
-- Result(i) := Value(i);
-- end if;
-- end loop;
-- return Result;
-- end Sense;
---------------------------------------------------------------------
--
-- Function: STD_LOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_LOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
--synopsys synthesis_on
function STD_LOGIC_VECTORtoBIT_VECTOR (V: STD_LOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
variable Result: BIT_VECTOR (V'length-1 downto 0);
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
--synopsys synthesis_off
alias Value: STD_LOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' | 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when others =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_LOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_LOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGIC_VECTORtoBIT_VECTOR
--
-- Purpose: Conversion fun. from STD_ULOGIC_VECTOR to BIT_VECTOR
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGIC_VECTORtoBIT_VECTOR (V: STD_ULOGIC_VECTOR
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT_VECTOR is
-- pragma built_in SYN_FEED_THRU
variable Result: BIT_VECTOR (V'length-1 downto 0);
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
--synopsys synthesis_off
alias Value: STD_ULOGIC_VECTOR (V'length-1 downto 0) is V;
--synopsys synthesis_on
begin
--synopsys synthesis_off
for i in Value'range loop
case Value(i) is
when '0' | 'L' =>
Result(i) := '0';
when '1' | 'H' =>
Result(i) := '1';
when 'X' | 'W' =>
if ( Xflag ) then
Result(i) := vX;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: X --> 0"
severity WARNING;
end if;
when others =>
if ( Zflag ) then
Result(i) := vZ;
else
Result(i) := '0';
assert FALSE
report "STD_ULOGIC_VECTORtoBIT_VECTOR: Z --> 0"
severity WARNING;
end if;
end case;
end loop;
return Result;
--synopsys synthesis_on
end STD_ULOGIC_VECTORtoBIT_VECTOR;
---------------------------------------------------------------------
--
-- Function: STD_ULOGICtoBIT
--
-- Purpose: Conversion function from STD_ULOGIC to BIT
--
-- Mapping: 0, L --> 0
-- 1, H --> 1
-- X, W --> vX if Xflag is TRUE
-- X, W --> 0 if Xflag is FALSE
-- Z --> vZ if Zflag is TRUE
-- Z --> 0 if Zflag is FALSE
-- U --> vU if Uflag is TRUE
-- U --> 0 if Uflag is FALSE
-- - --> vDC if DCflag is TRUE
-- - --> 0 if DCflag is FALSE
--
---------------------------------------------------------------------
function STD_ULOGICtoBIT (V: STD_ULOGIC
--synopsys synthesis_off
; vX, vZ, vU, vDC: BIT := '0';
Xflag, Zflag, Uflag, DCflag: BOOLEAN := FALSE
--synopsys synthesis_on
) return BIT is
-- pragma built_in SYN_FEED_THRU
variable Result: BIT;
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "FEED_THROUGH" ;
begin
--synopsys synthesis_off
case V is
when '0' | 'L' =>
Result := '0';
when '1' | 'H' =>
Result := '1';
when 'X' | 'W' =>
if ( Xflag ) then
Result := vX;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: X --> 0"
severity WARNING;
end if;
when others =>
if ( Zflag ) then
Result := vZ;
else
Result := '0';
assert FALSE
report "STD_ULOGICtoBIT: Z --> 0"
severity WARNING;
end if;
end case;
return Result;
--synopsys synthesis_on
end STD_ULOGICtoBIT;
--------------------------------------------------------------------------
-- Begin: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
function AND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
variable result: STD_LOGIC;
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "REDUCE_AND" ;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
variable result: STD_LOGIC;
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "REDUCE_OR" ;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
variable result: STD_LOGIC;
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "REDUCE_XOR" ;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_LOGIC_VECTOR_93) return UX01 is
begin
return not XOR_REDUCE(ARG);
end;
function AND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
variable result: STD_LOGIC;
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "REDUCE_AND" ;
begin
result := '1';
for i in ARG'range loop
result := result and ARG(i);
end loop;
return result;
end;
function NAND_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
begin
return not AND_REDUCE(ARG);
end;
function OR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
variable result: STD_LOGIC;
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "REDUCE_OR" ;
begin
result := '0';
for i in ARG'range loop
result := result or ARG(i);
end loop;
return result;
end;
function NOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
begin
return not OR_REDUCE(ARG);
end;
function XOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
variable result: STD_LOGIC;
-- Added Synthesis Directive
attribute SYNTHESIS_RETURN of result:variable is "REDUCE_XOR" ;
begin
result := '0';
for i in ARG'range loop
result := result xor ARG(i);
end loop;
return result;
end;
function XNOR_REDUCE(ARG: STD_ULOGIC_VECTOR) return UX01 is
begin
return not XOR_REDUCE(ARG);
end;
-- End: VIPER #9548/8783: Mixed dialect: vhdl-1993 package specific additions
--synopsys synthesis_off
function fun_BUF3S(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3S: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('Z', 'Z', 'Z', 'Z'), --| 0 X01 |
('U', 'X', '0', '1')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('Z', 'Z', 'Z', 'Z'), --| 0 X0H |
('U', 'X', '0', 'H')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XL1 |
('U', 'X', 'L', '1')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('Z', 'Z', 'Z', 'Z'), --| 0 X0Z |
('U', 'X', '0', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('Z', 'Z', 'Z', 'Z'), --| 0 XZ1 |
('U', 'X', 'Z', '1')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('Z', 'Z', 'Z', 'Z'), --| 0 WLH |
('U', 'W', 'L', 'H')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('Z', 'Z', 'Z', 'Z'), --| 0 WLZ |
('U', 'W', 'L', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('Z', 'Z', 'Z', 'Z'), --| 0 WZH |
('U', 'W', 'Z', 'H')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('Z', 'Z', 'Z', 'Z'), --| 0 W0H |
('U', 'W', '0', 'H')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('Z', 'Z', 'Z', 'Z'), --| 0 WL1 |
('U', 'W', 'L', '1')));--| 1 WL1 |
begin
return tbl_BUF3S(Strn, Enable, Input);
end fun_BUF3S;
function fun_BUF3SL(Input, Enable: UX01; Strn: STRENGTH) return STD_LOGIC is
type TRISTATE_TABLE is array(STRENGTH, UX01, UX01) of STD_LOGIC;
-- truth table for tristate "buf" function (Enable active Low)
constant tbl_BUF3SL: TRISTATE_TABLE :=
-- ----------------------------------------------------
-- | Input U X 0 1 | Enable Strength |
-- ---------------------------------|-----------------|
((('U', 'U', 'U', 'U'), --| U X01 |
('U', 'X', 'X', 'X'), --| X X01 |
('U', 'X', '0', '1'), --| 0 X01 |
('Z', 'Z', 'Z', 'Z')), --| 1 X01 |
(('U', 'U', 'U', 'U'), --| U X0H |
('U', 'X', 'X', 'X'), --| X X0H |
('U', 'X', '0', 'H'), --| 0 X0H |
('Z', 'Z', 'Z', 'Z')), --| 1 X0H |
(('U', 'U', 'U', 'U'), --| U XL1 |
('U', 'X', 'X', 'X'), --| X XL1 |
('U', 'X', 'L', '1'), --| 0 XL1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XL1 |
(('U', 'U', 'U', 'Z'), --| U X0Z |
('U', 'X', 'X', 'Z'), --| X X0Z |
('U', 'X', '0', 'Z'), --| 0 X0Z |
('Z', 'Z', 'Z', 'Z')), --| 1 X0Z |
(('U', 'U', 'U', 'U'), --| U XZ1 |
('U', 'X', 'X', 'X'), --| X XZ1 |
('U', 'X', 'Z', '1'), --| 0 XZ1 |
('Z', 'Z', 'Z', 'Z')), --| 1 XZ1 |
(('U', 'U', 'U', 'U'), --| U WLH |
('U', 'W', 'W', 'W'), --| X WLH |
('U', 'W', 'L', 'H'), --| 0 WLH |
('Z', 'Z', 'Z', 'Z')), --| 1 WLH |
(('U', 'U', 'U', 'U'), --| U WLZ |
('U', 'W', 'W', 'Z'), --| X WLZ |
('U', 'W', 'L', 'Z'), --| 0 WLZ |
('Z', 'Z', 'Z', 'Z')), --| 1 WLZ |
(('U', 'U', 'U', 'U'), --| U WZH |
('U', 'W', 'W', 'W'), --| X WZH |
('U', 'W', 'Z', 'H'), --| 0 WZH |
('Z', 'Z', 'Z', 'Z')), --| 1 WZH |
(('U', 'U', 'U', 'U'), --| U W0H |
('U', 'W', 'W', 'W'), --| X W0H |
('U', 'W', '0', 'H'), --| 0 W0H |
('Z', 'Z', 'Z', 'Z')), --| 1 W0H |
(('U', 'U', 'U', 'U'), --| U WL1 |
('U', 'W', 'W', 'W'), --| X WL1 |
('U', 'W', 'L', '1'), --| 0 WL1 |
('Z', 'Z', 'Z', 'Z')));--| 1 WL1 |
begin
return tbl_BUF3SL(Strn, Enable, Input);
end fun_BUF3SL;
function fun_MUX2x1(Input0, Input1, Sel: UX01) return UX01 is
type MUX_TABLE is array (UX01, UX01, UX01) of UX01;
-- truth table for "MUX2x1" function
constant tbl_MUX2x1: MUX_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | Sel In1 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'X', '0', '1'), --| '0' 'U' |
('U', 'U', 'U', 'U')), --| '1' 'U' |
(('U', 'X', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', '1'), --| '0' 'X' |
('X', 'X', 'X', 'X')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('U', 'X', '0', '1'), --| '0' '0' |
('0', '0', '0', '0')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MUX2x1(Input1, Sel, Input0);
end fun_MUX2x1;
function fun_MAJ23(Input0, Input1, Input2: UX01) return UX01 is
type MAJ23_TABLE is array (UX01, UX01, UX01) of UX01;
----------------------------------------------------------------------------
-- The "tbl_MAJ23" truth table return 1 if the majority of three
-- inputs is 1, a 0 if the majority is 0, a X if unknown, and a U if
-- uninitialized.
----------------------------------------------------------------------------
constant tbl_MAJ23: MAJ23_TABLE :=
--------------------------------------------
--| In0 'U' 'X' '0' '1' | In1 In2 |
--------------------------------------------
((('U', 'U', 'U', 'U'), --| 'U' 'U' |
('U', 'U', 'U', 'U'), --| 'X' 'U' |
('U', 'U', '0', 'U'), --| '0' 'U' |
('U', 'U', 'U', '1')), --| '1' 'U' |
(('U', 'U', 'U', 'U'), --| 'U' 'X' |
('U', 'X', 'X', 'X'), --| 'X' 'X' |
('U', 'X', '0', 'X'), --| '0' 'X' |
('U', 'X', 'X', '1')), --| '1' 'X' |
(('U', 'U', '0', 'U'), --| 'U' '0' |
('U', 'X', '0', 'X'), --| 'X' '0' |
('0', '0', '0', '0'), --| '0' '0' |
('U', 'X', '0', '1')), --| '1' '0' |
(('U', 'U', 'U', '1'), --| 'U' '1' |
('U', 'X', 'X', '1'), --| 'X' '1' |
('U', 'X', '0', '1'), --| '0' '1' |
('1', '1', '1', '1')));--| '1' '1' |
begin
return tbl_MAJ23(Input0, Input1, Input2);
end fun_MAJ23;
function fun_WiredX(Input0, Input1: STD_ULOGIC) return STD_LOGIC is
TYPE stdlogic_table IS ARRAY(STD_ULOGIC, STD_ULOGIC) OF STD_LOGIC;
-- truth table for "WiredX" function
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ));-- | - |
-- Added Synthesis Directive
variable result : STD_LOGIC ;
attribute SYNTHESIS_RETURN of result:variable is "WIRED_THREE_STATE" ;
begin
result := resolution_table(Input0, Input1);
return result ;
end fun_WiredX;
--synopsys synthesis_on
end;

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--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_SIGNED --
-- --
-- --
-- Date: 09/11/91 KN --
-- 10/08/92 AMT change std_ulogic to signed std_logic --
-- 10/28/92 AMT added signed functions, -, ABS --
-- --
-- Purpose: --
-- A set of signed arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: Comparision of same length std_logic_vector is defined --
-- in the LRM. The interpretation is for unsigned vectors --
-- This package will "overload" that definition. --
-- --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_SIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
attribute foreign of "+"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_plus";
attribute foreign of "+"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_integer_plus";
attribute foreign of "+"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_signed_plus";
attribute foreign of "+"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_ulogic_plus";
attribute foreign of "+"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_signed_plus";
attribute foreign of "-"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_minus";
attribute foreign of "-"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_integer_minus";
attribute foreign of "-"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_signed_minus";
attribute foreign of "-"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_ulogic_minus";
attribute foreign of "-"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_signed_minus";
attribute foreign of "+"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unary_plus";
attribute foreign of "-"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_unary_minus";
attribute foreign of "*"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_signed_signed_mult";
attribute foreign of "<"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_less";
attribute foreign of "<"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_less";
attribute foreign of "<"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_less";
attribute foreign of "<="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_less_or_equal";
attribute foreign of "<="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_less_or_equal";
attribute foreign of "<="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_less_or_equal";
attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_greater";
attribute foreign of ">"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_greater";
attribute foreign of ">"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_greater";
attribute foreign of ">="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_greater_or_equal";
attribute foreign of ">="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_greater_or_equal";
attribute foreign of ">="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_greater_or_equal";
attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_equal";
attribute foreign of "="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_equal";
attribute foreign of "="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_equal";
attribute foreign of "/="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_signed_signed_is_not_equal";
attribute foreign of "/="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_signed_integer_is_not_equal";
attribute foreign of "/="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_signed_is_not_equal";
attribute foreign of conv_integer[STD_LOGIC_VECTOR return integer]:function is "std_logic_arith_conv_signed_to_integer";
attribute foreign of SHL[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_signed_shl";
attribute foreign of SHR[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_signed_shr";
end STD_LOGIC_SIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_SIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) + R; -- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + SIGNED(R); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := SIGNED(L) - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := SIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - SIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + SIGNED(L); -- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := - SIGNED(L); -- pragma label minus
return std_logic_vector(result);
end;
function "ABS"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := ABS( SIGNED(L));
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := SIGNED(L) * SIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return SIGNED(L) < SIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return SIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < SIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= SIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return SIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= SIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > SIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return SIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > SIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= SIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return SIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= SIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) = SIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return SIGNED(L) /= SIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return SIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= SIGNED(R);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(SIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(SIGNED(ARG),UNSIGNED(COUNT)));
end;
-- This function converts std_logic_vector to a signed integer value
-- using a conversion function in std_logic_arith
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : SIGNED(ARG'range);
begin
result := SIGNED(ARG);
return CONV_INTEGER(result);
end;
end STD_LOGIC_SIGNED;

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--------------------------------------------------------------------------
-- --
-- Copyright (c) 1990, 1991, 1992 by Synopsys, Inc. --
-- All rights reserved. --
-- --
-- This source file may be used and distributed without restriction --
-- provided that this copyright statement is not removed from the file --
-- and that any derivative work contains this copyright notice. --
-- --
-- Package name: STD_LOGIC_UNSIGNED --
-- --
-- --
-- Date: 09/11/92 KN --
-- 10/08/92 AMT --
-- --
-- Purpose: --
-- A set of unsigned arithemtic, conversion, --
-- and comparision functions for STD_LOGIC_VECTOR. --
-- --
-- Note: comparision of same length discrete arrays is defined --
-- by the LRM. This package will "overload" those --
-- definitions --
-- --
--------------------------------------------------------------------------
-- Modifications :
-- Attributes added for Xilinx specific optimizations
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package STD_LOGIC_UNSIGNED is
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER;
--attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "ieee_std_logic_unsigned_greater_stdv_stdv";
--attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "ieee_std_logic_unsigned_equal_stdv_stdv";
attribute foreign of "+"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_plus";
attribute foreign of "+"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_integer_plus";
attribute foreign of "+"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_unsigned_plus";
attribute foreign of "+"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_ulogic_plus";
attribute foreign of "+"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_unsigned_plus";
attribute foreign of "-"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_minus";
attribute foreign of "-"[STD_LOGIC_VECTOR, INTEGER return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_integer_minus";
attribute foreign of "-"[INTEGER, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_integer_unsigned_minus";
attribute foreign of "-"[STD_LOGIC_VECTOR, std_logic return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_ulogic_minus";
attribute foreign of "-"[std_logic, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_ulogic_unsigned_minus";
attribute foreign of "+"[STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unary_plus";
attribute foreign of "*"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return STD_LOGIC_VECTOR]:function is "std_logic_arith_unsigned_unsigned_mult";
attribute foreign of "<"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_less";
attribute foreign of "<"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_less";
attribute foreign of "<"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_less";
attribute foreign of "<="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_less_or_equal";
attribute foreign of "<="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_less_or_equal";
attribute foreign of "<="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_less_or_equal";
attribute foreign of ">"[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_greater";
attribute foreign of ">"[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_greater";
attribute foreign of ">"[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_greater";
attribute foreign of ">="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_greater_or_equal";
attribute foreign of ">="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_greater_or_equal";
attribute foreign of ">="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_greater_or_equal";
attribute foreign of "="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_equal";
attribute foreign of "="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_equal";
attribute foreign of "="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_equal";
attribute foreign of "/="[STD_LOGIC_VECTOR, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_unsigned_unsigned_is_not_equal";
attribute foreign of "/="[STD_LOGIC_VECTOR, integer return BOOLEAN]:function is "std_logic_arith_unsigned_integer_is_not_equal";
attribute foreign of "/="[integer, STD_LOGIC_VECTOR return BOOLEAN]:function is "std_logic_arith_integer_unsigned_is_not_equal";
attribute foreign of conv_integer[STD_LOGIC_VECTOR return integer]:function is "std_logic_arith_conv_unsigned_to_integer";
attribute foreign of SHL[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_unsigned_shl";
attribute foreign of SHR[std_logic_vector, std_logic_vector return std_logic_vector]:function is "std_logic_arith_unsigned_shr";
-- remove this since it is already in std_logic_arith
-- function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR;
end STD_LOGIC_UNSIGNED;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
package body STD_LOGIC_UNSIGNED is
function maximum(L, R: INTEGER) return INTEGER is
begin
if L > R then
return L;
else
return R;
end if;
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) + R;-- pragma label plus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to plus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L + UNSIGNED(R);-- pragma label plus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR (length-1 downto 0);
begin
result := UNSIGNED(L) - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: INTEGER) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R; -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: INTEGER; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC_VECTOR; R: STD_LOGIC) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := UNSIGNED(L) - R;
return std_logic_vector(result);
end;
function "-"(L: STD_LOGIC; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to minus
variable result : STD_LOGIC_VECTOR (R'range);
begin
result := L - UNSIGNED(R); -- pragma label minus
return std_logic_vector(result);
end;
function "+"(L: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable result : STD_LOGIC_VECTOR (L'range);
begin
result := + UNSIGNED(L);
return std_logic_vector(result);
end;
function "*"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
-- pragma label_applies_to mult
constant length: INTEGER := maximum(L'length, R'length);
variable result : STD_LOGIC_VECTOR ((L'length+R'length-1) downto 0);
begin
result := UNSIGNED(L) * UNSIGNED(R); -- pragma label mult
return std_logic_vector(result);
end;
function "<"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
constant length: INTEGER := maximum(L'length, R'length);
begin
return UNSIGNED(L) < UNSIGNED(R); -- pragma label lt
end;
function "<"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to lt
begin
return UNSIGNED(L) < R; -- pragma label lt
end;
function "<"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to lt
begin
return L < UNSIGNED(R); -- pragma label lt
end;
function "<="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= UNSIGNED(R); -- pragma label leq
end;
function "<="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to leq
begin
return UNSIGNED(L) <= R; -- pragma label leq
end;
function "<="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to leq
begin
return L <= UNSIGNED(R); -- pragma label leq
end;
function ">"(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > UNSIGNED(R); -- pragma label gt
end;
function ">"(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to gt
begin
return UNSIGNED(L) > R; -- pragma label gt
end;
function ">"(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to gt
begin
return L > UNSIGNED(R); -- pragma label gt
end;
function ">="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= UNSIGNED(R); -- pragma label geq
end;
function ">="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
-- pragma label_applies_to geq
begin
return UNSIGNED(L) >= R; -- pragma label geq
end;
function ">="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
-- pragma label_applies_to geq
begin
return L >= UNSIGNED(R); -- pragma label geq
end;
function "="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) = UNSIGNED(R);
end;
function "="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) = R;
end;
function "="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L = UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return UNSIGNED(L) /= UNSIGNED(R);
end;
function "/="(L: STD_LOGIC_VECTOR; R: INTEGER) return BOOLEAN is
begin
return UNSIGNED(L) /= R;
end;
function "/="(L: INTEGER; R: STD_LOGIC_VECTOR) return BOOLEAN is
begin
return L /= UNSIGNED(R);
end;
function CONV_INTEGER(ARG: STD_LOGIC_VECTOR) return INTEGER is
variable result : UNSIGNED(ARG'range);
begin
result := UNSIGNED(ARG);
return CONV_INTEGER(result);
end;
function SHL(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHL(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
function SHR(ARG:STD_LOGIC_VECTOR;COUNT: STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(SHR(UNSIGNED(ARG),UNSIGNED(COUNT)));
end;
-- remove this since it is already in std_logic_arith
--function CONV_STD_LOGIC_VECTOR(ARG: INTEGER; SIZE: INTEGER) return STD_LOGIC_VECTOR is
--variable result1 : UNSIGNED (SIZE-1 downto 0);
--variable result2 : STD_LOGIC_VECTOR (SIZE-1 downto 0);
--begin
--result1 := CONV_UNSIGNED(ARG,SIZE);
--return std_logic_vector(result1);
--end;
end STD_LOGIC_UNSIGNED;

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-------------------------------------------------------------------------------
-- Copyright (c) 1995/2015 Xilinx, Inc.
-- All Right Reserved.
-------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 2015.3
-- \ \ Description : Xilinx Functional Simulation Library Component
-- / / Macro for DSP48
-- /___/ /\ Filename : ADDMACC_MACRO.vhd
-- \ \ / \
-- \___\/\___\
--
-- Revision:
-- 04/18/08 - Initial version.
-- 04/09/15 - 852167 - align with verilog
-- End Revision
----- CELL ADDMACC_MACRO -----
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library UNISIM;
use UNISIM.vcomponents.all;
library STD;
use STD.TEXTIO.ALL;
entity ADDMACC_MACRO is
generic (
DEVICE : string := "VIRTEX6";
LATENCY : integer := 4;
WIDTH_PREADD : integer := 25;
WIDTH_MULTIPLIER : integer := 18;
WIDTH_PRODUCT : integer := 48
);
port (
PRODUCT : out std_logic_vector(WIDTH_PRODUCT-1 downto 0);
CARRYIN : in std_logic;
CE : in std_logic;
CLK : in std_logic;
MULTIPLIER : in std_logic_vector(WIDTH_MULTIPLIER-1 downto 0);
LOAD : in std_logic;
LOAD_DATA : in std_logic_vector(WIDTH_PRODUCT-1 downto 0);
PREADD1 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
PREADD2 : in std_logic_vector(WIDTH_PREADD-1 downto 0);
RST : in std_logic
);
end entity ADDMACC_MACRO;
architecture addmacc of ADDMACC_MACRO is
function CheckDevice (
device : in string
) return boolean is
variable func_val : boolean;
variable Message : LINE;
begin
if (DEVICE = "VIRTEX6" or DEVICE = "SPARTAN6" or DEVICE = "7SERIES") then
func_val := true;
else
func_val := false;
write( Message, STRING'("Illegal value of Attribute DEVICE : ") );
write ( Message, DEVICE);
write( Message, STRING'(". Legal values of this attribute are ") );
write( Message, STRING'(" VIRTEX6, SPARTAN6, 7SERIES. ") );
ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
DEALLOCATE (Message);
end if;
return func_val;
end;
function CheckWidthPreadd (
width : in integer;
device : in string
) return boolean is
variable func_val : boolean;
variable Message : LINE;
begin
if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
if (width > 0 and width <= 25) then
func_val := true;
else
func_val := false;
write( Message, STRING'("Illegal value of Attribute WIDTH_PREADD : ") );
write ( Message, WIDTH_PREADD);
write( Message, STRING'(". Legal values of this attribute are ") );
write( Message, STRING'(" 1 to 25 ") );
ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
DEALLOCATE (Message);
end if;
-- begin s1
else
if (DEVICE = "SPARTAN6" and width > 0 and width <= 18) then
func_val := true;
else
func_val := false;
write( Message, STRING'("Illegal value of Attribute WIDTH_PREADD : ") );
write ( Message, WIDTH_PREADD);
write( Message, STRING'(". Legal values of this attribute are ") );
write( Message, STRING'(" 1 to 18 ") );
ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
DEALLOCATE (Message);
end if;
-- end s1
end if;
return func_val;
end;
function GetWidthPreadd (
device : in string
) return integer is
variable func_val : integer;
variable Message : LINE;
begin
if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
func_val := 25;
else
func_val := 18;
DEALLOCATE (Message);
end if;
return func_val;
end;
function CheckWidthMult (
width : in integer
) return boolean is
variable func_val : boolean;
variable Message : LINE;
begin
if (width > 0 and width <= 18 ) then
func_val := true;
else
func_val := false;
write( Message, STRING'("Illegal value of Attribute WIDTH_MULTPLIER : ") );
write ( Message, WIDTH_MULTIPLIER);
write( Message, STRING'(". Legal values of this attribute are ") );
write( Message, STRING'(" 1 to 18 ") );
ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
DEALLOCATE (Message);
end if;
return func_val;
end;
function CheckWidthProd (
width : in integer
) return boolean is
variable func_val : boolean;
variable Message : LINE;
begin
if (width > 0 and width <= 48 ) then
func_val := true;
else
func_val := false;
write( Message, STRING'("Illegal value of Attribute WIDTH_PRODUCT : ") );
write ( Message, WIDTH_PRODUCT);
write( Message, STRING'(". Legal values of this attribute are ") );
write( Message, STRING'(" 1 to 48 ") );
ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
DEALLOCATE (Message);
end if;
return func_val;
end;
function GetABREG_IN (
latency : in integer
) return integer is
variable func_width : integer;
begin
if (LATENCY = 2 or LATENCY = 3) then
func_width := 1;
elsif (LATENCY = 4 ) then
func_width := 2;
else
func_width := 0;
end if;
return func_width;
end;
function GetABREG1_IN (
latency : in integer
) return integer is
variable func_width : integer;
begin
if (LATENCY = 2 or LATENCY = 3 or LATENCY = 4) then
func_width := 1;
else
func_width := 0;
end if;
return func_width;
end;
function GetABREG0_IN (
latency : in integer
) return integer is
variable func_width : integer;
begin
if (LATENCY = 4) then
func_width := 1;
else
func_width := 0;
end if;
return func_width;
end;
function GetMREG_IN (
latency : in integer
) return integer is
variable func_width : integer;
begin
if (LATENCY = 3 or LATENCY = 4 ) then
func_width := 1;
else
func_width := 0;
end if;
return func_width;
end;
function GetPREG_IN (
latency : in integer
) return integer is
variable func_width : integer;
variable Message : LINE;
begin
if (LATENCY = 1 or LATENCY = 2 or LATENCY = 3 or LATENCY = 4 ) then
func_width := 1;
else
func_width := 0;
write( Message, STRING'("Illegal value of Attribute LATENCY : ") );
write ( Message, LATENCY);
write( Message, STRING'(". Legal values of this attribute are ") );
write( Message, STRING'(" 1 to 4 ") );
ASSERT FALSE REPORT Message.ALL SEVERITY Failure;
DEALLOCATE (Message);
end if;
return func_width;
end;
function GetOPMODE_IN (
device : in string
) return integer is
variable func_width : integer;
begin
if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") then
func_width := 7;
elsif (DEVICE = "SPARTAN6") then
func_width := 8;
else
func_width := 8;
end if;
return func_width;
end;
--Signal Declarations:
constant OPMODE_WIDTH : integer := GetOPMODE_IN(DEVICE);
constant ChkDevice : boolean := CheckDevice(DEVICE);
constant ChkWidthPreAdd : boolean := CheckWidthPreAdd(WIDTH_PREADD, DEVICE);
constant MaxWidthPreAdd : integer := GetWidthPreAdd(DEVICE);
constant ChkWidthMult : boolean := CheckWidthMult(WIDTH_MULTIPLIER);
constant ChkWidthProd : boolean := CheckWidthProd(WIDTH_PRODUCT);
constant AREG_IN : integer := GetABREG_IN(LATENCY);
constant BREG_IN : integer := GetABREG_IN(LATENCY);
constant A0REG_IN : integer := GetABREG0_IN(LATENCY);
constant B0REG_IN : integer := GetABREG0_IN(LATENCY);
constant A1REG_IN : integer := GetABREG1_IN(LATENCY);
constant B1REG_IN : integer := GetABREG1_IN(LATENCY);
constant MREG_IN : integer := GetMREG_IN(LATENCY);
constant PREG_IN : integer := GetPREG_IN(LATENCY);
signal OPMODE_IN : std_logic_vector((OPMODE_WIDTH-1) downto 0);
signal PREADD1_IN : std_logic_vector(29 downto 0) := "000000000000000000000000000000";
signal PREADD2_IN : std_logic_vector(24 downto 0) := "0000000000000000000000000";
signal MULTIPLIER_IN : std_logic_vector(17 downto 0) := "000000000000000000";
signal LOAD_DATA_IN : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
signal RESULT_OUT : std_logic_vector(47 downto 0) := "000000000000000000000000000000000000000000000000";
signal CEA1_IN : std_logic;
signal CEA2_IN : std_logic;
signal CEB1_IN : std_logic;
signal CEB2_IN : std_logic;
-- Architecture Section: instantiation
begin
CEA1_IN <= CE when (AREG_IN = 2) else '0';
CEA2_IN <= CE when (AREG_IN = 1 or AREG_IN = 2) else '0';
CEB1_IN <= CE when (BREG_IN = 2) else '0';
CEB2_IN <= CE when (BREG_IN = 1 or BREG_IN = 2) else '0';
v : if (DEVICE = "VIRTEX5" or DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
OPMODE_IN <= "01" & LOAD & "0101";
end generate v;
s : if (DEVICE = "SPARTAN6") generate
OPMODE_IN <= "00011" & LOAD & "01";
end generate s;
load1 : if (WIDTH_PRODUCT = 48) generate
begin
LOAD_DATA_IN <= LOAD_DATA;
end generate load1;
load2 : if (WIDTH_PRODUCT < 48) generate
begin
l1: for i in 47 downto WIDTH_PRODUCT generate
LOAD_DATA_IN(i) <= '0';
end generate;
LOAD_DATA_IN(WIDTH_PRODUCT-1 downto 0) <= LOAD_DATA;
end generate load2;
pa1 : if (WIDTH_PREADD = MaxWidthPreAdd) generate
begin
PREADD1_IN(MaxWidthPreAdd-1 downto 0) <= PREADD1;
PREADD2_IN(MaxWidthPreAdd-1 downto 0) <= PREADD2;
end generate pa1;
mult1 : if (WIDTH_MULTIPLIER = 18) generate
begin
MULTIPLIER_IN <= MULTIPLIER;
end generate mult1;
pa2 : if (WIDTH_PREADD < MaxWidthPreAdd) generate
begin
pa: for i in MaxWidthPreAdd-1 downto WIDTH_PREADD generate
PREADD1_IN(i) <= PREADD1((WIDTH_PREADD-1));
PREADD2_IN(i) <= PREADD2((WIDTH_PREADD-1));
end generate;
PREADD1_IN(WIDTH_PREADD-1 downto 0) <= PREADD1;
PREADD2_IN(WIDTH_PREADD-1 downto 0) <= PREADD2;
end generate pa2;
mult2 : if (WIDTH_MULTIPLIER < 18) generate
begin
m1: for i in 17 downto WIDTH_MULTIPLIER generate
MULTIPLIER_IN(i) <= MULTIPLIER((WIDTH_MULTIPLIER-1));
end generate;
MULTIPLIER_IN(WIDTH_MULTIPLIER-1 downto 0) <= MULTIPLIER;
end generate mult2;
PRODUCT <= RESULT_OUT(WIDTH_PRODUCT-1 downto 0);
-- begin generate virtex6
bl : if (DEVICE = "VIRTEX6" or DEVICE = "7SERIES") generate
begin
DSP48E_1: DSP48E1
generic map (
ACASCREG => AREG_IN,
AREG => AREG_IN,
BCASCREG => BREG_IN,
BREG => BREG_IN,
MREG => MREG_IN,
PREG => PREG_IN,
USE_DPORT => TRUE)
port map (
ACOUT => open,
BCOUT => open,
CARRYCASCOUT => open,
CARRYOUT => open,
MULTSIGNOUT => open,
OVERFLOW => open,
P => RESULT_OUT,
PATTERNBDETECT => open,
PATTERNDETECT => open,
PCOUT => open,
UNDERFLOW => open,
A => PREADD1_IN,
ACIN => "000000000000000000000000000000",
ALUMODE => "0000",
B => MULTIPLIER_IN,
BCIN => "000000000000000000",
C => LOAD_DATA_IN,
CARRYCASCIN => '0',
CARRYIN => CARRYIN,
CARRYINSEL => "000",
CEA1 => CEA1_IN,
CEA2 => CEA2_IN,
CEAD => CE,
CEALUMODE => CE,
CEB1 => CEB1_IN,
CEB2 => CEB2_IN,
CEC => CE,
CECARRYIN => CE,
CECTRL => CE,
CED => CE,
CEINMODE => CE,
CEM => CE,
CEP => CE,
CLK => CLK,
D => PREADD2_IN,
INMODE => "00100",
MULTSIGNIN => '0',
OPMODE => OPMODE_IN,
PCIN => "000000000000000000000000000000000000000000000000",
RSTA => RST,
RSTALLCARRYIN => RST,
RSTALUMODE => RST,
RSTB => RST,
RSTC => RST,
RSTCTRL => RST,
RSTD => RST,
RSTINMODE => RST,
RSTM => RST,
RSTP => RST
);
end generate bl;
-- end generate virtex6
-- begin generate spartan6
st : if DEVICE = "SPARTAN6" generate
begin
DSP48E_2: DSP48A1
generic map (
A0REG => A0REG_IN,
A1REG => A1REG_IN,
B0REG => B0REG_IN,
B1REG => B1REG_IN,
MREG => MREG_IN,
PREG => PREG_IN )
port map (
BCOUT => open,
CARRYOUT => open,
CARRYOUTF => open,
M => open,
P => RESULT_OUT,
PCOUT => open,
A => MULTIPLIER_IN,
B => PREADD1_IN(17 downto 0),
C => LOAD_DATA_IN,
CARRYIN => CARRYIN,
CEA => CE,
CEB => CE,
CEC => CE,
CECARRYIN => '0',
CED => CE,
CEM => CE,
CEOPMODE => CE,
CEP => CE,
CLK => CLK,
D => PREADD2_IN(17 downto 0),
OPMODE => OPMODE_IN,
PCIN => "000000000000000000000000000000000000000000000000",
RSTA => RST,
RSTB => RST,
RSTC => RST,
RSTCARRYIN => RST,
RSTD => RST,
RSTM => RST,
RSTOPMODE => RST,
RSTP => RST
);
end generate st;
-- end generate spartan6
end addmacc;

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