kirigaya/digital-ide
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

update

Browse Source
This commit is contained in:
锦恢 2025-01-06 22:37:27 +08:00
parent 0321ab8a78
commit 4861410eab
4 changed files with 14 additions and 49 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
package.json
View File

@ -754,31 +754,11 @@
}
],
"editor/context": [
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.pl.setSrcTop",
"group": "navigation@1"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.pl.setSimTop",
"group": "navigation@2"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.tool.instance",
"group": "navigation@3"
},
{
"when": "editorLangId == verilog || editorLangId == systemverilog || editorLangId == vhdl",
"command": "digital-ide.tool.icarus.simulateFile",
"group": "navigation@5"
},
{
"when": "resourceLangId == vcd || resourceLangId == vcd",
"command": "digital-ide.waveviewer.show",
"group": "navigation@7"
},
{
"when": "resourceLangId == vhdl",
"command": "digital-ide.vhdl2vlog",

5
src/function/index.ts
View File

@ -59,8 +59,9 @@ function registerDocumentation(context: vscode.ExtensionContext) {
function registerSimulation(context: vscode.ExtensionContext) {
vscode.commands.registerCommand('digital-ide.tool.instance', sim.instantiation);
vscode.commands.registerCommand('digital-ide.tool.testbench', sim.testbench);
vscode.commands.registerCommand('digital-ide.tool.icarus.simulateFile', (view: ModuleDataItem) => {
sim.Icarus.simulateFile(view);
vscode.commands.registerCommand('digital-ide.tool.icarus.simulateFile', (view: ModuleDataItem) => {
const icarus = new sim.IcarusSimulate(context);
icarus.simulateFile(view);
});
}

4
src/function/sim/index.ts
View File

@ -1,9 +1,9 @@
import { instantiation } from './instance';
import { testbench } from './testbench';
import { Icarus } from './simulate';
import { IcarusSimulate } from './simulate';
export {
instantiation,
testbench,
Icarus
IcarusSimulate
};

34
src/function/sim/simulate.ts
View File

@ -12,6 +12,7 @@ import { HdlFile, HdlModule } from '../../hdlParser/core';
import { ModuleDataItem } from '../treeView/tree';
import { defaultMacro, doFastApi } from '../../hdlParser/util';
import { t } from '../../i18n';
import { openWaveViewer } from '../dide-viewer';
type Path = string;
@ -161,16 +162,17 @@ class Simulate {
* @description icarus 仿真类
*
*/
class IcarusSimulate extends Simulate {
export class IcarusSimulate extends Simulate {
os: string;
prjPath: AbsPath;
toolChain: ToolChainType;
context: vscode.ExtensionContext;
simConfig: SimulateConfig | undefined;
constructor() {
constructor(context: vscode.ExtensionContext) {
super();
this.os = opeParam.os;
this.context = context;
this.prjPath = opeParam.prjInfo.arch.prjPath;
this.toolChain = opeParam.prjInfo.toolChain;
}
@ -428,6 +430,9 @@ class IcarusSimulate extends Simulate {
const vcdPath = match[1];
const absVcdPath = hdlPath.resolve(cwd, vcdPath);
MainOutput.report(t('info.simulate.vvp.vcd-generate', absVcdPath), { level: ReportType.Finish });
if (fs.existsSync(absVcdPath)) {
openWaveViewer(this.context, vscode.Uri.file(absVcdPath));
}
} else {
MainOutput.report(line.slice(9).trim());
}
@ -506,11 +511,6 @@ class IcarusSimulate extends Simulate {
return;
}
}
public async simulateModule(hdlModule: HdlModule) {
this.simulateByHdlModule(hdlModule);
}
public async tryGetModuleFromView(view: ModuleDataItem): Promise<HdlModule | undefined> {
if (view.path) {
@ -570,20 +570,4 @@ class IcarusSimulate extends Simulate {
return;
}
}
}
const icarus = new IcarusSimulate();
namespace Icarus {
export async function simulateModule(hdlModule: HdlModule) {
await icarus.simulateModule(hdlModule);
}
export async function simulateFile(view: ModuleDataItem) {
await icarus.simulateFile(view);
}
};
export {
Icarus
};
}