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锦恢 2025-03-02 23:43:58 +08:00
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4
README.md
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@ -4,11 +4,7 @@
## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development ## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development
<<<<<<< HEAD
[Document (New)](https://nc-ai.cn/) | [中文文档 (New)](https://nc-ai.cn/zh/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
=======
[Document (New)](https://nc-ai.cn/en/) | [中文文档 (New)](https://nc-ai.cn/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0) [Document (New)](https://nc-ai.cn/en/) | [中文文档 (New)](https://nc-ai.cn/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
>>>>>>> 3838196cca3b041f9324ef7788847a91d45658b6
![](https://img.shields.io/badge/version-0.4.0-purple) ![](https://img.shields.io/badge/version-0.4.0-purple)
![](https://img.shields.io/badge/Verilog-support-green) ![](https://img.shields.io/badge/Verilog-support-green)

120
design/lsp.drawio
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@ -1,120 +0,0 @@
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package-lock.json generated
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7
package.json
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@ -4,12 +4,12 @@
"description": "all in one vscode plugin for Verilog/VHDL development", "description": "all in one vscode plugin for Verilog/VHDL development",
"publisher": "sterben", "publisher": "sterben",
"homepage": "https://digital-eda.github.io/DIDE-doc-Cn", "homepage": "https://digital-eda.github.io/DIDE-doc-Cn",
"version": "0.4.0", "version": "0.4.1",
"main": "./out/extension", "main": "./out/extension",
"l10n": "./l10n", "l10n": "./l10n",
"icon": "images/icon.png", "icon": "images/icon.png",
"engines": { "engines": {
"vscode": "^1.94.0" "vscode": "^1.89.0"
}, },
"keywords": [ "keywords": [
"FPGA Develop Support", "FPGA Develop Support",
@ -1267,6 +1267,7 @@
"dependencies": { "dependencies": {
"axios": "^1.7.7", "axios": "^1.7.7",
"bson": "^6.8.0", "bson": "^6.8.0",
"bufferutil": "^4.0.9",
"chokidar": "^4.0.1", "chokidar": "^4.0.1",
"minimatch": "^10.0.1", "minimatch": "^10.0.1",
"pako": "^2.1.0", "pako": "^2.1.0",
@ -1275,10 +1276,12 @@
"state-machine-cat": "^9.2.5", "state-machine-cat": "^9.2.5",
"tar": "^7.4.3", "tar": "^7.4.3",
"temp": "^0.9.4", "temp": "^0.9.4",
"utf-8-validate": "^5.0.10",
"vscode-jsonrpc": "^8.2.1", "vscode-jsonrpc": "^8.2.1",
"vscode-languageclient": "^9.0.1", "vscode-languageclient": "^9.0.1",
"vscode-textmate": "^9.0.0", "vscode-textmate": "^9.0.0",
"wavedrom": "^2.9.1", "wavedrom": "^2.9.1",
"webpack": "^5.98.0",
"zlib": "^1.0.5" "zlib": "^1.0.5"
} }
} }

3
project/property-schema.json
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@ -198,8 +198,7 @@
"xc7a35tftg256-1", "xc7a35tftg256-1",
"xc7a35tcsg324-1", "xc7a35tcsg324-1",
"xc7z035ffg676-2", "xc7z035ffg676-2",
"xc7z020clg484-1", "xc7z020clg484-1"
"hello-world"
] ]
} }
}, },

2
scripts/README.md
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@ -15,5 +15,5 @@ $ npm install vsce -g
``` ```
```bash ```bash
$ python script/command/make_package.py $ python scripts/command/make_package.py
``` ```

8
scripts/command/make_package.py
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@ -64,7 +64,7 @@ def modify_vsix():
os.remove(dist_path) os.remove(dist_path)
# move public # move public
copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public')) # copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public'))
# webview # webview
copy_dir('./resources/dide-netlist/view', os.path.join(extract_folder, 'extension', 'resources', 'dide-netlist', 'view')) copy_dir('./resources/dide-netlist/view', os.path.join(extract_folder, 'extension', 'resources', 'dide-netlist', 'view'))
@ -100,8 +100,8 @@ pipe.add_command('compile typescript', 'tsc -p ./ --outDir out-js')
pipe.add_command('webpack', 'webpack --mode production') pipe.add_command('webpack', 'webpack --mode production')
pipe.add_command('make vsix installer', 'vsce package') pipe.add_command('make vsix installer', 'vsce package')
pipe.add_command('modify vsix installer', lambda : modify_vsix()) pipe.add_command('modify vsix installer', lambda : modify_vsix())
pipe.add_command('remove out-js', lambda : remove_folder('out-js')) # pipe.add_command('remove out-js', lambda : remove_folder('out-js'))
pipe.add_command('remove out', lambda : remove_folder('out')) # pipe.add_command('remove out', lambda : remove_folder('out'))
pipe.add_command('install', lambda : install_extension()) # pipe.add_command('install', lambda : install_extension())
pipe.run() pipe.run()

2
scripts/command/pull-digital-lsp.py
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@ -4,7 +4,7 @@ import os
import argparse import argparse
parser = argparse.ArgumentParser() parser = argparse.ArgumentParser()
parser.add_argument('--version', default='0.4.0') parser.add_argument('--version', default='0.4.1')
args = parser.parse_args() args = parser.parse_args()
version_string = args.version version_string = args.version

4
src/function/sim/simulate.ts
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@ -302,8 +302,8 @@ export class IcarusSimulate extends Simulate {
command += ' ' + extaArgs; command += ' ' + extaArgs;
} }
const parent = fspath.dirname(path); // const parent = fspath.dirname(path);
command += ' ' + '-I"' + parent + '"'; // command += ' ' + '-I "' + parent + '"';
return command; return command;
} }

2
syntaxes/systemverilog.json
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@ -172,7 +172,7 @@
"keywords": { "keywords": {
"patterns": [ "patterns": [
{ {
"match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case(xz)?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|output|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor)\\b", "match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case(xz)?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|output|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor|logic)\\b",
"name": "keyword.other.verilog" "name": "keyword.other.verilog"
}, },
{ {