0.4.x package test
This commit is contained in:
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49ca4653da
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@ -4,11 +4,7 @@
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## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development
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<<<<<<< HEAD
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[Document (New)](https://nc-ai.cn/) | [中文文档 (New)](https://nc-ai.cn/zh/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
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=======
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[Document (New)](https://nc-ai.cn/en/) | [中文文档 (New)](https://nc-ai.cn/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
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>>>>>>> 3838196cca3b041f9324ef7788847a91d45658b6
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@ -1,120 +0,0 @@
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<mxfile host="65bd71144e">
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<diagram id="Jyg0ghsg0WSuYoSyPP-c" name="linter">
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<mxGraphModel dx="868" dy="626" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="1" pageScale="1" pageWidth="827" pageHeight="1169" math="0" shadow="0">
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</diagram>
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</mxfile>
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1225
package-lock.json
generated
1225
package-lock.json
generated
File diff suppressed because it is too large
Load Diff
@ -4,12 +4,12 @@
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"description": "all in one vscode plugin for Verilog/VHDL development",
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"publisher": "sterben",
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"homepage": "https://digital-eda.github.io/DIDE-doc-Cn",
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"version": "0.4.0",
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"version": "0.4.1",
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"main": "./out/extension",
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"l10n": "./l10n",
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"icon": "images/icon.png",
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"engines": {
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"vscode": "^1.94.0"
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"vscode": "^1.89.0"
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},
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"keywords": [
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"FPGA Develop Support",
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@ -1267,6 +1267,7 @@
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"dependencies": {
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"axios": "^1.7.7",
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"bson": "^6.8.0",
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"bufferutil": "^4.0.9",
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"chokidar": "^4.0.1",
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"minimatch": "^10.0.1",
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"pako": "^2.1.0",
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"state-machine-cat": "^9.2.5",
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"tar": "^7.4.3",
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"temp": "^0.9.4",
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"utf-8-validate": "^5.0.10",
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"vscode-jsonrpc": "^8.2.1",
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"vscode-languageclient": "^9.0.1",
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"vscode-textmate": "^9.0.0",
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"wavedrom": "^2.9.1",
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"webpack": "^5.98.0",
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"zlib": "^1.0.5"
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}
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}
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"xc7a35tftg256-1",
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"xc7a35tcsg324-1",
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"xc7z035ffg676-2",
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"xc7z020clg484-1",
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"hello-world"
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"xc7z020clg484-1"
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]
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}
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},
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@ -15,5 +15,5 @@ $ npm install vsce -g
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```
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```bash
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$ python script/command/make_package.py
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$ python scripts/command/make_package.py
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```
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@ -64,7 +64,7 @@ def modify_vsix():
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os.remove(dist_path)
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# move public
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copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public'))
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# copy_dir('./resources/public', os.path.join(extract_folder, 'extension', 'resources', 'public'))
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# webview
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copy_dir('./resources/dide-netlist/view', os.path.join(extract_folder, 'extension', 'resources', 'dide-netlist', 'view'))
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@ -100,8 +100,8 @@ pipe.add_command('compile typescript', 'tsc -p ./ --outDir out-js')
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pipe.add_command('webpack', 'webpack --mode production')
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pipe.add_command('make vsix installer', 'vsce package')
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pipe.add_command('modify vsix installer', lambda : modify_vsix())
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pipe.add_command('remove out-js', lambda : remove_folder('out-js'))
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pipe.add_command('remove out', lambda : remove_folder('out'))
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pipe.add_command('install', lambda : install_extension())
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# pipe.add_command('remove out-js', lambda : remove_folder('out-js'))
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# pipe.add_command('remove out', lambda : remove_folder('out'))
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# pipe.add_command('install', lambda : install_extension())
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pipe.run()
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@ -4,7 +4,7 @@ import os
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import argparse
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parser = argparse.ArgumentParser()
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parser.add_argument('--version', default='0.4.0')
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parser.add_argument('--version', default='0.4.1')
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args = parser.parse_args()
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version_string = args.version
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@ -302,8 +302,8 @@ export class IcarusSimulate extends Simulate {
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command += ' ' + extaArgs;
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}
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const parent = fspath.dirname(path);
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command += ' ' + '-I"' + parent + '"';
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// const parent = fspath.dirname(path);
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// command += ' ' + '-I "' + parent + '"';
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return command;
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}
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@ -172,7 +172,7 @@
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"keywords": {
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"patterns": [
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{
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"match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case(xz)?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|output|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor)\\b",
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"match": "\\b(always|and|assign|attribute|begin|buf|bufif0|bufif1|case(xz)?|cmos|deassign|default|defparam|disable|edge|else|end(attribute|case|function|generate|module|primitive|specify|table|task)?|event|for|force|forever|fork|function|generate|genvar|highz(01)|if(none)?|initial|inout|input|output|integer|join|localparam|medium|module|large|macromodule|nand|negedge|nmos|nor|not|notif(01)|or|parameter|pmos|posedge|primitive|pull0|pull1|pulldown|pullup|rcmos|real|realtime|reg|release|repeat|rnmos|rpmos|rtran|rtranif(01)|scalared|signed|small|specify|specparam|strength|strong0|strong1|supply0|supply1|table|task|time|tran|tranif(01)|tri(01)?|tri(and|or|reg)|unsigned|vectored|wait|wand|weak(01)|while|wire|wor|xnor|xor|logic)\\b",
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"name": "keyword.other.verilog"
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},
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{
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