Merge branch 'main' of https://github.com/Digital-EDA/Digital-IDE

package.nls.json

@@ -6,7 +6,7 @@
     "digital-ide.hdlDoc.showWebview.title": "Show the document of current file in a webview",
     "digital-ide.tool.instance.title": "Generate instance template from selected module",
     "digital-ide.tool.testbench.title": "Generate testbench template from current file",
-    "digital-ide.tool.icarus.simulateFile.title": "Do simulation for current file",
+    "digital-ide.tool.icarus.simulateFile.title": "Do simulation for current module",
     "digital-ide.treeView.arch.expand.title": "Expand all the items in tree view",
     "digital-ide.treeView.arch.collapse.title": "Collapse all the items in tree view",
     "digital-ide.treeView.arch.refresh.title": "Refresh the tree view",

package.nls.zh-cn.json

@@ -6,7 +6,7 @@
     "digital-ide.hdlDoc.showWebview.title": "在 webview 中展示文档",
     "digital-ide.tool.instance.title": "生成选中 module 的例化模板",
     "digital-ide.tool.testbench.title": "从当前文件中选择 module 生成 testbench",
-    "digital-ide.tool.icarus.simulateFile.title": "对当前文件进行仿真",
+    "digital-ide.tool.icarus.simulateFile.title": "对当前模块进行仿真",
     "digital-ide.treeView.arch.expand.title": "展开视图中的所有项目",
     "digital-ide.treeView.arch.collapse.title": "收起视图中的所有项目",
     "digital-ide.treeView.arch.refresh.title": "刷新树视图",

package.nls.zh-tw.json

@@ -6,7 +6,7 @@
     "digital-ide.hdlDoc.showWebview.title": "在 webview 中展示文檔",
     "digital-ide.tool.instance.title": "生成選中 module 的例化模板",
     "digital-ide.tool.testbench.title": "從當前文件中選擇 module 生成 testbench",
-    "digital-ide.tool.icarus.simulateFile.title": "對當前文件進行仿真",
+    "digital-ide.tool.icarus.simulateFile.title": "對當前文模块進行仿真",
     "digital-ide.treeView.arch.expand.title": "展開視圖中的所有項目",
     "digital-ide.treeView.arch.collapse.title": "收起視圖中的所有項目",
     "digital-ide.treeView.arch.refresh.title": "刷新樹視圖",

project/property-schema.json

@@ -200,22 +200,7 @@
 				"xc7z035ffg676-2",
 				"xc7z020clg484-1"
 			]
-		},
+		}
-        "iverilogCompileOptions": {
-            "type": "object",
-            "description": "options to define iverilog arguments",
-            "properties": {
-                "standard": {
-                    "type": "string",
-                    "description": "value of argument -g, default is -g2012",
-                    "default": "2012"
-                },
-                "includes": {
-                    "type": "array",
-                    "description": "value of argument -I"
-                }
-            }
-        }
 	},
 	"required": [
 		"toolChain",

snippets/svlog.json

@@ -278,7 +278,7 @@
             "    output [OWIDTH - 1 : 0] ${4:data_o}",
             ");",
             "    $5",
-            "endmodule  //$1\n"
+            "endmodule"
         ],
         "description": "Insert a module with parameter"
     },

src/function/dide-netlist/api.ts

@@ -125,7 +125,7 @@ export async function gotoDefinition(data: any, panel: vscode.WebviewPanel) {
         const uri = vscode.Uri.file(getRealPath(path));
         await vscode.commands.executeCommand('vscode.open', uri, {
             selection: new vscode.Range(
-                new vscode.Position(range.start.line, range.end.character),
+                new vscode.Position(range.start.line, range.start.character),
                 new vscode.Position(range.end.line, range.end.character)
             )
         });

src/function/sim/simulate.ts

@@ -189,7 +189,6 @@ class IcarusSimulate extends Simulate {
 
     /**
      * @description 生成用于进行仿真的依赖项相关的参数
-     * @param dependences 
      * @returns 
      */
     private makeDependenceArguments(dependences: string[]): string {
@@ -236,9 +235,6 @@ class IcarusSimulate extends Simulate {
 
     /**
      * @description 获取 iverilog 仿真的命令
-     * @param name name of top module
-     * @param path path of the simulated file
-     * @param dependences dependence that not specified in `include macro
      * @returns 
      */
     private getCommand(name: string, path: AbsPath, dependences: string[]): string | undefined {
@@ -276,9 +272,38 @@ class IcarusSimulate extends Simulate {
         const argu = '-g' + iverilogCompileOptions.standard;
         const outVvpPath = makeSafeArgPath(hdlPath.join(simConfig.simulationHome, name + '.vvp'));      
         const mainPath = makeSafeArgPath(path);
-        
+
-        const cmd = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name} ${macroIncludeArgs} ${thirdLibraryDirArgs} ${mainPath} ${dependenceArgs} ${thirdLibraryFileArgs}`;
+        const args = [];
-        return cmd;
+        if (macroIncludeArgs) {
+            args.push(macroIncludeArgs);
+        }
+
+        if (thirdLibraryDirArgs) {
+            args.push(thirdLibraryDirArgs);
+        }
+
+        if (mainPath) {
+            args.push(mainPath);
+        }
+
+        if (dependenceArgs) {
+            args.push(dependenceArgs);
+        }
+
+        if (thirdLibraryFileArgs) {
+            args.push(thirdLibraryFileArgs);
+        }
+
+        const extaArgs = args.join(' ');
+        let command = `${iverilogPath} ${argu} -o ${outVvpPath} -s ${name}`;
+        if (extaArgs) {
+            command += ' ' + extaArgs;
+        }
+
+        const parent = fspath.dirname(path);
+        command += ' ' + '-I"' + parent + '"';
+
+        return command;
     }
 
     private execInTerminal(command: string, cwd: AbsPath, hdlModule: HdlModule) {
@@ -332,10 +357,6 @@ class IcarusSimulate extends Simulate {
 
     /**
      * @description 运行 iverilog xxx 的命令
-     * @param simConfig 
-     * @param command 
-     * @param cwd 
-     * @param hdlModule 
      */
     private runIverilog(simConfig: SimulateConfig, command: string, cwd: string, hdlModule: HdlModule) {
         child_process.exec(command, (error, stdout, stderr) => {
@@ -349,9 +370,9 @@ class IcarusSimulate extends Simulate {
             const generateVvpName = hdlModule.name + '.vvp';
 
             const outVvpPath = hdlPath.join(simConfig.simulationHome, generateVvpName);
-            MainOutput.report(t('info.simulation.create-vvp', outVvpPath), {
+            // MainOutput.report(t('info.simulation.create-vvp', outVvpPath), {
-                level: ReportType.Run
+            //     level: ReportType.Run
-            });
+            // });
             
             const vvpPath = simConfig.vvpPath;
 
@@ -361,7 +382,7 @@ class IcarusSimulate extends Simulate {
             const vvpCwd = opeParam.openMode === 'file' ? cwd: opeParam.workspacePath;
 
             const vvpCommand = `${vvpPath} ${outVvpPath}`;
-            MainOutput.report(vvpCommand, { level: ReportType.Run });
+            // MainOutput.report(vvpCommand, { level: ReportType.Run });
             
             this.runVvp(vvpCommand, vvpCwd);
         });
@@ -369,8 +390,6 @@ class IcarusSimulate extends Simulate {
 
     /**
      * @description 陨星 vvp xxx 的命令
-     * @param command 
-     * @param cwd 
      */
     private runVvp(command: string, cwd: string) {
         child_process.exec(command, { cwd }, (error, stdout, stderr) => {
@@ -408,7 +427,7 @@ class IcarusSimulate extends Simulate {
                 if (match) {
                     const vcdPath = match[1];
                     const absVcdPath = hdlPath.resolve(cwd, vcdPath);
-                    MainOutput.report(t('info.simulate.vvp.vcd-generate', absVcdPath));
+                    MainOutput.report(t('info.simulate.vvp.vcd-generate', absVcdPath), { level: ReportType.Finish });
                 } else {
                     MainOutput.report(line.slice(9).trim());
                 }
@@ -429,7 +448,10 @@ class IcarusSimulate extends Simulate {
                     MainOutput.report(line.slice(10).trim(), { level: ReportType.Error });
                 }
             } else {
-                MainOutput.report(line, { level: ReportType.Info });
+                const displayMessage = line.trim();
+                if (displayMessage) {
+                    MainOutput.report(displayMessage, { level: ReportType.PrintOuput});
+                }
             }
         }
     }
@@ -470,7 +492,7 @@ class IcarusSimulate extends Simulate {
         //     return;
         // }
         
-        const dependences = this.getAllOtherDependences(path, name);
+        const dependences = this.getAllOtherDependences(path, name);        
         const simulationCommand = this.getCommand(name, path, dependences);
         if (simulationCommand) {
             const cwd = hdlPath.resolve(path, '..');            

src/global/outputChannel.ts

@@ -33,7 +33,15 @@ enum ReportType {
     /**
      * 某些功能或者子进程在运行中产出的信息
      */
-    Run = 'Run'
+    Run = 'Run',
+    /**
+     * 展示程序的输出
+     */
+    PrintOuput = 'PrintOutput',
+    /**
+     * 代表程序的结束
+     */
+    Finish = 'Finish'
 };
 
 interface ReportOption {
@@ -96,13 +104,24 @@ class Output {
         option = option || { level: ReportType.Info, notify: false } as ReportOption;
         const level = option.level || ReportType.Info;
         const notify = option.notify || false;
-        
+
         if (!this.skipMessage(level) && message) {
             const currentTime = this.getCurrentTime();
-            this._output.appendLine('[' + level + ' - ' + currentTime + '] ' + message);
 
-            if (notify) {
+            switch (option.level) {
-                this.showInWindows('' + message, level);
+                case ReportType.PrintOuput:
+                    this._output.appendLine(message.toString());
+                    break;
+                case ReportType.Finish:
+                    this._output.appendLine('\n[' + level + ' - ' + currentTime + '] ' + message);
+                    break;
+            
+                default:
+                    this._output.appendLine('[' + level + ' - ' + currentTime + '] ' + message);
+                    if (notify) {
+                        this.showInWindows('' + message, level);
+                    }
+                    break;
             }
         }
     }

src/hdlParser/core.ts

@@ -885,7 +885,7 @@ class HdlModule {
         const instModName = rawHdlInstance.type;
 
         if (this.languageId === HdlLangID.Verilog || this.languageId === HdlLangID.SystemVerilog) {
-            const searchResult = this.searchInstModPath(instModName);
+            const searchResult = this.searchInstModPath(instModName);            
             const hdlInstance = new HdlInstance(rawHdlInstance.name,
                                                 rawHdlInstance.type,
                                                 searchResult.path,

src/monitor/hdl.ts

@@ -105,6 +105,7 @@ export class HdlAction extends BaseAction {
         // 更新 hdl 文件
         const fast = await LspClient.DigitalIDE?.sendRequest(SyncFastRequestType, { path, fileType, toolChain })
         if (fast) {
+            console.log('update includes:', fast.macro.includes);
             hdlParam.updateFast(path, fast);
         }
         

syntaxes/digital-ide-output.json

@@ -71,6 +71,21 @@
                 }
             }
         },
+        {
+            "name": "digital-ide.Finish",
+            "match": "^(\\[Finish - (.*?)\\])(.*)",
+            "captures": {
+                "1": {
+                    "name": "token.warn-token"
+                },
+                "2": {
+                    "name": "string"
+                },
+                "3": {
+                    "name": "token.warn-token"
+                }
+            }
+        },
         {
             "name": "digital-ide.Launch",
             "match": "^(\\[Launch - (.*?)\\])([\\s\\S]*)",