fix clean command
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@ -1,7 +0,0 @@
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set_param general.maxThreads 8
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create_project template d:/Project/FPGA/Design/TCL_project/Test/Efinity/prj/xilinx -part none -force
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set_property SOURCE_SET sources_1 [get_filesets sim_1]
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set_property top_lib xil_defaultlib [get_filesets sim_1]
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update_compile_order -fileset sim_1 -quiet
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source d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/refresh.tcl -quiet
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file delete d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/launch.tcl -force
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@ -1,17 +0,0 @@
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remove_files -quiet [get_files]
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set xip_repo_paths {}
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set_property ip_repo_paths $xip_repo_paths [current_project] -quiet
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update_ip_catalog -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/async_fifo.v -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/DPRAM.v -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_decode.sv -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_encode.sv -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_pkg.sv -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hbram_controller.v -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hbram_ctrl.v -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hyper_bus.v -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram_test.v -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/spi_slave.v -quiet
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add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/test.v -quiet
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add_files -fileset constrs_1 d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/data -quiet
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file delete d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/refresh.tcl -force
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@ -245,8 +245,12 @@ export async function clean() {
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const plName = opeParam.prjInfo.prjName.PL;
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const plName = opeParam.prjInfo.prjName.PL;
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const targetPath = fspath.dirname(opeParam.prjInfo.arch.hardware.src);
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const targetPath = fspath.dirname(opeParam.prjInfo.arch.hardware.src);
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const sourceIpPath = `${workspacePath}/prj/xilinx/${plName}.srcs/sources_1/ip`;
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let type = 'srcs';
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const sourceBdPath = `${workspacePath}/prj/xilinx/${plName}.srcs/sources_1/bd`;
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if (hdlDir.isDir(`${workspacePath}/prj/xilinx/${plName}.gen`)) {
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type = 'gen';
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}
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const sourceIpPath = `${workspacePath}/prj/xilinx/${plName}.${type}/sources_1/ip`;
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const sourceBdPath = `${workspacePath}/prj/xilinx/${plName}.${type}/sources_1/bd`;
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hdlDir.mvdir(sourceIpPath, targetPath, true);
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hdlDir.mvdir(sourceIpPath, targetPath, true);
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MainOutput.report("move dir from " + sourceIpPath + " to " + targetPath);
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MainOutput.report("move dir from " + sourceIpPath + " to " + targetPath);
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