test efinix finish

package.json

@@ -1278,9 +1278,9 @@
         "chokidar": "^4.0.1",
         "minimatch": "^10.0.1",
         "pako": "^2.1.0",
-        "puppeteer-core": "^24.4.0",
+        "puppeteer-core": "^19.4.1",
         "showdown": "^2.1.0",
-        "state-machine-cat": "^12.0.21",
+        "state-machine-cat": "^9.2.5",
         "tar": "^7.4.3",
         "temp": "^0.9.4",
         "vscode-jsonrpc": "^8.2.1",

project/property-schema.json

@@ -198,7 +198,8 @@
 				"xc7a35tftg256-1",
 				"xc7a35tcsg324-1",
 				"xc7z035ffg676-2",
-				"xc7z020clg484-1"
+				"xc7z020clg484-1",
+				"Ti60F100S3F2-C4"
 			]
 		}
 	},

resources/script/xilinx/launch.tcl

@@ -0,0 +1,7 @@
+set_param general.maxThreads 8
+create_project template d:/Project/FPGA/Design/TCL_project/Test/Efinity/prj/xilinx -part none -force
+set_property SOURCE_SET sources_1   [get_filesets sim_1]
+set_property top_lib xil_defaultlib [get_filesets sim_1]
+update_compile_order -fileset sim_1 -quiet
+source d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/refresh.tcl -quiet
+file delete d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/launch.tcl -force

resources/script/xilinx/refresh.tcl

@@ -0,0 +1,17 @@
+remove_files -quiet [get_files]
+set xip_repo_paths {}
+set_property ip_repo_paths $xip_repo_paths [current_project] -quiet
+update_ip_catalog -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/async_fifo.v -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/DPRAM.v -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_decode.sv -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_encode.sv -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/ecc_pkg.sv -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hbram_controller.v -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hbram_ctrl.v -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram/hyper_bus.v -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/hbram_test.v -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/spi_slave.v -quiet
+add_file d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/src/test.v -quiet
+add_files -fileset constrs_1 d:/Project/FPGA/Design/TCL_project/Test/Efinity/user/data -quiet
+file delete d:/Project/Code/.prj/Digital-IDE/resources/script/xilinx/refresh.tcl -force

src/function/treeView/tree.ts

@@ -288,9 +288,15 @@ class ModuleTreeProvider implements vscode.TreeDataProvider<ModuleDataItem> {
 
     public setFirstTop(type: keyof FirstTop, name: string, path: AbsPath | undefined) {
         this.firstTop[type] = {name, path};
+        if (type == "src") {            
+            opeParam.firstSrcTopModule.name = name;
+            opeParam.firstSrcTopModule.path = path;
+        } else if (type == "sim") {
+            opeParam.firstSimTopModule.name = name;
+            opeParam.firstSimTopModule.path = path;
+        }   
     }
 
-
     private makeFirstTopIconName(type: string): string {
         return 'current-' + type + '-top';
     }

src/global/enum.ts

@@ -34,6 +34,7 @@ function validToolChainType(name: ToolChainType) {
     const allTypes = [
         'xilinx',
         'intel',
+        'efinity',
         'custom'
     ];
     return allTypes.includes(name);

src/global/opeParam.ts

@@ -22,7 +22,7 @@ const OpeParamDefaults = {
 
 interface FirstTopModuleDesc {
     name: string
-    path: AbsPath
+    path: AbsPath | undefined
 };
 
 function readJSON(path: AbsPath): object {

src/manager/PL/efinity.ts

@@ -96,13 +96,25 @@ const security = `  <efx:security>
     <efx:param name="auth_key_file" value="NONE" value_type="e_string"/>
   </efx:security>`;
 
+export interface ePLContext {
+    // 保留启动上下文
+    terminal? : vscode.Terminal,
+    // 目前使用的启动上下文
+    process?: ChildProcessWithoutNullStreams,
+    // 工具类型
+    tool? : string,
+    // 第三方工具运行路径
+    path? : string,
+    // 操作类
+    ope : EfinityOperation,
+};
 
 export class EfinityOperation {
     script: string;
     efxPath: string;
     constructor() {
         this.script = '';
-        this.efxPath = hdlPath.join(opeParam.workspacePath, `${opeParam.prjInfo.prjName}.xml`);
+        this.efxPath = hdlPath.join(opeParam.workspacePath, `${opeParam.prjInfo.prjName.PL}.xml`);
     }
 
     private getDeviceInfo(device: string): string {
@@ -120,12 +132,22 @@ export class EfinityOperation {
     }
 
     private getDesignInfo(): string {
-
         let designFile = `    <efx:top_module name="${opeParam.firstSrcTopModule.name}"/>\n`;
         for (const hdlFile of hdlParam.getAllHdlFiles()) {
-            // ${hdlFile.path}
+            switch (hdlFile.projectType) {
-            designFile += `    <efx:design_file name="${hdlFile.path}" version="default" library="default"/>\n`;
+                case HdlFileProjectType.Src:
-
+                case HdlFileProjectType.LocalLib:
+                case HdlFileProjectType.RemoteLib:
+                case HdlFileProjectType.Sim:
+                    designFile += `    <efx:design_file name="${hdlFile.path}" version="default" library="default"/>\n`;
+                    break;
+                case HdlFileProjectType.IP:
+                case HdlFileProjectType.Primitive:
+                    // IP 和 原语不用管
+                    break;
+                default:
+                    break;
+            }
         }
         designFile += `    <efx:top_vhdl_arch name=""/>`
         return `  <efx:design_info def_veri_version="verilog_2k" def_vhdl_version="vhdl_2008">\n${designFile}
@@ -136,25 +158,24 @@ export class EfinityOperation {
         let constraintFile = '';
         hdlFile.pickFileRecursive(opeParam.prjInfo.arch.hardware.data, filePath => {
             if (filePath.endsWith('.sdc')) {
-                constraintFile += `    <efx:constraint_file name="${filePath}" />\n`;
+                constraintFile += `  <efx:constraint_file name="${filePath}" />\n`;
             }
         });
 
         constraintFile += `    <efx:inter_file name="" />\n`;
 
-        return `    <efx:constraint_info>\n${constraintFile}    </efx:constraint_info>`;
+        return `  <efx:constraint_info>\n${constraintFile}    </efx:constraint_info>`;
     }
 
     public launch() {
-        this.script = `<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="${opeParam.prjInfo.prjName}" description="" last_change="1724639062" sw_version="2023.2.307" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">\n${this.getDeviceInfo}\n${this.getDesignInfo}\n${this.getConstraintInfo}\n  <efx:sim_info />\n  <efx:misc_info />\n  <efx:ip_info />\n${syn}\n${pnr}\n${bit}\n${debug}\n${security}\n</efx:project>`;
+        this.script = `<efx:project xmlns:efx="http://www.efinixinc.com/enf_proj" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" name="${opeParam.prjInfo.prjName}" description="" last_change="1724639062" sw_version="2023.2.307" last_run_state="pass" last_run_flow="bitstream" config_result_in_sync="sync" design_ood="sync" place_ood="sync" route_ood="sync" xsi:schemaLocation="http://www.efinixinc.com/enf_proj enf_proj.xsd">\n${this.getDeviceInfo(opeParam.prjInfo.device)}\n${this.getDesignInfo()}\n${this.getConstraintInfo()}\n  <efx:sim_info />\n  <efx:misc_info />\n  <efx:ip_info />\n${syn}\n${pnr}\n${bit}\n${debug}\n${security}\n</efx:project>`;
 
         fs.writeFileSync(this.efxPath, this.script);
 
     }
 
     public build() {
-        const efxPath = hdlPath.join(opeParam.workspacePath, `${opeParam.prjInfo.prjName}.xml`);
+        exec(`${this.updateEfinixPath()} ${this.efxPath} --flow compile --work_dir=${opeParam.workspacePath}/prj/efinix --output_dir ${opeParam.workspacePath}/prj/efinix/outflow --cleanup_work_dir work_pt`, (error, stdout, stderr) => {
-        exec(`${this.updateEfinixPath()} ${efxPath} --flow compile --work_dir=${opeParam.workspacePath}/prj/efinix --output_dir ${opeParam.workspacePath}/prj/efinix/outflow --cleanup_work_dir work_pt`, (error, stdout, stderr) => {
             console.log(error);
             
         })

src/manager/PL/index.ts

@@ -16,6 +16,7 @@ import { PropertySchema } from '../../global/propertySchema';
 import { HardwareOutput, MainOutput, ReportType } from '../../global/outputChannel';
 import { AbsPath } from '../../global';
 import { t } from '../../i18n';
+import { EfinityOperation } from './efinity';
 
 class PlManage extends BaseManage {
     context: PLContext;
@@ -24,7 +25,7 @@ class PlManage extends BaseManage {
         super();
 
         this.context = { 
-            tool: opeParam.prjInfo.toolChain || 'xilinx', 
+            tool: opeParam.prjInfo.toolChain, 
             path: '',
             ope: new XilinxOperation(),
             terminal: undefined,
@@ -34,7 +35,10 @@ class PlManage extends BaseManage {
         const curToolChain = this.context.tool;
         if (curToolChain === ToolChainType.Xilinx) {
             this.context.path = this.context.ope.updateVivadoPath();
-        }       
+        } else if (curToolChain === ToolChainType.Efinity) {
+            this.context.ope = new EfinityOperation();
+            this.context.path = this.context.ope.updateEfinixPath();
+        }      
     }
 
     public launch() {

src/manager/PL/xilinx.ts

@@ -36,7 +36,7 @@ interface PLContext {
     // 第三方工具运行路径
     path? : string,
     // 操作类
-    ope : XilinxOperation,
+    ope : Record<string, any>
 };
 
 interface PLPrjInfo {
@@ -54,7 +54,6 @@ interface BootInfo {
     fsblPath : AbsPath
 };
 
-
 /**
  * xilinx operation under PL
  */
@@ -394,7 +393,6 @@ class XilinxOperation {
         });
 
         // 导入非本地的设计源文件
-        console.log(hdlParam.getAllHdlFiles());
         for (const hdlFile of hdlParam.getAllHdlFiles()) {
             switch (hdlFile.projectType) {
                 case HdlFileProjectType.Src:
@@ -620,7 +618,6 @@ file delete ${scriptPath} -force\n`;
         context.process?.stdin.write(cmd + '\n');
     }
 
-
     generateBit(context: PLContext) {
         vscode.window.showInformationMessage(
             "Xilinx: BitStream",