更新 sv 高亮语法 | 更新 i18n

config/systemverilog.configuration.json

@@ -27,5 +27,8 @@
 		{"open":"[", "close":"]", "notIn":["string", "comment"]},
 		{"open":"{", "close":"}", "notIn":["string", "comment"]},
 		{"open":"\"", "close":"\"", "notIn":["string", "comment"]}
-	]
+	],
+    "onTypeFormatting": {
+        "autoFormatTriggerCharacters": ["\n"]
+    }
 }

config/verilog.configuration.json

@@ -13,11 +13,13 @@
 		["module", "endmodule"],
 		["task", "endtask"]
 	],
-
 	"autoClosingPairs": [
 		{"open":"(", "close":")", "notIn":["string", "comment"]},
 		{"open":"[", "close":"]", "notIn":["string", "comment"]},
 		{"open":"{", "close":"}", "notIn":["string", "comment"]},
 		{"open":"\"", "close":"\"", "notIn":["string", "comment"]}
-	]
+	],
+    "onTypeFormatting": {
+        "autoFormatTriggerCharacters": ["\n"]
+    }
 }

config/vhdl.configuration.json

@@ -22,5 +22,8 @@
         ["(", ")"],
         ["\"", "\""],
         ["'", "'"]
-    ]
+    ],
+    "onTypeFormatting": {
+        "autoFormatTriggerCharacters": ["\n"]
+    }
 }

package.json

@@ -293,6 +293,11 @@
                     "description": "auto declare output type nets in the scope when instantiation happens.",
                     "type": "boolean",
                     "default": true
+                },
+                "fpga-support.onTypeFormattingTriggerCharacters": {
+                    "type": "array",
+                    "default": ["\n"],
+                    "description": "Trigger characters for onTypeFormatting"
                 }
             }
         },
@@ -788,7 +793,7 @@
             "activitybar": [
                 {
                     "id": "TreeView",
-                    "title": "Digital-IDE: TreeView",
+                    "title": "%digital-ide.treeview%",
                     "icon": "images/svg/view.svg"
                 }
             ]

package.nls.json

@@ -46,5 +46,6 @@
     "digital-ide.lsp.svlog.linter.pick.title": "select a diagnostic for systemverilog verilog",
     "digital-ide.lsp.vhdl.linter.pick.title": "select a diagnostic for vhdl",
     "digital-ide.lsp.systemverilog.linter.pick.title": "select a diagnostic for systemverilog",
-    "digital-ide.tool.export-filelist.title": "export filelist"
+    "digital-ide.tool.export-filelist.title": "export filelist",
+    "digital-ide.treeview": "Digital IDE: TreeView"
 }

package.nls.zh-cn.json

@@ -7,18 +7,18 @@
     "digital-ide.tool.instance.title": "生成选中 module 的例化模板",
     "digital-ide.tool.testbench.title": "从当前文件中选择 module 生成 testbench",
     "digital-ide.tool.icarus.simulateFile.title": "对当前文件进行仿真",
-    "digital-ide.treeView.arch.expand.title": "扩大树视图中的所有项目",
+    "digital-ide.treeView.arch.expand.title": "展开视图中的所有项目",
-    "digital-ide.treeView.arch.collapse.title": "崩溃树视图中的所有项目",
+    "digital-ide.treeView.arch.collapse.title": "收起视图中的所有项目",
     "digital-ide.treeView.arch.refresh.title": "刷新树视图",
     "digital-ide.treeView.arch.openFile.title": "在树视图打开相应的文件",
-    "digital-ide.tool.clean.title": "干净的当前项目",
+    "digital-ide.tool.clean.title": "清理的当前项目",
     "digital-ide.soft.launch.title": "启动SDK开发辅助功能",
     "digital-ide.soft.build.title": "建立项目当前的SDK",
     "digital-ide.soft.download.title": "下载文件到设备引导",
     "digital-ide.hard.launch.title": "启动FPGA开发辅助功能",
     "digital-ide.hard.simulate.title": "启动生产仿真",
-    "digital-ide.hard.simulate.cli.title": "在CLI推出制造商模拟",
+    "digital-ide.hard.simulate.cli.title": "CLI",
-    "digital-ide.hard.simulate.gui.title": "在GUI推出制造商模拟",
+    "digital-ide.hard.simulate.gui.title": "GUI",
     "digital-ide.hard.refresh.title": "刷新当前的项目文件",
     "digital-ide.hard.build.title": "fpga构建当前项目",
     "digital-ide.hard.build.synth.title": "Synth当前项目",
@@ -27,7 +27,7 @@
     "digital-ide.hard.program.title": "下载文件到设备",
     "digital-ide.hard.gui.title": "打开界面",
     "digital-ide.hard.exit.title": "退出当前项目",
-    "digital-ide.pickLibrary.title": "从自定义选择自由和普遍",
+    "digital-ide.pickLibrary.title": "选择库文件",
     "digital-ide.pl.setSrcTop.title": "设置为 src 的顶层文件",
     "digital-ide.pl.setSimTop.title": "设置为 sim 的顶层文件",
     "digital-ide.pl.addDevice.title": "添加 device",
@@ -46,5 +46,6 @@
     "digital-ide.lsp.svlog.linter.pick.title": "选择 System Verilog 的诊断",
     "digital-ide.lsp.vhdl.linter.pick.title": "选择 VHDL 的诊断",
     "digital-ide.lsp.systemverilog.linter.pick.title": "选择 SystemVerilog 的诊断",
-    "digital-ide.tool.export-filelist.title": "导出 filelist"
+    "digital-ide.tool.export-filelist.title": "导出 filelist",
+    "digital-ide.treeview": "Digital IDE: 模块树"
 }

package.nls.zh-tw.json

@@ -46,5 +46,6 @@
     "digital-ide.lsp.svlog.linter.pick.title": "選擇 System Verilog 的診斷",
     "digital-ide.lsp.vhdl.linter.pick.title": "選擇 VHDL 的診斷",
     "digital-ide.lsp.systemverilog.linter.pick.title": "選擇 SystemVerilog 的診斷",
-    "digital-ide.tool.export-filelist.title": "導出 filelist"
+    "digital-ide.tool.export-filelist.title": "導出 filelist",
+    "digital-ide.treeview": "Digital IDE: 模块树"
 }

src/extension.ts

@@ -21,7 +21,7 @@ async function registerCommand(context: vscode.ExtensionContext) {
     func.registerWaveViewer(context);
 
     lspClient.activate(context);
-    await LspClient.MainClient?.onReady();
+    await LspClient.DigitalIDE?.onReady();
 }
 
 async function launch(context: vscode.ExtensionContext) {

src/function/index.ts

@@ -85,10 +85,10 @@ function registerLsp(context: vscode.ExtensionContext) {
 
     
     // vhdl lsp    
-    vscode.languages.registerDocumentSymbolProvider(vhdlSelector, lspDocSymbol.vhdlDocSymbolProvider);
+    // vscode.languages.registerDocumentSymbolProvider(vhdlSelector, lspDocSymbol.vhdlDocSymbolProvider);
-    vscode.languages.registerDefinitionProvider(vhdlSelector, lspDefinition.vhdlDefinitionProvider);
+    // vscode.languages.registerDefinitionProvider(vhdlSelector, lspDefinition.vhdlDefinitionProvider);
-    vscode.languages.registerHoverProvider(vhdlSelector, lspHover.vhdlHoverProvider);
+    // vscode.languages.registerHoverProvider(vhdlSelector, lspHover.vhdlHoverProvider);
-    vscode.languages.registerCompletionItemProvider(vhdlSelector, lspCompletion.vhdlCompletionProvider);
+    // vscode.languages.registerCompletionItemProvider(vhdlSelector, lspCompletion.vhdlCompletionProvider);
     
 
     // tcl lsp

src/function/lsp-client/index.ts

@@ -59,6 +59,9 @@ export function activate(context: vscode.ExtensionContext) {
                 language: 'vhdl'
             }
         ],
+        markdown: {
+            isTrusted: true
+        }
     };
 
     const client = new LanguageClient(
@@ -67,15 +70,15 @@ export function activate(context: vscode.ExtensionContext) {
         serverOptions,
         clientOptions
     );
-    LspClient.MainClient = client;
+    LspClient.DigitalIDE = client;
     
     client.start();
 }
 
 export function deactivate(): Thenable<void> | undefined {
-    if (!LspClient.MainClient) {
+    if (!LspClient.DigitalIDE) {
         return undefined;
     }
-    return LspClient.MainClient.stop();
+    return LspClient.DigitalIDE.stop();
 }
 

src/global/lsp.ts

@@ -4,12 +4,12 @@ import { Fast } from '../../resources/hdlParser';
 
 
 interface IDigitalIDELspClient {
-    MainClient?: LanguageClient,
+    DigitalIDE?: LanguageClient,
     VhdlClient?: LanguageClient
 }
 
 export const LspClient: IDigitalIDELspClient = {
-    MainClient: undefined,
+    DigitalIDE: undefined,
     VhdlClient: undefined
 };
 

src/hdlParser/core.ts

@@ -257,6 +257,15 @@ class HdlParam {
 
         progress?.report({ message: reportTitle + ` ${1}/${fileNum}`, increment: 0 });
 
+        // for (const path of hdlFiles) {
+        //     count ++;
+        //     console.log('send request: ' + path);
+            
+        //     await this.doHdlFast(path);
+        //     const increment = Math.floor(count / fileNum * 100);
+        //     progress?.report({ message: reportTitle + ` ${count}/${fileNum}`, increment });
+        // }
+
         async function consumePools() {
             for (const p of pools) {
                 const increment = Math.floor(p.id / fileNum * 100);
@@ -575,7 +584,7 @@ class HdlModule {
                                                 this.path,
                                                 common.InstModPathStatus.Current,
                                                 rawHdlInstance.instparams,
-                                                this.ports[0].range,
+                                                rawHdlInstance.instports,
                                                 rawHdlInstance.range,
                                                 this);
             hdlInstance.module = this;

src/hdlParser/util.ts

@@ -1,5 +1,5 @@
 import * as vscode from 'vscode';
-import { Fast, vlogAll, vhdlAll, svAll, vhdlFast, All } from '../../resources/hdlParser';
+import { Fast, vlogAll, vhdlAll, svAll, All } from '../../resources/hdlParser';
 import { hdlFile } from '../hdlFs';
 import { HdlLangID } from '../global/enum';
 import { AbsPath, LspClient } from '../global';
@@ -8,7 +8,7 @@ import { RawHdlModule } from './common';
 
 async function doFastApi(path: string): Promise<Fast | undefined> {
     try {
-        const client = LspClient.MainClient;
+        const client = LspClient.DigitalIDE;
         const langID = hdlFile.getLanguageId(path);
         if (client) {
             const response = await client.sendRequest(DoFastRequestType, { path });            
@@ -32,6 +32,11 @@ async function svFast(path: string): Promise<Fast | undefined> {
     return fast;
 }
 
+async function vhdlFast(path: string): Promise<Fast | undefined> {
+    const fast = await doFastApi(path);
+    return fast;
+}
+
 namespace HdlSymbol {
     /**
      * @description 计算出模块级的信息

src/manager/prj.ts

@@ -155,7 +155,7 @@ class PrjManage {
         MainOutput.report(`finish analyse ${hdlFiles.length} hdl files, find ${unhandleNum} unsolved instances`, ReportType.Info);
 
         // 完成后端向前端发送消息的注册
-        const mainClient = LspClient.MainClient;
+        const mainClient = LspClient.DigitalIDE;
         if (mainClient !== undefined) {
             await mainClient.onReady();
             mainClient.onNotification('update/fast', async (params: any) => {