50 lines
2.8 KiB
Markdown
50 lines
2.8 KiB
Markdown
<div align="center">
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<img src="./images/icon.png"/>
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## <code>Digital IDE</code> | All in one <code>vscode</code> plugin for Verilog/VHDL development
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[Document (New)](https://nc-ai.cn/) | [中文文档 (New)](https://nc-ai.cn/zh/) | [Bilibili Video](https://www.bilibili.com/video/BV1t14y1179V/?spm_id_from=333.999.0.0)
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</div>
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## New in 0.4.0
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**Rewritten Parser and Language Services in Rust**: Supports Verilog, VHDL, and SystemVerilog with faster performance and more stable services.
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**Improved Documentation**: Provides more direct and faster access to basic information and dependencies of the current HDL file. Supports Wavedrom-style comments and renders them into visual diagrams.
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**New VCD Renderer**: Added top toolbar, system beacon, and other components; supports drag-and-drop and grouping of selected signals in the left panel, as well as selecting multiple signals by holding Shift for addition and deletion; supports establishing a relative coordinate system based on system beacons; the top toolbar supports base conversion for displayed numbers of selected signals, rendering mode switching, and rendering signals as analog values.
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- Brand New Netlist Renderer
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## Features
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- Added comprehensive support for VHDL (file tree, LSP, etc.)
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- Added workspace icons for languages or generated files such as Verilog, VHDL, XDC, TCL, VVP, VCD, etc.
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- Added support for Vivado, ModelSim, and Verilator. Users can use these third-party tools for simulation and auto-correction by setting `function.lsp.linter.vhdl.diagnostor` (for VHDL) and `function.lsp.linter.vlog.diagnostor` (for Verilog).
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- Added LSP and syntax highlighting support for scripts like TCL, XDC, and VVP.
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## Changes
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- Display the plugin's working status in the status bar at the bottom of VSCode, making it easier for users to understand the current settings.
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- The bottom-right corner of the status bar now shows the currently selected linter and whether it is functioning properly.
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- Optimized project configuration directory.
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- Improved auto-completion performance.
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## Bug Fixes
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- Fixed a bug where comments on `input` and `output` were not displayed correctly in the documentation.
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- Fixed a bug in the Icarus Verilog simulation feature where duplicate paths were included as compilation parameters.
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- Fixed a bug in the Icarus Verilog simulation feature where adding or removing <code>`include</code> would cause simulation compilation to fail (the `instModPathStatus` property of the instance was not updated).
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- Fixed other known bugs. |