36 lines
1.4 KiB
Markdown
36 lines
1.4 KiB
Markdown
# Digital IDE - version 0.3.0
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<center>
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<img src="./images/DIDE.png">
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</center>
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> ASIC & FPGA develop Platform on VS code (IDE for development of verilog, vhdl and system verilog)
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- If you have any questions, please post them under [issues](https://github.com/Bestduan/Digital-IDE/issues).
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- If you like it, please [star](https://github.com/Bestduan/Digital-IDE).
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[English](https://bestduan.github.io/Digital-IDE-doc/#/)
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[中文教程](https://digital-eda.github.io/DIDE-doc-Cn/#/)
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You are free to use it. Finally, if you like this extension and have some great idea, please connact with me. I am look foward to your joining.
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- Email: sterben.661214@gmail.com.
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- QQ群: 932987873
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--------------------------------------------------------------------------------------------
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## Thanks
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* [VHDL](https://github.com/puorc/awesome-vhdl)
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* [TerosHDL](https://github.com/TerosTechnology/vscode-terosHDL)
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* [TCL Language Support](https://github.com/go2sh/tcl-language-support)
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* [Verilog HDL/SystemVerilog](https://github.com/mshr-h/vscode-verilog-hdl-support)
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* [SystemVerilog - Language Support](https://github.com/eirikpre/VSCode-SystemVerilog) |