Kirigaya ea1a70e8aa finish left parts 1

2023-11-29 01:22:05 +08:00

..

arm.json

initialize

2023-01-20 15:16:35 +08:00

digital-ide-output.json

add icon of vvp | pass vivado lsp | pass modelsim lsp

2023-11-27 20:05:24 +08:00

link.json

initialize

2023-01-20 15:16:35 +08:00

systemverilog.json

initialize

2023-01-20 15:16:35 +08:00

tcl.json

initialize

2023-01-20 15:16:35 +08:00

verilog.json

#fix hover | #fix completion

2023-07-07 02:29:43 +08:00

verilog.tmLanguage.json

finish document

2023-08-18 01:36:50 +08:00

vhdl.tmLanguage.json

finish left parts 1

2023-11-29 01:22:05 +08:00

vvp.tmLanguage.json

add icon of vvp | pass vivado lsp | pass modelsim lsp

2023-11-27 20:05:24 +08:00