114 lines
3.5 KiB
Markdown
114 lines
3.5 KiB
Markdown
# Change Log
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All notable changes to the "digital-ide" extension will be documented in this file.
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Check [Keep a Changelog](http://keepachangelog.com/) for recommendations on how to structure this file.
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## [0.3.2] - 2023-11-01
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Bug 修复
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- 修复文档化input, output处注释无法正常显示到文档的 bug
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- 修复 iverilog 仿真功能中，将重复的路径作为编译参数编译的 bug
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- 修复 iverilog 仿真功能中，将 `include 加入或去除后，无法通过仿真编译的 bug （没有更新 instance 的 instModPathStatus 属性）
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Feat
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- 增加对 XDC，TCL 等脚本的 LSP 支持
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- 增加 verilog, vhdl, xdc, tcl 等语言的图标
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- 增加对于 vivado 的支持，用户可以通过添加 vivado 路径的方式（或者将 bin 文件夹添加到环境变量，默认路径为 C:\Xilinx\Vivado\2018.3\bin）来使用 vivado 的仿真和自动纠错
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- 增加对于 modelsim 的支持，用户可以通过添加 modelsim 安装路径（或者将 bin 文件夹添加到环境变量，默认路径为 C:\modeltech64_10.4\win64）来使用 vivado 的仿真和自动纠错
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## [0.1.23] - 2022-12-24
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- Finish the css of documentation, see `./css/documentation.css` for detail.
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## [0.1.23] - 2022-12-23
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- Finish the function of documentation, webview display
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- Finish the function of documentation, support export markdown and html
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## [0.1.23] - 2022-12-22
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- Rename partial tokens of verilog, make highlighting more colorful
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## [0.1.23] - 2022-12-05
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- Tree View can display the module that has not solved the dependence
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- Finish the function of Instance and add icon for each solved module
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## [0.1.23] - 2022-12-02
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- Add unit test for most of logic
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## [0.1.23] - 2022-12-01
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- Finish reconstruction of HDLparam
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- Finish the implementation of tree view
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## [0.1.22] - 2022-01-20
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- Fix lib files do not display in tree view
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## [0.1.21] - 2022-01-20
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- Fix issue [#26](https://github.com/Bestduan/Digital-IDE/issues/26)
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- Rename as Digital-IDE
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- Fix generate property.json file
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## [0.1.20] - 2022-01-12
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- Fix issue [#32](https://github.com/Bestduan/Digital-IDE/issues/32)
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## [0.1.18] - 2021-09-12
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- delete generate tb file
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- add function netlist show
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- Fix issue [#25](https://github.com/Bestduan/fpga_support_plug/issues/25)
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- Fix issue [#24](https://github.com/Bestduan/fpga_support_plug/issues/24)
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## [0.1.17] - 2021-09-04
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- Fix issue [#22](https://github.com/Bestduan/fpga_support_plug/issues/22)
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- Fix issue [#21](https://github.com/Bestduan/fpga_support_plug/issues/21)
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- Fix issue [#20](https://github.com/Bestduan/fpga_support_plug/issues/20)
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## [0.1.16] - 2021-07-26
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- Optimization of the kernel, fix High CPU usage
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- Fix some other known bugs
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- Add Formatter function
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## [0.1.15] - 2021-05-02
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- Fix some bugs and add instructions
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## [0.1.12] - 2021-04-28
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- Added simulation function, automatically pop up error message
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## [0.1.10] - 2020-04-16
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- Added simulation function, automatically pop up error message
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## [0.1.8] - 2020-03-30
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- Fixed the problem of repeatedly opening a new project and supported adding devices directly from the Makefile
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## [0.1.6] - 2020-03-19
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- Add support for IP design and bd design
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- Add module jump (`Alt + F12` or `F12`)
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- Change the startup shortcut key
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- Fix some bugs to enhance robustness
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## [0.1.4] - 2020-03-10
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- Address the BUG existing in 0.1.3
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## [0.1.2] - 2020-03-03
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- Add Xilinx IP of Soc's cortexM3
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- Provide an example for `m3_for_xilinx.bd`
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- Resolve the file structure conversion problem
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## [0.0.2] - 2020-02-28
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- Added testbench / instance function
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## [0.0.1] - 2020-02-15
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- Initial Release |