update UT

This commit is contained in:
锦恢 2024-09-24 19:20:19 +08:00
parent 30cd26cab9
commit 30c83dd9a3
8 changed files with 138 additions and 3 deletions

1
Cargo.lock generated
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@ -210,6 +210,7 @@ dependencies = [
"once_cell", "once_cell",
"path-clean", "path-clean",
"pathdiff", "pathdiff",
"percent-encoding",
"regex", "regex",
"ropey", "ropey",
"serde", "serde",

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@ -8,6 +8,7 @@ edition = "2018"
sv-parser = { version = "0.13.3", path = "sv-parser/sv-parser"} sv-parser = { version = "0.13.3", path = "sv-parser/sv-parser"}
once_cell = "1.8" once_cell = "1.8"
futures = "0.3" futures = "0.3"
percent-encoding = "2.1.0"
log = "0.4.19" log = "0.4.19"
tower-lsp = "0.20.0" tower-lsp = "0.20.0"
flexi_logger = "0.29.0" flexi_logger = "0.29.0"

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@ -4,6 +4,8 @@ use std::{collections::HashMap, io::BufReader};
use std::path::PathBuf; use std::path::PathBuf;
use anyhow::Error; use anyhow::Error;
use log::info; use log::info;
use percent_encoding::percent_decode_str;
use std::env::consts::OS;
use sv_parser::{parse_sv, unwrap_node, ConstantMintypmaxExpression, GateInstantiation, ListOfParameterAssignments, ListOfPortConnections, Locate, PackedDimensionRange, RefNode, SyntaxTree}; use sv_parser::{parse_sv, unwrap_node, ConstantMintypmaxExpression, GateInstantiation, ListOfParameterAssignments, ListOfPortConnections, Locate, PackedDimensionRange, RefNode, SyntaxTree};
use super::fast_hdlparam::{FastHdlparam, Macro}; use super::fast_hdlparam::{FastHdlparam, Macro};
@ -27,11 +29,26 @@ pub fn sv_parser(path: &str) -> Option<FastHdlparam> {
} }
pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Result<FastHdlparam, Error> { pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Result<FastHdlparam, Error> {
// 对不同操作系统文件路径的支持
let decoded_path = percent_decode_str(path.to_str().unwrap()).decode_utf8_lossy();
let decoded_path_str = decoded_path.as_ref();
let path = match OS {
"windows" => {
// 去掉开头的斜杠
let trimmed_path_str = decoded_path_str.trim_start_matches('/');
PathBuf::from(trimmed_path_str)
},
_ => {
// 其他操作系统(如 Linux保持原样
PathBuf::from(decoded_path_str)
},
};
let mut hdlparam = FastHdlparam { let mut hdlparam = FastHdlparam {
fast_macro: Macro { fast_macro: Macro {
defines: Vec::new(), defines: Vec::new(),
errors: Vec::new(), errors: Vec::new(),
includes: get_includes(path), includes: get_includes(&path),
invalid: Vec::new() invalid: Vec::new()
}, },
content: Vec::new() content: Vec::new()
@ -71,7 +88,8 @@ pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Re
let replacement = match unwrap_node!(x, MacroText) { let replacement = match unwrap_node!(x, MacroText) {
Some(RefNode::MacroText(x)) => Some(x.nodes.0), Some(RefNode::MacroText(x)) => Some(x.nodes.0),
_ => None // TODO 把下面的 contine 替换为 None 会报错
_ => continue
}.unwrap(); }.unwrap();
let (end_line, end_character) = (replacement.line, get_column_by_offset(&content, replacement.offset) + replacement.len); let (end_line, end_character) = (replacement.line, get_column_by_offset(&content, replacement.offset) + replacement.len);
let replacement = syntax_tree.get_str(&replacement).unwrap(); let replacement = syntax_tree.get_str(&replacement).unwrap();
@ -602,10 +620,11 @@ fn get_column_by_offset(content: &[String], offset: usize) -> usize {
#[cfg(test)] #[cfg(test)]
mod tests { mod tests {
use std::fs; use std::{fs, path::Path};
use super::sv_parser; use super::sv_parser;
const TESTFILES_DIR: &str = "testfiles"; const TESTFILES_DIR: &str = "testfiles";
const DIGTIAL_IDE_TEST: &str = "/home/dide/project/Digital-Test/Digital-IDE-test/user";
macro_rules! unwrap_result { macro_rules! unwrap_result {
($expr:expr) => { ($expr:expr) => {
@ -640,4 +659,42 @@ mod tests {
} }
} }
} }
#[test]
fn test_digital_ide_test() {
// 判断路径是否存在且为文件夹
let path = Path::new(DIGTIAL_IDE_TEST);
if path.exists() && path.is_dir() {
// 递归遍历文件夹
if let Err(e) = traverse_directory(path) {
eprintln!("Error: {}", e);
}
} else {
eprintln!("Path does not exist or is not a directory");
}
}
fn traverse_directory(dir: &Path) -> Result<(), Box<dyn std::error::Error>> {
if dir.is_dir() {
for entry in fs::read_dir(dir)? {
let entry = entry?;
let path = entry.path();
if path.is_dir() {
// 递归遍历子文件夹
traverse_directory(&path)?;
} else if path.is_file() {
// 检查文件扩展名
if let Some(ext) = path.extension() {
if ext == "v" || ext == "sv" {
println!("Test file: {:?}", path);
let file_path = path.to_str().unwrap();
let _ = sv_parser(file_path);
}
}
}
}
}
Ok(())
}
} }

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@ -0,0 +1,51 @@
//https://stackoverflow.com/questions/17647819/looking-for-a-crc-implementation-in-systemverilog
module top;
function byte calc_crc(byte unsigned cmd[]);
bit [7:0] crc, d, c;
int i;
crc = 0;
for (i=0; i<cmd.size(); i++) begin
d = cmd[i];
c = crc;
crc[0] = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7];
crc[1] = d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6];
crc[2] = d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6];
crc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7];
crc[4] = d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4];
crc[5] = d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5];
crc[6] = d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6];
crc[7] = d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7];
//$display("crc result: %h",crc);
end
return crc;
endfunction
localparam CRC32POL = 32'hEDB88320; /* Ethernet CRC-32 Polynom, reverse Bits */
function automatic bit[31:0] genCRC32(input bit [7:0] databyte_stream[]);
int unsigned i, j;
bit [31:0] crc32_val = 32'hffffffff; // shiftregister,startvalue
bit [7:0] data;
//The result of the loop generate 32-Bit-mirrowed CRC
for (i = 0; i < databyte_stream.size; i++) // Byte-Stream
begin
data = databyte_stream[i];
for (j=0; j < 8; j++) // Bitwise from LSB to MSB
begin
if ((crc32_val[0]) != (data[0])) begin
crc32_val = (crc32_val >> 1) ^ CRC32POL;
end else begin
crc32_val >>= 1;
end
data >>= 1;
end
end
crc32_val ^= 32'hffffffff; //invert results
return crc32_val;
endfunction : genCRC32
endmodule

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@ -0,0 +1,8 @@
module ibex_alu #(
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
) (
input ibex_pkg::alu_op_e operator_i,
input logic [31:0] operand_a_i,
input logic [31:0] operand_b_i);
endmodule

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@ -0,0 +1,9 @@
`ifndef MEM_BASE_OBJECT_SV
`define MEM_BASE_OBJECT_SV
class mem_base_object;
bit [7:0] addr;
bit [7:0] data;
// Read = 0, Write = 1
bit rd_wr;
endclass
`endif

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@ -0,0 +1,5 @@
module top();
real a = 4.76;
real b = 0.74;
var type(a+b) c;
endmodule

3
testfiles/stm_import.sv Normal file
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@ -0,0 +1,3 @@
module chip;
import chip_pkg::*;
endmodule