update UT
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30cd26cab9
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1
Cargo.lock
generated
1
Cargo.lock
generated
@ -210,6 +210,7 @@ dependencies = [
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"once_cell",
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"once_cell",
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"path-clean",
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"path-clean",
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"pathdiff",
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"pathdiff",
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"percent-encoding",
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"regex",
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"regex",
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"ropey",
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"ropey",
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"serde",
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"serde",
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@ -8,6 +8,7 @@ edition = "2018"
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sv-parser = { version = "0.13.3", path = "sv-parser/sv-parser"}
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sv-parser = { version = "0.13.3", path = "sv-parser/sv-parser"}
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once_cell = "1.8"
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once_cell = "1.8"
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futures = "0.3"
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futures = "0.3"
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percent-encoding = "2.1.0"
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log = "0.4.19"
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log = "0.4.19"
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tower-lsp = "0.20.0"
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tower-lsp = "0.20.0"
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flexi_logger = "0.29.0"
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flexi_logger = "0.29.0"
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@ -4,6 +4,8 @@ use std::{collections::HashMap, io::BufReader};
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use std::path::PathBuf;
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use std::path::PathBuf;
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use anyhow::Error;
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use anyhow::Error;
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use log::info;
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use log::info;
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use percent_encoding::percent_decode_str;
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use std::env::consts::OS;
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use sv_parser::{parse_sv, unwrap_node, ConstantMintypmaxExpression, GateInstantiation, ListOfParameterAssignments, ListOfPortConnections, Locate, PackedDimensionRange, RefNode, SyntaxTree};
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use sv_parser::{parse_sv, unwrap_node, ConstantMintypmaxExpression, GateInstantiation, ListOfParameterAssignments, ListOfPortConnections, Locate, PackedDimensionRange, RefNode, SyntaxTree};
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use super::fast_hdlparam::{FastHdlparam, Macro};
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use super::fast_hdlparam::{FastHdlparam, Macro};
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@ -27,11 +29,26 @@ pub fn sv_parser(path: &str) -> Option<FastHdlparam> {
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}
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}
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pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Result<FastHdlparam, Error> {
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pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Result<FastHdlparam, Error> {
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// 对不同操作系统文件路径的支持
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let decoded_path = percent_decode_str(path.to_str().unwrap()).decode_utf8_lossy();
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let decoded_path_str = decoded_path.as_ref();
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let path = match OS {
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"windows" => {
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// 去掉开头的斜杠
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let trimmed_path_str = decoded_path_str.trim_start_matches('/');
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PathBuf::from(trimmed_path_str)
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},
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_ => {
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// 其他操作系统(如 Linux)保持原样
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PathBuf::from(decoded_path_str)
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},
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};
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let mut hdlparam = FastHdlparam {
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let mut hdlparam = FastHdlparam {
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fast_macro: Macro {
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fast_macro: Macro {
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defines: Vec::new(),
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defines: Vec::new(),
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errors: Vec::new(),
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errors: Vec::new(),
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includes: get_includes(path),
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includes: get_includes(&path),
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invalid: Vec::new()
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invalid: Vec::new()
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},
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},
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content: Vec::new()
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content: Vec::new()
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@ -71,7 +88,8 @@ pub fn make_fast_from_syntaxtree(syntax_tree: &SyntaxTree, path: &PathBuf) -> Re
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let replacement = match unwrap_node!(x, MacroText) {
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let replacement = match unwrap_node!(x, MacroText) {
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Some(RefNode::MacroText(x)) => Some(x.nodes.0),
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Some(RefNode::MacroText(x)) => Some(x.nodes.0),
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_ => None
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// TODO : 把下面的 contine 替换为 None 会报错
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_ => continue
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}.unwrap();
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}.unwrap();
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let (end_line, end_character) = (replacement.line, get_column_by_offset(&content, replacement.offset) + replacement.len);
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let (end_line, end_character) = (replacement.line, get_column_by_offset(&content, replacement.offset) + replacement.len);
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let replacement = syntax_tree.get_str(&replacement).unwrap();
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let replacement = syntax_tree.get_str(&replacement).unwrap();
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@ -602,10 +620,11 @@ fn get_column_by_offset(content: &[String], offset: usize) -> usize {
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#[cfg(test)]
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#[cfg(test)]
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mod tests {
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mod tests {
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use std::fs;
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use std::{fs, path::Path};
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use super::sv_parser;
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use super::sv_parser;
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const TESTFILES_DIR: &str = "testfiles";
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const TESTFILES_DIR: &str = "testfiles";
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const DIGTIAL_IDE_TEST: &str = "/home/dide/project/Digital-Test/Digital-IDE-test/user";
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macro_rules! unwrap_result {
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macro_rules! unwrap_result {
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($expr:expr) => {
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($expr:expr) => {
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@ -640,4 +659,42 @@ mod tests {
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}
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}
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}
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}
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}
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}
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#[test]
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fn test_digital_ide_test() {
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// 判断路径是否存在且为文件夹
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let path = Path::new(DIGTIAL_IDE_TEST);
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if path.exists() && path.is_dir() {
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// 递归遍历文件夹
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if let Err(e) = traverse_directory(path) {
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eprintln!("Error: {}", e);
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}
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} else {
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eprintln!("Path does not exist or is not a directory");
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}
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}
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fn traverse_directory(dir: &Path) -> Result<(), Box<dyn std::error::Error>> {
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if dir.is_dir() {
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for entry in fs::read_dir(dir)? {
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let entry = entry?;
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let path = entry.path();
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if path.is_dir() {
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// 递归遍历子文件夹
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traverse_directory(&path)?;
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} else if path.is_file() {
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// 检查文件扩展名
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if let Some(ext) = path.extension() {
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if ext == "v" || ext == "sv" {
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println!("Test file: {:?}", path);
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let file_path = path.to_str().unwrap();
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let _ = sv_parser(file_path);
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}
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}
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}
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}
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}
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Ok(())
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}
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}
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}
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51
testfiles/crc_functions.sv
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51
testfiles/crc_functions.sv
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@ -0,0 +1,51 @@
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//https://stackoverflow.com/questions/17647819/looking-for-a-crc-implementation-in-systemverilog
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module top;
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function byte calc_crc(byte unsigned cmd[]);
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bit [7:0] crc, d, c;
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int i;
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crc = 0;
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for (i=0; i<cmd.size(); i++) begin
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d = cmd[i];
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c = crc;
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crc[0] = d[7] ^ d[6] ^ d[0] ^ c[0] ^ c[6] ^ c[7];
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crc[1] = d[6] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[6];
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crc[2] = d[6] ^ d[2] ^ d[1] ^ d[0] ^ c[0] ^ c[1] ^ c[2] ^ c[6];
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crc[3] = d[7] ^ d[3] ^ d[2] ^ d[1] ^ c[1] ^ c[2] ^ c[3] ^ c[7];
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crc[4] = d[4] ^ d[3] ^ d[2] ^ c[2] ^ c[3] ^ c[4];
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crc[5] = d[5] ^ d[4] ^ d[3] ^ c[3] ^ c[4] ^ c[5];
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crc[6] = d[6] ^ d[5] ^ d[4] ^ c[4] ^ c[5] ^ c[6];
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crc[7] = d[7] ^ d[6] ^ d[5] ^ c[5] ^ c[6] ^ c[7];
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//$display("crc result: %h",crc);
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end
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return crc;
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endfunction
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localparam CRC32POL = 32'hEDB88320; /* Ethernet CRC-32 Polynom, reverse Bits */
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function automatic bit[31:0] genCRC32(input bit [7:0] databyte_stream[]);
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int unsigned i, j;
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bit [31:0] crc32_val = 32'hffffffff; // shiftregister,startvalue
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bit [7:0] data;
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//The result of the loop generate 32-Bit-mirrowed CRC
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for (i = 0; i < databyte_stream.size; i++) // Byte-Stream
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begin
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data = databyte_stream[i];
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for (j=0; j < 8; j++) // Bitwise from LSB to MSB
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begin
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if ((crc32_val[0]) != (data[0])) begin
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crc32_val = (crc32_val >> 1) ^ CRC32POL;
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end else begin
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crc32_val >>= 1;
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end
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data >>= 1;
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end
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end
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crc32_val ^= 32'hffffffff; //invert results
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return crc32_val;
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endfunction : genCRC32
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endmodule
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8
testfiles/hierarchical_name_of_type copy.sv
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8
testfiles/hierarchical_name_of_type copy.sv
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@ -0,0 +1,8 @@
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module ibex_alu #(
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parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BNone
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) (
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input ibex_pkg::alu_op_e operator_i,
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input logic [31:0] operand_a_i,
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input logic [31:0] operand_b_i);
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endmodule
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9
testfiles/mem_base_object.sv
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9
testfiles/mem_base_object.sv
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@ -0,0 +1,9 @@
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`ifndef MEM_BASE_OBJECT_SV
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`define MEM_BASE_OBJECT_SV
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class mem_base_object;
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bit [7:0] addr;
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bit [7:0] data;
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// Read = 0, Write = 1
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bit rd_wr;
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endclass
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`endif
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5
testfiles/operator_type.sv
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5
testfiles/operator_type.sv
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@ -0,0 +1,5 @@
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module top();
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real a = 4.76;
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real b = 0.74;
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var type(a+b) c;
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endmodule
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3
testfiles/stm_import.sv
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3
testfiles/stm_import.sv
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@ -0,0 +1,3 @@
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module chip;
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import chip_pkg::*;
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endmodule
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