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Author	SHA1	Message	Date
light-ly	3774068671	Merge branch 'main' into vhdl_project	2024-12-04 01:24:41 +08:00
light-ly	299e4dc031	refactor vhdl fast	2024-12-04 01:23:42 +08:00
LSTM-Kirigaya	d9fe1e9ed5	更加丰富的 vlog 的 sys task 补全	2024-12-03 22:10:10 +08:00
LSTM-Kirigaya	4dca88c5c1	更加丰富的 vlog 的 sys task 补全	2024-12-03 21:26:43 +08:00
light-ly	d8ddebc744	Merge branch 'vhdl_project' of https://github.com/Digital-EDA/digital-lsp-server into vhdl_project	2024-12-03 19:30:18 +08:00
light-ly	b52d69bdbb	fix new fast: stage	2024-12-03 17:24:01 +08:00
LSTM-Kirigaya	3690d88551	serde rename arch_name as archName	2024-12-03 17:15:35 +08:00
LSTM-Kirigaya	9c911a28d7	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-12-03 16:12:59 +08:00
LSTM-Kirigaya	f42739e8ec	add linter	2024-12-03 09:41:11 +08:00
light-ly	58eaaa824a	add arch name to module	2024-12-02 23:11:07 +08:00
LSTM-Kirigaya	509fd1a506	去除 vhdl_parser 中的补全项目	2024-12-02 00:30:03 +08:00
light-ly	99786868b9	fix vhdl name	2024-12-02 00:05:19 +08:00
light-ly	6cecb97555	add dot compeletion to vhdl	2024-12-01 23:16:39 +08:00
light-ly	01b59428c2	fix vhdl std path	2024-12-01 22:24:49 +08:00
light-ly	2fcfed4674	refactor vhdl lsp service	2024-11-27 03:25:55 +08:00
LSTM-Kirigaya	c40e66f3df	完成了 vhdl 的自动补全（关键词自动补全 + 自动例化）	2024-11-26 16:59:15 +08:00
Kirigaya	3f9d5ff1cc	save	2024-11-19 15:34:18 +08:00
Kirigaya	230ef10f59	实现 sync fast	2024-11-17 16:25:27 +08:00
LSTM-Kirigaya	83df59917f	fix copy scripts permission	2024-11-16 11:34:59 +08:00
light-ly	f325142046	fix datatype byte_idx out of range	2024-11-16 11:34:04 +08:00
light-ly	05621800a4	fix emu scope idx out of range	2024-11-16 11:18:05 +08:00
light-ly	989b66b737	skip architecture when there is no entity	2024-11-16 10:23:49 +08:00
light-ly	0aa6ef0462	change vhdl parse: only think of entity as module	2024-11-16 10:08:13 +08:00
Kirigaya	9bb54e0327	完成 CodeLens 的支持, Run | Test	2024-11-14 20:54:06 +08:00
Kirigaya	348214e42d	完成 CodeLens 的支持	2024-11-14 20:43:02 +08:00
LSTM-Kirigaya	b01ff8e371	完成 xilinx 原语适配	2024-11-14 16:18:47 +08:00
light-ly	ce267363fb	merge primitives completion to new completion code	2024-11-13 23:22:18 +08:00
light-ly	a11ce70bb4	Merge branch 'main' into dev	2024-11-13 23:03:06 +08:00
LSTM-Kirigaya	12e1b25f11	完成自动补全的 output 自动申明 | 完成配置文件的前后端更新系统	2024-11-13 22:52:27 +08:00
light-ly	8681f29ca7	fix write error	2024-11-13 22:49:35 +08:00
LSTM-Kirigaya	d45c243d62	完成自动补全的 output 自动申明 | 完成配置文件的前后端更新系统	2024-11-13 22:46:00 +08:00
light-ly	ec5e1f19c4	add primitives port/param auto completion	2024-11-13 22:45:18 +08:00
light-ly	82b4f6f092	add primitives auto instantiation	2024-11-13 22:24:07 +08:00
light-ly	290d1aec05	add primitives param hover	2024-11-13 02:25:59 +08:00
light-ly	41b2db2eba	add primitives port hover	2024-11-13 02:17:05 +08:00
light-ly	eb210bb3b7	add module hover for primitives	2024-11-12 23:08:08 +08:00
light-ly	397946438c	fix primitives module name | add primitives request	2024-11-12 23:05:43 +08:00
light-ly	6039bdf2c8	add primitive init	2024-11-12 21:45:24 +08:00
light-ly	2851c1dfa6	add deserialize function	2024-11-12 18:30:02 +08:00
light-ly	103baacb8f	fix primitive bug | add gen primitive bin to copy sh	2024-11-12 16:55:11 +08:00
LSTM-Kirigaya	935a852ba0	解决 vhdl 解析内容和内存中文本不一致的现象	2024-11-12 15:57:26 +08:00
LSTM-Kirigaya	15cfaccec1	将 vhdl	2024-11-12 15:56:29 +08:00
LSTM-Kirigaya	c8aa5e2dcc	完成 IP 的支持（还差自动补全）	2024-11-11 23:53:14 +08:00
LSTM-Kirigaya	5540b0b1f2	增加全局 conf 属性: extensionPath	2024-11-11 21:41:08 +08:00
light-ly	9dc59280e6	change some fuction to pub	2024-11-11 21:20:40 +08:00
LSTM-Kirigaya	9333ed0272	Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server	2024-11-11 21:06:21 +08:00
LSTM-Kirigaya	cbddc07bdc	xilinx IP 支持 | 增加全局 conf 属性	2024-11-11 21:06:12 +08:00
light-ly	eccde327d7	add primitive parser mod	2024-11-11 16:49:31 +08:00
LSTM-Kirigaya	f055b2bbc3	增加对于 xilinx IP 的 entity 内部 port 的解析	2024-11-11 02:06:41 +08:00
LSTM-Kirigaya	b14f8bd17f	规范 module 的 hover 和 definition 接口	2024-11-08 23:11:27 +08:00