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95632ace63
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更新字段
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2024-12-23 17:38:21 +08:00 |
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light-ly
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bdec500594
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fix vhdl arch range
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2024-12-22 22:27:01 +08:00 |
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light-ly
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173388df1b
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fix vhdl instance type
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2024-12-21 16:02:11 +08:00 |
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b09921473f
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修复 fast 中 endmodule 位置拿错的问题
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2024-12-19 22:15:00 +08:00 |
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c24b90ea96
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实现三种诊断模式
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2024-12-17 23:32:31 +08:00 |
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b9c8a2f451
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实现三种诊断模式
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2024-12-17 20:36:01 +08:00 |
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9119cfb0ed
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实现 did_close 事件
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2024-12-17 19:14:56 +08:00 |
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826d62dfbd
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实现 server 的 execute_command 管线,并实现前端主动发起 lint 请求
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2024-12-17 18:20:44 +08:00 |
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574c50325e
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完成返回诊断器的接口
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2024-12-16 01:24:09 +08:00 |
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fa7b42f09b
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更新文本缓冲区备份的索引模式 | 将 AST 的存储地点从 Sources 中移动到 HdlFile 内部
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2024-12-16 00:44:33 +08:00 |
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0cf07fd017
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修复 macro usage 无法跳转的问题
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2024-12-15 01:35:26 +08:00 |
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9688a330bf
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实现 endmodule 的 inlay hints
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2024-12-13 22:00:40 +08:00 |
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setsumi
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1142aa324f
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add directives comment
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2024-12-13 11:34:50 +00:00 |
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1090face1e
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更新 directives
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2024-12-13 18:10:27 +08:00 |
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aad333783e
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修复 system task 中几个未转义的命令 | 所有自动补全增加 label_details
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2024-12-13 01:56:02 +08:00 |
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20500a55ca
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更加完善的宏相关的自动补全
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2024-12-12 22:09:04 +08:00 |
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7cad6176b6
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update sv parser
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2024-12-12 21:25:19 +08:00 |
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7875a631a8
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剥离 scope tree 逻辑到 core 模块中
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2024-12-12 18:18:06 +08:00 |
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36ba7a350d
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更好的 vivado 诊断器
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2024-12-11 22:01:12 +08:00 |
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4db6837029
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完成 modelsim | vivado 的诊断
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2024-12-10 23:17:56 +08:00 |
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ae083bdad4
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完成 verilator 的诊断
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2024-12-10 19:15:39 +08:00 |
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f7caccc338
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Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server
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2024-12-10 18:35:37 +08:00 |
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7dd4f58da6
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完成 verilator 的诊断
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2024-12-10 18:35:29 +08:00 |
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light-ly
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3bdd727267
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fix vhdl project init
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2024-12-10 00:08:46 +08:00 |
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b1b302bbfb
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完成 iverilog 的诊断
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2024-12-09 23:07:18 +08:00 |
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19fed383b0
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Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server
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2024-12-09 19:33:39 +08:00 |
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f7583e465f
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完成 linter 的诊断 pipeline 架构实现
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2024-12-09 19:33:34 +08:00 |
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723ee40a4e
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完成 linter 的诊断 pipeline 架构实现
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2024-12-09 19:33:25 +08:00 |
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light-ly
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de587096b2
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fix bigfile parse error | remove vhdl test
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2024-12-07 15:47:46 +08:00 |
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e726fffd99
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完成诊断器架构重新设计
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2024-12-06 23:24:10 +08:00 |
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7824b74c9a
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完成 linter 后端请求接口和基本数据结构
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2024-12-05 23:53:38 +08:00 |
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8e2b373702
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添加 18.3.3 标准
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2024-12-04 17:50:42 +08:00 |
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c9b259570a
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merge
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2024-12-04 01:36:29 +08:00 |
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579684061a
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Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server
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2024-12-04 01:29:04 +08:00 |
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light-ly
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68a498da32
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sync Cargo.lock
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2024-12-04 01:25:43 +08:00 |
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light-ly
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3774068671
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Merge branch 'main' into vhdl_project
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2024-12-04 01:24:41 +08:00 |
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light-ly
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299e4dc031
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refactor vhdl fast
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2024-12-04 01:23:42 +08:00 |
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ac37cd3e2b
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save
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2024-12-04 00:57:59 +08:00 |
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setsumi
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539bb20112
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add sys_tasks.rs comment
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2024-12-03 16:12:11 +00:00 |
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d9fe1e9ed5
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更加丰富的 vlog 的 sys task 补全
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2024-12-03 22:10:10 +08:00 |
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4dca88c5c1
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更加丰富的 vlog 的 sys task 补全
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2024-12-03 21:26:43 +08:00 |
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light-ly
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d8ddebc744
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Merge branch 'vhdl_project' of https://github.com/Digital-EDA/digital-lsp-server into vhdl_project
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2024-12-03 19:30:18 +08:00 |
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light-ly
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b52d69bdbb
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fix new fast: stage
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2024-12-03 17:24:01 +08:00 |
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3690d88551
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serde rename arch_name as archName
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2024-12-03 17:15:35 +08:00 |
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9c911a28d7
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Merge branch 'main' of https://github.com/Digital-EDA/digital-lsp-server
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2024-12-03 16:12:59 +08:00 |
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f42739e8ec
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add linter
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2024-12-03 09:41:11 +08:00 |
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light-ly
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58eaaa824a
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add arch name to module
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2024-12-02 23:11:07 +08:00 |
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509fd1a506
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去除 vhdl_parser 中的补全项目
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2024-12-02 00:30:03 +08:00 |
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light-ly
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99786868b9
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fix vhdl name
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2024-12-02 00:05:19 +08:00 |
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light-ly
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6cecb97555
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add dot compeletion to vhdl
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2024-12-01 23:16:39 +08:00 |
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