57 lines
1.2 KiB
Verilog
57 lines
1.2 KiB
Verilog
/* @meta
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* Create Date : 2/6/2025 14:58
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* Author : nitcloud
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* Target Device : [Target FPGA and ASIC Device]
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* Tool Versions : vivado 18.3 & DC 2016
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* Revision Historyc :
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* Revision :
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* 04/12 0.01 - File Created
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* Description :
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* Company : ncai Technology .Inc
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* Copyright : 1999, ncai Technology Inc, All right reserved
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*/
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/* @module
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* Netlist : level-1
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* FSMView : on
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* Overview: 4-stage pipelined accumulator.
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*/
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/*
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* 这是一些简单的文字，可以随意渲染
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* :::info
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* 请注意版权问题
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* :::
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*
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* 使用 C 语言如此进行简单的编译
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* ```c
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* int main() {
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* return 0;
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* }
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* ```
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*/
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/* @wavedrom accuml this is accuml wavedrom
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{signal: [
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{name: 'clock', wave: '10101010101010101'},
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{name: 'reset', wave: '10...............'},
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{name: 'clr', wave: '01.0.............'},
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{name: 'idata', wave: 'x3...............', data: ['5']},
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{name: 'odata', wave: 'x........5.5.5.5.', data: ['5','10','25','30']},
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]}
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*/
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module adder(
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// 这是一个简单的注释
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// 这是它们的第二行注释
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input a,
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input b,
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// 这是输出信号
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output c,
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);
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// 具体的代码实现
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meta_add u_meta_add(a, b, c);
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endmodule |