Revert "sv-parser support parse class declare"

This reverts commit 9015bb0a95a6843e00e4017023c7ad2f6ea33a91.

sv-parser-parser/src/source_text/system_verilog_source_text.rs

@@ -50,9 +50,6 @@ pub(crate) fn description(s: Span) -> IResult<Span, Description> {
         map(config_declaration, |x| {
             Description::ConfigDeclaration(Box::new(x))
         }),
-        map(class_declaration, |x| {
-            Description::ClassDeclaration(Box::new(x))
-        }),
     ))(s)
 }
 

sv-parser-pp/src/preprocess.rs

@@ -1339,36 +1339,4 @@ endmodule
         );
         assert_eq!(ret.origin(80).unwrap().1, 60);
     }
-
-
-    #[test]
-    fn test21() {
-        let include_paths = [get_testcase("")];
-        let (ret, _) = preprocess(
-            get_testcase("test21.sv"),
-            &HashMap::new(),
-            &include_paths,
-            false,
-            false,
-        )
-        .unwrap();
-    }
-
-    #[test]
-    fn test22() {
-        let include_paths = [get_testcase("")];
-        let (ret, _) = preprocess(
-            get_testcase("test22.sv"),
-            &HashMap::new(),
-            &include_paths,
-            false,
-            false,
-        )
-        .unwrap();
-    }
-
-
-
-
-
 }

sv-parser-pp/testcases/test21.sv

@@ -1,7 +0,0 @@
-class test21 extends base_class /* base class*/;
-	int a;
-	int b;
-	function int funcname();
-		return 2;
-	endfunction : funcname
-endclass : test21

sv-parser-pp/testcases/test22.sv

@@ -1,18 +0,0 @@
-// it's for test
-
-`ifndef ABCD
-`define ABCD
-
-package my_package;
-
-	import uvm_pkg::*;
-	import internal_pkg::*;
-
-	// include 
-	`include "test21.sv"
-
-	
-endpackage : my_package
-
-
-`endif

sv-parser-syntaxtree/src/source_text/system_verilog_source_text.rs

@@ -23,7 +23,6 @@ pub enum Description {
     PackageItem(Box<DescriptionPackageItem>),
     BindDirective(Box<DescriptionBindDirective>),
     ConfigDeclaration(Box<ConfigDeclaration>),
-    ClassDeclaration(Box<ClassDeclaration>),
 }
 
 #[derive(Clone, Debug, PartialEq, Node)]