merge original test files

Draft/quote.v

@@ -0,0 +1,15 @@
+module main();
+    
+    
+    // outports wire
+    wire         	clkout;
+    
+    clkdiv u_clkdiv(
+        .clk50  	( clk50   ),
+        .rst_n  	( rst_n   ),
+        .clkout 	( clkout  )
+    );
+    
+    
+    
+endmodule //main

Draft/test.v

@@ -0,0 +1,47 @@
+module clkdiv(
+    input clk50,
+    input rst_n,
+    output reg clkout
+);
+    reg [15:0] cnt;
+    always @(posedge clk50 or negedge rst_n)
+    begin
+        if(!rst_n)
+        begin
+            cnt <= 16'b0;
+            clkout <= 1'b0;
+        end
+        else if(cnt == 16'd162) 
+        begin
+            clkout <= 1'b1;
+            cnt <= cnt + 16'd1;
+        end
+            else if(cnt == 16'd325) 
+        begin
+            clkout <= 1'b0;
+            cnt <= 16'd0;
+        end
+            else 
+        begin
+            cnt <= cnt + 16'd1;
+        end
+    end
+endmodule
+
+
+
+// module des_sample (
+//     input            clk,
+//     input            rst,
+//     output reg [7:0] nums
+// );
+
+//     always @(posedge clk or negedge rst) begin
+//         if (!rst) begin
+//             nums = 8'h00;
+//         end else begin
+//             nums = nums + 1;
+//         end
+//     end
+
+// endmodule

MipsDesign/.gitignore

@@ -0,0 +1,4 @@
+*.vcd
+*.jpg
+*.out
+*.pdf

MipsDesign/.vscode/property.json

@@ -0,0 +1,25 @@
+{
+	"toolChain": "xilinx",
+	"prjName": {
+		"PL": "template"
+	},
+	"soc": {
+		"core": "none"
+	},
+	"enableShowLog": false,
+	"device": "none",
+	"arch": {
+		"hardware": {
+			"src": "./src",
+			"sim": "./sim"
+		}
+	},
+    "iverilogCompileOptions": {
+        "standard": "2012",
+        "includes": [
+            "${workspace}/src",
+            "${workspace}/src/Controller",
+            "${workspace}/src/DataPath"
+        ]
+    }
+}

MipsDesign/README.md

@@ -0,0 +1,118 @@
+# 五级流水线（带冒险和异常处理）
+
+### 项目结构
+
+```
+multistage_pipeline
+	|-> data:		 	IM和DM读入的地方
+	|-> figure:      	设计图纸，我高兴时可能会写写使用说明
+	|-> Python:		 	一些加速生产的脚本
+	|-> mips_code:   	用来测试的mips汇编源代码
+	|-> sim:		    放激励文件的文件夹
+	|-> src
+		|-> Controller: 控制器
+		|-> DataPath:   数据通路
+		|-> Hazard:		旁路模块与冒险检测模块
+		|-> Pipe:		流水线寄存器
+		|-> Utils:		其余组件
+		|-> myCpu.v:	顶层模块
+	
+	|-> README.md:   	Current 
+	|-> .gitignore		上传文件过滤列表
+```
+
+### 设计图纸(2021.5.17更新)
+
+![](./figure/五级流水线.png)
+
+
+
+---
+
+## 日志
+
+### 2021.5.17
+
+从前两次的设计中，体会到一点：一个正确的，完备的思路对于一个不小的项目来说是多么的重要。因此，这次为了轻松愉悦的开发过程，我花了许久（6个小时左右）设计了最终带转发，冒险和异常检测的五级流水线图纸。并且吸取了部分DUAN学长的FPGA项目习惯。
+
+祝成功！
+
+
+### 2021.5.18
+
+在实现乘除法指令(`MULT,DIV,MULTU,DIVU`)时，我发现了一个问题，那就是乘除法指令的输出是一个63位的数字，虽然实际上乘除法只是改变专用寄存器的值，但是我对专用寄存器的设计使得我每个时钟周期只能改变`$hi`和`$lo`中的某一个。我的电路无法在一个时钟周期内一次性改变`$hi`和`$lo`。总得满足我的乘除法指令吧？怎么办呢？我的做法比较简单粗暴，我为`ALU`增加了一个输出接口`prod`，这个接口值和MIPS32指令手册上描述乘法除法中的prod的含义一样，为了让它能够成功抵达`regfile`，并成功写入，我做出了如下的改变：
+
+- `ALU`增加新的输出接口值`prod`，当然，相应的后续流水线寄存器中也会添加暂存prod的接口。
+- 选择目的操作数寄存器编号的`mux1`增加一个选项：34，不同于0-33，34不代表任何一个寄存器的编号，而是告诉我们的regfile，你要拆分并读入流水线存入的prod值。
+- `regfile`增加一个输入接口`MEM_WB_prod`，代表接受最后一个流水线寄存器的存储的prod值。然后在`regfile`内部，我增加了写寄存器的逻辑：增加一个34号，如果接受到的目的操作数编号（在我的设计中为`MEM_WB_mux1_out`）为34，则将prod拆成两块送给`$hi`和`$lo`。
+
+> 是否有更好的解决方案呢？
+
+### 2021.5.26
+
+果然，在实现57条指令的过程中，我发现了一个问题，由于我对专用寄存器`$hi`和`$lo`的是走的专线，所以导致这两个家伙没有进入我的数据冒险系统中。也就是说，如果我的上一条指令改变了专用寄存器的值，而下一条指令又需要使用专用寄存器的值，那么就会发生错误，因为此时下一条指令拿到的`$hi`或者`$lo`并不是最新的。为了解决这个问题，我采用了简单粗暴的方法：为EX阶段的保存专用寄存器的线(`ID_EX_low_out`和`ID_EX_high_out`)增加旁路。需要注意的是，我的垃圾设计的缺点这个时候就体现出来了，因为存储最新的专用寄存器值得地方可以是专用寄存器专用线，也可以是prod，所以嘛。。。在写旁路时旁路单元输出旁路信号的逻辑会有一点点小的改变，旁路选择的选项也从原本的3个（EX_MEM阶段的源操作数值、MEM_WB阶段的源操作数值、原本的值，也就是ID_EX阶段源操作数的值）变为5个（增加了EX_MEM阶段的prod和MEM_WB阶段的prod），因此旁路单元输出的旁路信号的位数从原本的2位变成3位。
+
+
+### 2021.5.26
+
+中间事情真的很多，所以只能断断续续地更新了。在我的想法下，今天完成了57条指令的全数据通路和控制器的连接，接下来就只剩调试了。有时间我得将已经被我改得面目全非的设计图纸的visio原文件修改同步更新一下了。
+
+### 2021.5.30
+
+开始进行整体测试，今天先测试所有的R型指令，遇到了pc启动的问题，我将reset设置为了上升沿，并且将`pc.v`修改如下：
+
+```verilog
+    // initial 
+    always @(posedge reset) begin
+        pc_out <= initial_addr;
+    end
+
+    always @(posedge clock && reset == 1) begin
+        if (!OR1_out)              // OR1_out represents stall or not
+            pc_out <= npc_out;
+    end
+```
+
+也就是将初始化和持续更新分开来。
+
+除此之外，用来用来软堵塞pc的`OR1_out`和`OR2_out`一开始都是x，会使得pc在启动时不更新，所以需要对两个冒险模块初始化其输出信号，使得一开始输出的都是不堵塞的信号。
+
+### 2021.5.31
+
+5月的最后一天，我已经完成了所有R型指令的测试、旁路测试和冒险测试。debug过程中发现一个问题：和之前一样，尽量别写形如`posedge clock or posedge reset`，请把初始化的always块另外写，因为我这边默认是reset上升沿触发模块的初始化操作，但是如果你将reset信号与别的信号混在一起写，就会导致模块永远处于更新状态，对于我的`regfile`，这意味着，每当后续的上升沿来临时，寄存器堆中所有的寄存器都会清零。
+
+**第二个值得记载的bug**就是有关branch类型指令的问题，在pro1和pro2中的branch信号中，我最终的目标地址是通过branch当前的相对位移`>>2`和基地址相加得到的，但是pro3在我的设计中，branch在ID阶段得到的`pc_add_out`是当前IF阶段的`pc_add_out`，而不是随着当前这条branch指令得到的。因此在使用branch跳转时使用的`pc_add_out`必须减四才能正确。
+
+**第三个值得记载的bug**
+
+对于跳转指令的堵塞，有一个很隐蔽的bug，在控制冒险时，当我们为了branch指令的操作数而软阻塞ID阶段和IF阶段的指令时，由于使用的是延迟槽的机制，虽然我们阻塞了ID和IF，但是判断是否冲刷的模块还是在正常工作。所以如果堵塞的branch指令是生效，是需要跳转的，那么在堵塞的第一个周期，IF_ID流水线寄存器中保存的ID阶段的指令就会被冲刷成空指令，这会使得第二个堵塞周期结束，电路回归正常时，branch会去解析空指令，从而使得pc变成0（这根据你提供的空指令的后16位决定，我使用的是`addi $t0, $zero, 0`，其后16位为0）.所以有必要控制堵塞IF_ID流水线寄存器的信号和冲刷IF_ID流水线寄存器的信号的优先级：**当且仅当IF_ID流水线寄存器不被堵塞时，IF_ID才能执行冲刷的操作**。根据这样的认识，我们可以只修改代码逻辑而不添加额外的信号得修复这个bug：
+
+```verilog
+    always @(posedge clock) 
+    begin
+        if (OR4_out)
+            IF_ID_im_out = NOP;         // use NOP to flush and the pc_add_out won't be used later, so we don't care about pc_add_out there
+        
+        else if (!OR2_out)               // update iff IF_ID_Write
+        begin
+            IF_ID_im_out = im_out;
+            IF_ID_pc_add_out = pc_add_out;
+        end
+    end
+```
+
+更改之后
+
+```verilog
+    always @(posedge clock) 
+    begin
+        if (!OR2_out)                // update iff IF_ID_Write
+        begin
+            if (OR4_out)
+                IF_ID_im_out = NOP;  // use NOP to flush and the pc_add_out won't be used later, so we don't care about pc_add_out there
+            else
+                IF_ID_im_out = im_out;
+            IF_ID_pc_add_out = pc_add_out;
+        end
+    end
+```

MipsDesign/data/r_text

@@ -0,0 +1,27 @@
+3c011001
+34300000
+24110006
+20120000
+0251402a
+11000015
+20130000
+02324022
+20090001
+01094022
+0268482a
+1120000d
+00135080
+020a5020
+8d480000
+8d490004
+0128582a
+11600005
+01006020
+01204020
+01804820
+ad480000
+ad490004
+22730001
+08100007
+22520001
+08100004

MipsDesign/mipcs_code/bubble.asm

@@ -0,0 +1,52 @@
+# data
+.data
+v : .word 4 3 1 6 2 5           # v is the beginning of a array, whose storage type is a word(four bytes)
+    
+# code
+.text
+.globl main
+# main parameter:
+# $s0 -> v
+# $s1 -> n
+# $s2 -> i
+# $s3 -> j
+
+main:
+    la      $s0, v                  # assign base address of v to $a0 (first parameter) 
+    addiu   $s1, $zero, 6           # assign 6 to the second parameter, which means the number of the array v
+    addi    $s2, $zero, 0           # int i = 0, save i to $s2 and j to $s3
+
+loop1:          # first layer of loop
+    slt     $t0, $s2,   $s1         # t0 == 1 if $s2(i) < $s1(n) else t0 == 0
+    beq     $t0, $zero, skip1       # if t0 == 0, which means i >= n, we skip out loop1
+    addi    $s3, $zero, 0           # int j = 0
+
+loop2:          # second layer of loop
+    sub     $t0, $s1,   $s2   
+    addi    $t1, $zero, 1
+    sub     $t0, $t0,   $t1         # save n - i - 1 to $t0
+    slt     $t1, $s3,   $t0         # t1 == 1 if $s3(j) < $t0(n - i - 1) else t1 == 0
+    beq     $t1, $zero, skip2       # if t1 == 0, which means j >= n - i - 1, we skip out loop2
+
+    sll     $t2, $s3,   2           # base address shamt of v[j]
+    add     $t2, $s0,   $t2	     # base address of v[j]
+    lw      $t0, 0($t2)             # v[j]
+    lw      $t1, 4($t2)             # v[j + 1]
+    slt     $t3, $t1, $t0           # t3 == 1 if $t1(v[j + 1]) < $t0(v[j]) else t3 == 0
+    beq     $t3, $zero, continue    # if t3 == 0, we don't need to do the swap, continue
+    add     $t4, $t0, $zero         # temp = a[j]
+    add     $t0, $t1, $zero         # a[j] = a[j + 1]
+    add     $t1, $t4, $zero         # a[j + 1] = temp
+    sw      $t0, 0($t2)
+    sw      $t1, 4($t2)
+
+continue:
+    addi    $s3, $s3,  1            # j ++
+    j       loop2
+
+skip2:          # skip out loop2
+    addi    $s2, $s2,  1            # i ++
+    j       loop1
+
+skip1:          # skip out loop1
+    

MipsDesign/mipcs_code/test_branch.asm

@@ -0,0 +1,78 @@
+# author : Yaning Li
+addi   $s1, $zero, 1
+addi   $s2, $zero, 2
+addi   $s3, $zero, 1
+addi   $t1, $zero, 1
+addi   $t1, $zero, 1
+addi   $t1, $zero, 1
+addi   $t1, $zero, 1
+addi   $t1, $zero, 1
+beq    $s1, $s2,   test1    # not
+addi   $t1, $zero, 2
+addi   $t1, $zero, 2
+addi   $t1, $zero, 2
+
+back1:
+addi   $t1, $zero, 3
+addi   $t1, $zero, 3
+addi   $t1, $zero, 3
+beq    $s1, $s3,   test2    # yes
+addi   $t1, $zero, 3
+addi   $t1, $zero, 3
+addi   $t1, $zero, 3
+
+back2:
+addi   $t1, $zero, 4
+addi   $t1, $zero, 4
+addi   $t1, $zero, 4
+bne    $s1, $s2,   test3    # yes
+addi   $t1, $zero, 4
+addi   $t1, $zero, 4
+addi   $t1, $zero, 4
+
+back3:
+addi   $t1, $zero, 5
+addi   $t1, $zero, 5
+addi   $t1, $zero, 5
+bne    $s1, $s3,   test4    # no
+addi   $t1, $zero, 5
+addi   $t1, $zero, 5
+addi   $t1, $zero, 5
+
+back4:
+j end
+addi   $t1, $zero, 6
+addi   $t1, $zero, 6
+addi   $t1, $zero, 6
+
+test1:
+addi   $s4, $s1,   1
+j      back1
+addi   $t1, $zero, 0
+addi   $t1, $zero, 0
+addi   $t1, $zero, 0
+
+
+test2:
+addi   $s4, $s1,   1
+j      back2
+addi   $t1, $zero, 0
+addi   $t1, $zero, 0
+addi   $t1, $zero, 0
+
+
+test3:
+addi   $s4, $s1,   1
+j      back3
+addi   $t1, $zero, 0
+addi   $t1, $zero, 0
+addi   $t1, $zero, 0
+
+test4:
+addi   $s4, $s1,   1
+j      back4
+addi   $t1, $zero, 0
+addi   $t1, $zero, 0
+addi   $t1, $zero, 0
+
+end:

MipsDesign/mipcs_code/test_forward1.asm

@@ -0,0 +1,44 @@
+# test forward1 and left branch command
+f1:
+addi   $s1, $zero, 1
+addi   $s2, $zero, 1
+addi   $s3, $zero, 0
+beq    $s1, $s2,   f3	# branch to f3
+
+f2:
+addi   $s1, $zero, -2
+addi   $s3, $zero, 0
+bltz   $s1, f4
+
+
+f3:
+addi   $s1, $zero, 1
+addi   $s2, $zero, 2
+addi   $s3, $zero, 0
+bne    $s1, $s2,   f2
+
+f4:
+addi   $s1, $zero, -1
+addi   $s3, $zero, 0
+bltzal $s1, f5
+
+final:
+jr     $ra		# to f6
+
+f5:
+addi   $s1, $zero, -1
+addi   $s3, $zero, 0
+bgez   $s1, end		# no jump
+addi   $s1, $zero, 1
+addi   $s3, $zero, 0
+blez   $s1, end		# no jump
+bgtz   $s1, f6
+
+j      end			# no exetable
+
+f6:
+addi   $s1, $zero, 1
+addi   $s3, $zero, 0
+bgezal $s1, final
+
+end:

MipsDesign/mipcs_code/test_forward2.asm

@@ -0,0 +1,27 @@
+# test forward unit2
+addi  $s1, $zero, 1		# s1 = 1
+addi  $s2, $zero, 2		# s2 = 2
+add   $s3, $s1  , $s2		# s3 = 3
+
+sub   $s1, $zero, $s1		# s1 = -1									
+sub   $s3, $s1  , $s2		# s3 = -3
+
+
+addi  $s1, $zero, 30		# s1 = 30
+addi  $s2, $zero, 2		# s2 = 2
+mult  $s1, $s2			# {hi, lo} = 60
+
+addi  $s1, $zero, 60		# s1 = 60
+addi  $s2, $zero, 15		# s2 = 15
+div   $s1, $s2			# {hi, lo} = {0, 4}
+
+
+addi  $s1, $zero, 1		# s1 = 1
+addi  $s1, $s1,   2		# s1 = 3
+addi  $s1, $s1,   3		# s1 = 6
+
+addi  $s1, $zero, 20		# s1 = 20
+addi  $s2, $zero, 10		# s2 = 10
+mult  $s1, $s2			# {hi, lo} = 200
+mflo  $s1			# s1 = lo = 200
+add   $s3, $s1, $s2		# s3 = s1 + s2 = 210

MipsDesign/mipcs_code/test_hazard1.asm

@@ -0,0 +1,45 @@
+# test hazard1
+# load base addr
+addi   $t0, $zero, 0x1001
+sll    $t0, $t0,   16
+f1:
+addi   $s1, $zero, 1
+addi   $s2, $zero, 1
+beq    $s1, $s2,   f3	# branch to f3
+
+f2:
+addi   $s1, $zero, -2
+bltz   $s1, f4
+
+
+f3:
+addi   $s1, $zero, 1
+addi   $s2, $zero, 2
+addi   $s3, $zero, 0
+bne    $s1, $s2,   f2
+
+f4:
+addi   $s1, $zero, -1
+bltzal $s1, f5
+
+final:
+jr     $ra		# to f6
+
+f5:
+addi   $s1, $zero, -1
+bgez   $s1, end		# no jump
+addi   $s1, $zero, 1
+blez   $s1, end		# no jump
+bgtz   $s1, f6
+
+j      end			# no exetable
+
+f6:
+addi   $s1, $zero, 3
+sw     $s1, 0($t0)
+lw     $s2, 0($t0)
+bgezal $s2, final
+
+end:
+addi   $s1, $s1, -1
+bgezal $s1, end

MipsDesign/mipcs_code/test_hazard2.asm

@@ -0,0 +1,11 @@
+# test  Hazard Detection Unit2, which is mainly load-use
+
+addi  $t0, $zero, 0x1001     # addr
+sll   $t0, $t0, 16
+addi  $s1, $zero, 1000       # s1 = 0x3e8
+addi  $s2, $zero, 8          # s2 = 8
+
+sw    $s1, 0($t0)
+addi  $s1, $zero, 12	     # s1 = 12
+lw    $s1, 0($t0)	         # s1 = 0x3e8
+srlv  $s3, $s1, $s2	         # s3 = 0x3

MipsDesign/mipcs_code/test_j.asm

@@ -0,0 +1,16 @@
+# author : Yaning Li
+addi    $s1,   $zero, 1
+addi    $s2,   $zero, 2
+lui     $zero, 0
+
+j       jaltest
+lui     $zero, 0
+
+back:
+addi    $s3,   $zero, 1
+lui     $zero, 0
+
+jaltest:
+addi    $s4,   $s1,   1
+j       back
+addi    $s1,   $s1,   0

MipsDesign/mipcs_code/test_jal_jr.asm

@@ -0,0 +1,11 @@
+addi $s1,$zero,1
+addi $s2,$zero,2
+jal  test1
+addi $s3,$zero,1
+j end
+
+test1:
+addi $s4,$s1,1
+jr   $ra
+
+end:

MipsDesign/mipcs_code/test_lw_sw.asm

@@ -0,0 +1,48 @@
+.data
+word : .word 0x8fffffff 0x6eeeeeee 0x21110000
+half : .half 0x8bbb 0x6ccc 0x2111
+byte : .byte 0x8a 0x7e 0x32
+
+.text
+
+# load base addr
+lui   $at,         0x00001001
+ori   $t0, $at,    0x00000000
+
+addi  $t1, $zero,  8
+
+lw    $s0, 0($t0)
+lw    $s1, 4($t0)
+lw    $s2, 8($t0)
+
+sw    $t1, 0($t0)
+sw    $t1, 4($t0)
+sw    $t1, 8($t0)
+
+# load base addr
+lui   $at,         0x00001001
+ori   $t0, $at,    0x0000000c
+
+addi  $t1, $zero,  8
+
+lh    $s0, 0($t0)
+lh    $s1, 2($t0)
+lh    $s2, 4($t0)
+
+sh    $t1, 0($t0)
+sh    $t1, 2($t0)
+sh    $t1, 4($t0)
+
+# load base addr
+lui   $at,         0x00001001
+ori   $t0, $at,    0x00000012
+
+addi  $t1, $zero,  8
+
+lb    $s0, 0($t0)
+lb    $s1, 1($t0)
+lb    $s2, 2($t0)
+
+sb    $t1, 0($t0)
+sb    $t1, 1($t0)
+sb    $t1, 2($t0)

MipsDesign/mipcs_code/test_r.asm

@@ -0,0 +1,54 @@
+# author : Yaning Li
+# integate : Zhelong Huang
+addi    $s1, $zero, 1       # s1 = s1 + 1    = 0x0000_0001
+addi    $s2, $zero, 2       # s2 = s2 + 2    = 0x0000_0002
+addi    $s1, $zero, 3       # s1 = s1 + 3    = 0x0000_0003
+addi    $s2, $zero, 4       # s2 = s2 + 4    = 0x0000_0004
+addiu   $s1, $zero, 5       # s1 = s1 + 5    = 0x0000_0005
+addiu   $s2, $zero, 6       # s2 = s2 + 6    = 0x0000_0006
+# for block
+addiu   $s3, $zero, 1
+addiu   $s3, $zero, 1
+addiu   $s3, $zero, 1
+
+add     $s3, $s1,   $s2     # s3 = 5 + 6     = 0x0000_000b
+addu    $s3, $s1,   $s2     # s3 = 5 + 6     = 0x0000_000b
+sub     $s3, $s2,   $s1     # s3 = 6 - 5     = 0x0000_0001
+subu    $s3, $s2,   $s1     # s3 = 6 - 5     = 0x0000_0001
+and     $s3, $s1,   $s2     # s3 = 5 & 6     = 0x0000_0004
+or      $s3, $s1,   $s2     # s3 = 5 | 6     = 0x0000_0007
+nor     $s3, $s1,   $s2     # s3 = ~(5 | 6)  = 0xffff_fff8
+xor     $s3, $s1,   $s2     # s3 = 5 ^ 6     = 0x0000_0003
+slt     $s3, $s1,   $s2     # s3 = (s1 < s2) = 0x0000_0001
+slt     $s3, $s2,   $s1     # s3 = (s2 < s1) = 0x0000_0000
+sltu    $s3, $s1,   $s2     # s3 = (s1 < s2) = 0x0000_0001
+sltu    $s3, $s2,   $s1     # s3 = (s2 < s1) = 0x0000_0000
+
+andi    $s3, $s1,   3       # s3 = s1 & 3    = 0x0000_0001
+ori     $s3, $s1,   2       # s3 = s1 | 2    = 0x0000_0007
+xori    $s3, $s2,   3       # s3 = s2 ^ 3    = 0x0000_0005
+slti    $s3, $s2,   1       # s3 = (s2 < 1)  = 0x0000_0000
+sltiu   $s3, $s2,   9       # s3 = (s2 < 9)  = 0x0000_0001
+sll     $s3, $s1,   2       # s3 = s1 << 2   = 0x0000_0014
+srl     $s3, $s2,   1       # s3 = s2 >> 1   = 0x0000_0003
+
+lui     $s4, 32768          # s4 = {32768, {161'b0}} = 0x8000_0000
+lui     $s4, 32768
+lui     $s4, 32768
+lui     $s4, 32768
+
+sra     $s3, $s4,   4       # s3 = s4 >> 4   = 0xf800_0000
+
+sllv 	$s3, $s2, $s1	    # s3 = GPR[s2] << GPR[s1]
+srlv    $s3, $s2, $s1
+srav	$s3, $s2, $s1
+
+mult    $s1, $s2
+multu   $s1, $s2
+div     $s2, $s1
+divu    $s2, $s1
+
+mthi    $s1
+mtlo    $s2
+mfhi    $s3
+mflo    $s3

MipsDesign/mipcs_code/test_with.asm

@@ -0,0 +1,148 @@
+test_addi:
+add   $s1, $0, 0
+add   $s2, $0, 0
+add   $s0, $0, 100
+addi  $s3, $1, -100
+
+test_addiu:
+addiu $s4, $s0, -1000
+
+test_andi:
+andi  $s5, $s0, 1010
+
+test_ori:
+ori   $s1, $s2, 100
+
+test_xori:
+xori  $s5, $s2, 100
+
+test_sltiu:
+sltiu $s4, $s5, 100
+
+test_add:
+add   $s1, $s2, $s3
+ 
+test_addu:
+add   $s1, $s1, $s2
+
+test_sub:
+sub   $s1, $s2, $s3
+
+test_subu:
+subu  $s3, $s2, $s2
+
+test_and:
+and   $s4, $s5, $s2
+
+test_or:
+or    $s2, $s3, $s1
+
+test_nor:
+nor   $s2, $s3, $s4
+
+test_xor:
+xor   $s4, $s3, $s2
+
+test_slt:
+slt   $s0, $s2, $s3
+
+test_sltu:
+sltu  $s1, $s3, $s5
+
+save_test_result:
+addi  $s6, $0,  0x1001
+sll   $s6, $s6, 16
+
+sw    $s0, 0($s6)
+sw    $s1, 4($s6)
+sw    $s2, 8($s6)
+sw    $s3, 12($s6)
+sw    $s4, 16($s6)
+sw    $s5, 20($s6)
+
+addi 	$t0, $0, 0xffffffff
+
+addi  $t1, $0,  0x1001
+sll   $t1, $t1, 16
+
+sw	$t0, 0($t1)
+
+addi	$t1, $t1, 4
+
+sh	$t0, 0($t1)
+
+addi	$t1, $t1, 4
+
+sb	$t0, 0($t1)
+
+lw	$t2, 0($t1)
+
+addi	$t1, $t1, 4
+
+sw	$t2, 0($t1)		
+
+lh	$t2, 0($t1)
+
+addi	$t1, $t1, 4
+
+sw	$t2, 0($t1)	
+
+lhu	$t2, 0($t1)
+
+addi	$t1, $t1, 4
+
+sw	$t2, 0($t1)	
+
+lb	$t2, 0($t1)
+
+addi    $t1, $t1, 4
+
+sw	$t2, 0($t1)		
+
+lbu	$t2, 0($t1)
+
+addi	$t1, $t1, 4
+
+sw	$t2, 0($t1)	
+
+lui	$t3, 0xffff
+
+addi	$t1, $t1, 4
+
+sw	$t2, 0($t1)	
+
+sll	$t3, $t3, 2
+
+addi	$t1, $t1, 4
+
+sw	$t3, 0($t1)	
+
+sra	$t3, $t3, 2
+
+addi	$t1, $t1, 4
+
+sw	$t3, 0($t1)	
+
+srl	$t3, $t3, 2
+
+test_j:
+addi    $t2, $0, 60
+
+addi	$t2, $t2, 60
+
+beq     $t2, 120, test_beq
+
+bne     $t2, 180, test_j
+
+sw	$t3, 0($t1)
+
+test_beq:
+jal     test_jal
+
+j       end
+
+test_jal:
+jr      $ra
+
+
+end:

MipsDesign/run.bat

@@ -0,0 +1,2 @@
+iverilog -T min -o ./sim/testBench.v.out ./sim/testBench.v
+vvp ./sim/testBench.v.out

MipsDesign/run.sh

@@ -0,0 +1,3 @@
+#!/bin/bash
+iverilog -T min -o ./sim/testBench.v.out ./sim/testBench.v
+vvp ./sim/testBench.v.out

MipsDesign/sim/testBench.v

@@ -0,0 +1,25 @@
+`include "../src/MyCpu.v"
+
+module testBench();
+    reg clock;
+    reg reset;
+
+    initial begin
+        $display("begin simulate");
+        $dumpfile("../simulation/icarus/wave.vcd"); 
+        $dumpvars;
+        clock = 0;
+        reset = 0;
+        #20 reset = ~reset;
+        #30000 $finish;    
+    end
+
+    MyCpu u_MyCpu(
+        .clock(clock),
+        .reset(reset)
+    );
+
+    always #20 clock = ~clock;
+
+endmodule
+

MipsDesign/src/Controller/controller.v

@@ -0,0 +1,233 @@
+module controller #( 
+    /*
+        field of all one bit signal
+    */
+    parameter T          = 1'b1,
+    parameter F          = 1'b0,
+    /*
+        field of use_stage
+        0 : be used in ID
+        1 : be used in EX
+    */
+    parameter ID = 1'b0,
+    parameter EX = 1'b1,
+    /*
+        LS_bit field
+        value to tell the difference between word, half word and btye
+    */
+    parameter NONE       = 2'b00,
+    parameter WORD       = 2'b01,
+    parameter HALF       = 2'b10,
+    parameter BYTE       = 2'b11,    
+    /*
+        Branch field
+        tag to distinguish Branch
+    */
+    parameter BEQ        = 4'b0000,              // branch equal
+    parameter BNE        = 4'b0001,              // branch not equal 
+    parameter BGEZ       = 4'b0010,              // branch greater than or equal to zero
+    parameter BGTZ       = 4'b0011,              // branch greater than zero
+    parameter BLEZ       = 4'b0100,              // branch less than or equal to zero
+    parameter BLTZ       = 4'b0101,              // branch less than zero
+    parameter BGEZAL     = 4'b0110,              // branch greater than or equal to zero and link
+    parameter BLTZAL     = 4'b0111,              // branch less than zero and link
+    parameter NO_BRANCH  = 4'b1000,              // no branch
+    /*
+        RegDst field
+        tag to decide which register may be updated
+    */
+    parameter RT         = 3'b000,              // to GPR[rt]
+    parameter RD         = 3'b001,              // to GPR[rd]
+    parameter RA         = 3'b010,              // to GPR[31]
+    parameter HI         = 3'b011,              // to GPR[32]
+    parameter LO         = 3'b100,              // to GPR[33]
+    parameter PROD       = 3'b101,              // to HI and LO 
+    /*
+        DataDst field
+        tag to decide what may be wirtten to regfile
+    */
+    parameter ALU_OUT    = 3'b000,
+    parameter PC_ADD_OUT = 3'b001,
+    parameter HIGH_OUT   = 3'b010,
+    parameter LOW_OUT    = 3'b011,
+    parameter CP0_OUT    = 3'b100, 
+
+    /*
+        ALUOp field
+        tag to decide which operation will be done in alu
+    */
+    parameter USE_R_TYPE = 4'b0000,
+    parameter USE_ADD    = 4'b0001,
+    parameter USE_ADDU   = 4'b0010,
+    parameter USE_SUB    = 4'b0011,
+    parameter USE_SUBU   = 4'b0100,
+    parameter USE_SLT    = 4'b0101,
+    parameter USE_SLTU   = 4'b0110,
+    parameter USE_AND    = 4'b0111,
+    parameter USE_OR     = 4'b1000,
+    parameter USE_NOR    = 4'b1001,
+    parameter USE_XOR    = 4'b1010,
+    parameter USE_LUI    = 4'b1011,
+
+    /*
+        field of ExcCode
+    */
+    parameter NO_EXC     = 4'b0000
+    // TODO : finish interface with cp0
+)(
+    input      [ 5: 0] opcode,
+    input      [ 4: 0] rs,
+    input      [ 4: 0] rt,
+    input      [ 5: 0] funct,
+    output reg         use_stage,
+    output reg [ 1: 0] LS_bit,
+    output reg [ 2: 0] RegDst,
+    output reg [ 2: 0] DataDst,
+    output reg         MemtoReg,    
+    output reg [ 3: 0] ALUOp,
+    output reg         MemWrite,
+    output reg         ALUSrc,
+    output reg         ShamtSrc,
+    output reg         RegWrite,
+    output reg         Ext_op,                      // 1 : signed ext  0 : unsigned ext
+    output reg [ 3: 0] ExcCode,
+    output reg [ 3: 0] Branch,
+    output reg         Jump,
+    output reg         Jr
+);
+    /*
+        opcode field
+    */
+    parameter opcode_is_RType  = 6'b000000;
+
+    // conditional transfer
+    parameter opcode_is_BEQ    = 6'b000100;
+    parameter opcode_is_BNE    = 6'b000101;
+    parameter opcode_is_BGTZ   = 6'b000111;
+    parameter opcode_is_BLEZ   = 6'b000110;
+    parameter opcode_is_REGIMM = 6'b000001;
+    // when   opcode_is_REGIMM, rt
+    parameter rt_is_BGEZ       = 5'b00001;
+    parameter rt_is_BLTZ       = 5'b00000;
+    parameter rt_is_BGEZAL     = 5'b10001;
+    parameter rt_is_BLTZAL     = 5'b10000;   
+
+    // I type R op
+    parameter opcode_is_ADDI   = 6'b001000;
+    parameter opcode_is_ADDIU  = 6'b001001;
+    parameter opcode_is_SLTI   = 6'b001010;
+    parameter opcode_is_SLTIU  = 6'b001011;
+    parameter opcode_is_ANDI   = 6'b001100;
+    parameter opcode_is_LUI    = 6'b001111;
+    parameter opcode_is_ORI    = 6'b001101;
+    parameter opcode_is_XORI   = 6'b001110;
+
+    // load and save
+    parameter opcode_is_LW     = 6'b100011;
+    parameter opcode_is_LH     = 6'b100001;
+    parameter opcode_is_LHU    = 6'b100101;
+    parameter opcode_is_LB     = 6'b100000;
+    parameter opcode_is_LBU    = 6'b100100;
+    parameter opcode_is_SW     = 6'b101011;
+    parameter opcode_is_SH     = 6'b101001;
+    parameter opcode_is_SB     = 6'b101000;
+
+    // J Type
+    parameter opcode_is_J      = 6'b000010;
+    parameter opcode_is_JAL    = 6'b000011;
+
+    // self trap
+    parameter opcode_is_COP0   = 6'b010000;
+    // COP0 field
+    parameter rs_is_MFC0       = 5'b00000;
+    parameter rs_is_MTC0       = 5'b00100;
+    parameter funct_is_ERET    = 6'b011000;     
+
+    /*
+        funct code field
+    */
+    parameter funct_is_MULT    = 6'b011000;
+    parameter funct_is_MULTU   = 6'b011001;
+    parameter funct_is_DIV     = 6'b011010;
+    parameter funct_is_DIVU    = 6'b011011;
+    parameter funct_is_JR      = 6'b001000;             // PC ← GPR[rs]                               rd :       data :                                       
+    parameter funct_is_SLLV    = 6'b000100;             // GPR[rd] ← GPR[rt] << GPR[rs] (logical)     rd : rd      data : alu                             
+    parameter funct_is_SRLV    = 6'b000110;             // GPR[rd] ← GPR[rt] >> GPR[rs] (logical)     rd : rd      data : alu                          
+    parameter funct_is_SRAV    = 6'b000111;             // GPR[rd] ← GPR[rt] >> GPR[rs] (arithmetic)  rd : rd      data : alu                             
+    parameter funct_is_MFHI    = 6'b010000;             // GPR[rd] ← HI                               rd : rd      data : high_out
+    parameter funct_is_MFLO    = 6'b010010;             // GPR[rd] ← LO                               rd : rd      data : low_out   
+    parameter funct_is_MTHI    = 6'b010001;             // HI ← GPR[rs]                               rd : 32      data : alu
+    parameter funct_is_MTLO    = 6'b010011;             // LO ← GPR[rs]                               rd : 33      data : alu
+    // MTHI & MTLO can be seen as HI ← alu_out ← GPR[rs]
+
+    `define SIGNAL {use_stage, LS_bit, RegDst, DataDst, MemtoReg, ALUOp, MemWrite, ALUSrc, ShamtSrc, RegWrite, Ext_op, ExcCode, Branch, Jump, Jr}
+
+    always @(*) begin
+        case (opcode)
+            opcode_is_RType : begin
+                case (funct) 
+                    funct_is_MULT  : `SIGNAL = {EX, NONE, PROD, ALU_OUT , F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_MULTU : `SIGNAL = {EX, NONE, PROD, ALU_OUT , F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_DIV   : `SIGNAL = {EX, NONE, PROD, ALU_OUT , F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_DIVU  : `SIGNAL = {EX, NONE, PROD, ALU_OUT , F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_JR    : `SIGNAL = {ID, NONE, RD  , ALU_OUT , F, USE_R_TYPE, F, F, F, F, F, NO_EXC, NO_BRANCH, F, T};
+                    funct_is_SLLV  : `SIGNAL = {EX, NONE, RD  , ALU_OUT , F, USE_R_TYPE, F, F, T, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_SRLV  : `SIGNAL = {EX, NONE, RD  , ALU_OUT , F, USE_R_TYPE, F, F, T, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_SRAV  : `SIGNAL = {EX, NONE, RD  , ALU_OUT , F, USE_R_TYPE, F, F, T, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_MFHI  : `SIGNAL = {EX, NONE, RD  , HIGH_OUT, F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_MFLO  : `SIGNAL = {EX, NONE, RD  , LOW_OUT , F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_MTHI  : `SIGNAL = {EX, NONE, HI  , ALU_OUT , F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                    funct_is_MTLO  : `SIGNAL = {EX, NONE, LO  , ALU_OUT , F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                    default        : `SIGNAL = {EX, NONE, RD  , ALU_OUT , F, USE_R_TYPE, F, F, F, T, F, NO_EXC, NO_BRANCH, F, F};
+                endcase
+            end
+            opcode_is_BEQ    : `SIGNAL = {ID, NONE, RD, ALU_OUT, F, USE_R_TYPE, F, F, F, F, T, NO_EXC, BEQ , F, F};
+            opcode_is_BNE    : `SIGNAL = {ID, NONE, RD, ALU_OUT, F, USE_R_TYPE, F, F, F, F, T, NO_EXC, BNE , F, F};
+            opcode_is_BGTZ   : `SIGNAL = {ID, NONE, RD, ALU_OUT, F, USE_R_TYPE, F, F, F, F, T, NO_EXC, BGTZ, F, F};
+            opcode_is_BLEZ   : `SIGNAL = {ID, NONE, RD, ALU_OUT, F, USE_R_TYPE, F, F, F, F, T, NO_EXC, BLEZ, F, F};
+            opcode_is_REGIMM : begin
+                case (rt)
+                    rt_is_BGEZ   : `SIGNAL = {ID, NONE, RD, ALU_OUT   , F, USE_R_TYPE, F, F, F, F, T, NO_EXC, BGEZ  , F, F};
+                    rt_is_BLTZ   : `SIGNAL = {ID, NONE, RD, ALU_OUT   , F, USE_R_TYPE, F, F, F, F, T, NO_EXC, BLTZ  , F, F};
+                    rt_is_BGEZAL : `SIGNAL = {ID, NONE, RA, PC_ADD_OUT, F, USE_R_TYPE, F, F, F, T, T, NO_EXC, BGEZAL, F, F};
+                    rt_is_BLTZAL : `SIGNAL = {ID, NONE, RA, PC_ADD_OUT, F, USE_R_TYPE, F, F, F, T, T, NO_EXC, BLTZAL, F, F}; 
+                endcase
+            end
+
+            opcode_is_ADDI   : `SIGNAL = {EX, NONE, RT, ALU_OUT, F, USE_ADD , F, T, F, T, T, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_ADDIU  : `SIGNAL = {EX, NONE, RT, ALU_OUT, F, USE_ADDU, F, T, F, T, T, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_SLTI   : `SIGNAL = {EX, NONE, RT, ALU_OUT, F, USE_SLT , F, T, F, T, T, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_SLTIU  : `SIGNAL = {EX, NONE, RT, ALU_OUT, F, USE_SLTU, F, T, F, T, T, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_ANDI   : `SIGNAL = {EX, NONE, RT, ALU_OUT, F, USE_AND , F, T, F, T, F, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_ORI    : `SIGNAL = {EX, NONE, RT, ALU_OUT, F, USE_OR  , F, T, F, T, F, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_XORI   : `SIGNAL = {EX, NONE, RT, ALU_OUT, F, USE_XOR , F, T, F, T, F, NO_EXC, NO_BRANCH, F, F};        
+            opcode_is_LUI    : `SIGNAL = {EX, NONE, RT, ALU_OUT, F, USE_LUI , F, T, F, T, F, NO_EXC, NO_BRANCH, F, F};
+
+            opcode_is_LW     : `SIGNAL = {EX, WORD, RT, ALU_OUT, T, USE_ADD , F, T, F, T, T, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_LH     : `SIGNAL = {EX, HALF, RT, ALU_OUT, T, USE_ADD , F, T, F, T, T, NO_EXC, NO_BRANCH, F, F};        
+            opcode_is_LHU    : `SIGNAL = {EX, HALF, RT, ALU_OUT, T, USE_ADD , F, T, F, T, F, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_LB     : `SIGNAL = {EX, BYTE, RT, ALU_OUT, T, USE_ADD , F, T, F, T, T, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_LBU    : `SIGNAL = {EX, BYTE, RT, ALU_OUT, T, USE_ADD , F, T, F, T, F, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_SW     : `SIGNAL = {EX, WORD, RT, ALU_OUT, F, USE_ADD , T, T, F, F, T, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_SH     : `SIGNAL = {EX, HALF, RT, ALU_OUT, F, USE_ADD , T, T, F, F, T, NO_EXC, NO_BRANCH, F, F};
+            opcode_is_SB     : `SIGNAL = {EX, BYTE, RT, ALU_OUT, F, USE_ADD , T, T, F, F, T, NO_EXC, NO_BRANCH, F, F};
+
+            opcode_is_J      : `SIGNAL = {ID, NONE, RD, ALU_OUT   , F, USE_ADD , F, T, F, F, F, NO_EXC, NO_BRANCH, T, F};
+            opcode_is_JAL    : `SIGNAL = {ID, NONE, RA, PC_ADD_OUT, F, USE_ADD , F, T, F, T, F, NO_EXC, NO_BRANCH, T, F};
+        
+            opcode_is_COP0 : begin
+                case (rs)
+                    // TODO : finish the signal, the completed SIGNAL is incorrect
+                    rs_is_MFC0 : `SIGNAL = {ID, NONE, RA, PC_ADD_OUT, F, USE_ADD , F, T, F, T, F, NO_EXC, NO_BRANCH, T, F};
+                    rs_is_MTC0 : `SIGNAL = {ID, NONE, RA, PC_ADD_OUT, F, USE_ADD , F, T, F, T, F, NO_EXC, NO_BRANCH, T, F};
+                    default : begin
+                        if (funct == funct_is_ERET)
+                            `SIGNAL = {ID, NONE, RA, PC_ADD_OUT, F, USE_ADD , F, T, F, T, F, NO_EXC, NO_BRANCH, T, F};
+                    end
+                endcase
+            end
+        endcase
+    end
+
+
+endmodule //controller

MipsDesign/src/DataPath/Hazard/ForwardUnit.v

@@ -0,0 +1,105 @@
+module ForwardUnit1 (
+    input      [ 4: 0] rs,
+    input      [ 4: 0] rt,
+    input              EX_MEM_RegWrite,
+    input      [ 5: 0] EX_MEM_mux1_out,
+    input              MEM_WB_RegWrite,
+    input      [ 5: 0] MEM_WB_mux1_out,
+    output reg [ 1: 0] Forward1A,                   // Forward signal to rs
+    output reg [ 1: 0] Forward1B                    // Forward signal to rt
+);
+    // forward rs
+    always @(*) begin
+        if (EX_MEM_RegWrite && EX_MEM_mux1_out != 0 && rs == EX_MEM_mux1_out)
+            Forward1A = 2'b10;
+        else if (MEM_WB_RegWrite && MEM_WB_mux1_out != 0 && rs == MEM_WB_mux1_out)
+            Forward1A = 2'b01;
+        else 
+            Forward1A = 2'b00;
+    end
+
+    // forward rt
+    always @(*) begin
+        if (EX_MEM_RegWrite && EX_MEM_mux1_out != 0 && rt == EX_MEM_mux1_out)
+            Forward1B = 2'b10;
+        else if (MEM_WB_RegWrite && MEM_WB_mux1_out != 0 && rt == MEM_WB_mux1_out)
+            Forward1B = 2'b01;
+        else
+            Forward1B = 2'b00;
+    end
+
+endmodule // ForwardUnit1
+
+
+module ForwardUnit2 (
+    input      [ 4: 0] ID_EX_rs,
+    input      [ 4: 0] ID_EX_rt,
+    input              EX_MEM_RegWrite,
+    input      [ 5: 0] EX_MEM_mux1_out,
+    input              MEM_WB_RegWrite,
+    input      [ 5: 0] MEM_WB_mux1_out,
+    output reg [ 1: 0] Forward2A,                   // Forward signal to ID_EX_rs(op1)
+    output reg [ 1: 0] Forward2B                    // Forward signal to ID_EX_rt(op2)
+);
+
+    // forward ID_EX_rs
+    always @(*) begin
+        if (EX_MEM_RegWrite && EX_MEM_mux1_out != 0 && ID_EX_rs == EX_MEM_mux1_out)
+            Forward2A = 2'b10;
+        else if (MEM_WB_RegWrite && MEM_WB_mux1_out != 0 && ID_EX_rs == MEM_WB_mux1_out)
+            Forward2A = 2'b01;
+        else 
+            Forward2A = 2'b00;
+    end
+
+    always @(*) begin
+        if (EX_MEM_RegWrite && EX_MEM_mux1_out != 0 && ID_EX_rt == EX_MEM_mux1_out)
+            Forward2B = 2'b10;
+        else if (MEM_WB_RegWrite && MEM_WB_mux1_out != 0 && ID_EX_rt == MEM_WB_mux1_out)
+            Forward2B = 2'b01;
+        else 
+            Forward2B = 2'b00;
+    end
+
+endmodule // ForwardUnit2
+
+module ForwardUnit3 (
+    input              EX_MEM_RegWrite,
+    input      [ 5: 0] EX_MEM_mux1_out,
+    input              MEM_WB_RegWrite,
+    input      [ 5: 0] MEM_WB_mux1_out,
+    input      [63: 0] EX_MEM_prod,
+    input      [63: 0] MEM_WB_prod,
+
+    output reg [ 2: 0] Forward3A,
+    output reg [ 2: 0] Forward3B
+);  
+    // low
+    always @(*) begin
+        if      (EX_MEM_RegWrite && EX_MEM_mux1_out == 33)  // lo <- alu_out
+            Forward3A = 3'b010;
+        else if (EX_MEM_RegWrite && EX_MEM_mux1_out == 34)  // lo <- prod[31: 0]
+            Forward3A = 3'b100;
+        else if (MEM_WB_RegWrite && MEM_WB_mux1_out == 33)  // lo <- alu_out
+            Forward3A = 3'b001;
+        else if (MEM_WB_RegWrite && MEM_WB_mux1_out == 34)  // lo <- prod[31: 0]
+            Forward3A = 3'b011;
+        else 
+            Forward3A = 3'b000;
+    end
+
+    // high
+    always @(*) begin
+        if      (EX_MEM_RegWrite && EX_MEM_mux1_out == 32)  // hi <- alu_out
+            Forward3B = 3'b010;
+        else if (EX_MEM_RegWrite && EX_MEM_mux1_out == 34)  // hi <- prod[63:32]
+            Forward3B = 3'b100;
+        else if (MEM_WB_RegWrite && MEM_WB_mux1_out == 32)  // hi <- alu_out
+            Forward3B = 3'b001;
+        else if (MEM_WB_RegWrite && MEM_WB_mux1_out == 34)  // hi <- prod[63:32]
+            Forward3B = 3'b011;
+        else                                                // origin
+            Forward3B = 3'b000;
+    end 
+
+endmodule // ForwardUnit3

MipsDesign/src/DataPath/Hazard/HDU.v

@@ -0,0 +1,86 @@
+/*
+    case (LS_bit)
+    00 : no load/save
+    01 : load/save word
+    10 : load/save half word
+    11 : load/save byte
+
+    case (MemWrite)
+    0 : no save
+    1 : save
+
+    case (use_stage)
+    0 : ID
+    1 : EX
+*/
+
+module HDU1 (
+    input               clock,
+    input               reset,
+    input               use_stage,
+    input               ID_EX_RegWrite,
+    input       [ 1: 0] EX_MEM_LS_bit,
+    input               EX_MEM_MemWrite,
+    input       [ 4: 0] rs,
+    input       [ 4: 0] rt,
+    input       [ 5: 0] mux1_out,
+    input       [ 5: 0] EX_MEM_mux1_out,
+    output reg          PcStall1,
+    output reg          IF_ID_Stall1,
+    output reg          HDU1_block
+);
+    `define TARGET {PcStall1, IF_ID_Stall1, HDU1_block}
+    // initial
+    always @(posedge reset) begin
+        `TARGET = {1'b0, 1'b0, 1'b0};
+    end
+
+    // judge next level's alu or load
+    always @(*) begin
+        if (use_stage == 0 && ID_EX_RegWrite &&         // next level to the branch and jump
+        (rs == mux1_out || rt == mux1_out))
+            `TARGET = {1'b1, 1'b1, 1'b1};
+        else if (use_stage == 0 && 
+            EX_MEM_MemWrite != 1 && EX_MEM_LS_bit != 2'b00 &&
+            (rs == EX_MEM_mux1_out || rt == EX_MEM_mux1_out))
+            `TARGET = {1'b1, 1'b1, 1'b1};
+        else 
+            `TARGET = {1'b0, 1'b0, 1'b0};
+    end
+    // judge the next of next level's load
+
+endmodule // HDU1
+
+module HDU2 (
+    input               clock,
+    input               reset,
+    input               use_stage,
+    input       [ 1: 0] ID_EX_LS_bit,
+    input               ID_EX_MemWrite,
+    input       [ 4: 0] rs,
+    input       [ 4: 0] rt,
+    input       [ 5: 0] mux1_out,
+    output reg          PcStall2,
+    output reg          IF_ID_Stall2,
+    output reg          HDU2_block
+);
+    `define TARGET  {PcStall2, IF_ID_Stall2, HDU2_block}
+
+    // initial 
+    always @(posedge reset) begin
+        `TARGET = {1'b0, 1'b0, 1'b0};
+    end
+
+    // solve load-use conflict
+    always @(*) begin
+        // stall the pipeline when load-use
+        // "ID_EX_MemWrite != 1 && ID_EX_LS_bit != 2'b00" make sure the instruction is a load
+        if (use_stage == 1 && 
+            ID_EX_MemWrite != 1 && ID_EX_LS_bit != 2'b00 && 
+            (rs == mux1_out || rt == mux1_out))
+            `TARGET = {1'b1, 1'b1, 1'b1};
+        else
+            `TARGET = {1'b0, 1'b0, 1'b0};
+    end
+
+endmodule //HDU2

MipsDesign/src/DataPath/Memory/dm_8k.v

@@ -0,0 +1,107 @@
+module dm_8k #(
+    parameter NONE       = 2'b00,
+    parameter WORD       = 2'b01,
+    parameter HALF       = 2'b10,
+    parameter BYTE       = 2'b11
+)(
+    input               clock,
+    input               reset,
+    input       [ 1: 0] EX_MEM_LS_bit,
+    input               EX_MEM_MemWrite,
+    input               EX_MEM_Ext_op,
+    input       [31: 0] EX_MEM_mux5_out,
+    input       [31: 0] EX_MEM_mux3_out,
+    output reg  [31: 0] dm_out
+);
+
+    reg         [31: 0] dm[2048: 0];
+    reg         [15: 0] temp;
+
+    always @(posedge reset) begin
+        // $readmemh("./data/r_data", dm, 0, 2048);
+        // TODO : change size of dm if there is load save command
+    end
+
+    reg         [31: 0] debug_save;
+    reg         [31: 0] debug_load;
+
+    wire         [31: 0] n1;
+    wire         [31: 0] n2;
+    wire         [31: 0] n3;
+    wire         [31: 0] n4;
+    wire         [31: 0] n5;
+    wire         [31: 0] n6;
+
+
+    // save word if MemWrite
+    always @(*) begin      
+        if (EX_MEM_MemWrite && EX_MEM_LS_bit != NONE) begin
+            case (EX_MEM_LS_bit)
+                WORD : begin
+                    debug_save = EX_MEM_mux3_out;
+                    dm[EX_MEM_mux5_out[11: 2]] = EX_MEM_mux3_out;
+                end
+                HALF : begin
+                    debug_save = EX_MEM_mux3_out[15: 0];
+                    case (EX_MEM_mux5_out[1])
+                        1'b0 : dm[EX_MEM_mux5_out[11: 2]][15: 0] = EX_MEM_mux3_out[15: 0];
+                        1'b1 : dm[EX_MEM_mux5_out[11: 2]][31:16] = EX_MEM_mux3_out[15: 0];
+                    endcase
+                end
+                BYTE : begin
+                    debug_save = EX_MEM_mux3_out[ 7: 0];
+                    case (EX_MEM_mux5_out[ 1: 0])
+                        2'b00 : dm[EX_MEM_mux5_out[11: 2]][ 7: 0] = EX_MEM_mux3_out[ 7: 0];
+                        2'b01 : dm[EX_MEM_mux5_out[11: 2]][15: 8] = EX_MEM_mux3_out[ 7: 0];
+                        2'b10 : dm[EX_MEM_mux5_out[11: 2]][23:16] = EX_MEM_mux3_out[ 7: 0];
+                        2'b11 : dm[EX_MEM_mux5_out[11: 2]][31:24] = EX_MEM_mux3_out[ 7: 0];
+                    endcase
+                end
+            endcase
+        end
+    end
+
+    // load word if LS_bit && !MemWrite
+    always @(*) begin
+        if (!EX_MEM_MemWrite && EX_MEM_LS_bit != NONE) begin
+            case (EX_MEM_LS_bit)
+                WORD : begin
+                    debug_load = EX_MEM_mux5_out[11: 2];
+                    dm_out = dm[EX_MEM_mux5_out[11: 2]];
+                end
+                HALF : begin
+                    case (EX_MEM_mux5_out[1])
+                        1'b0 : temp = dm[EX_MEM_mux5_out[11: 2]][15: 0];
+                        1'b1 : temp = dm[EX_MEM_mux5_out[11: 2]][31:16];
+                    endcase
+
+                    if (EX_MEM_Ext_op)
+                        dm_out = {{16{temp[15]}}, temp};
+                    else 
+                        dm_out = {{16{1'b0}}, temp};
+                end
+                BYTE : begin
+                    case (EX_MEM_mux5_out[ 1: 0])
+                        2'b00 : temp = dm[EX_MEM_mux5_out[11: 2]][ 7: 0];
+                        2'b01 : temp = dm[EX_MEM_mux5_out[11: 2]][15: 8];
+                        2'b10 : temp = dm[EX_MEM_mux5_out[11: 2]][23:16];
+                        2'b11 : temp = dm[EX_MEM_mux5_out[11: 2]][31:24];
+                    endcase
+
+                    if (EX_MEM_Ext_op)
+                        dm_out = {{24{temp[7]}}, temp[ 7: 0]};
+                    else 
+                        dm_out = {{24{1'b0}}, temp[ 7: 0]};
+                end
+            endcase
+        end
+    end
+
+    always @(dm[0] or dm[1] or dm[2] or dm[3] or dm[4] or dm[5])        // for debug
+    begin
+        for (integer i = 0; i < 6; i = i + 1)
+            $write("%d", dm[i]);
+            $display(" ");
+    end
+
+endmodule // dm_8k

MipsDesign/src/DataPath/Memory/im_8k.v

@@ -0,0 +1,15 @@
+module im_8k (
+    input          clock,
+    input          reset,
+    input  [31: 0] pc_out,
+    output [31: 0] im_out
+);
+    reg    [31: 0] im[2047: 0];             // instruction memory, which is an instruction pool
+
+    always @(posedge reset) begin
+        // $readmemh("./data/r_text", im, 0, 2047);
+    end
+
+    assign im_out = im[pc_out[11: 2]];
+    
+endmodule // im_8k

MipsDesign/src/DataPath/Pipe/EX_MEM.v

@@ -0,0 +1,37 @@
+module EX_MEM (
+    input              clock,
+    input              reset,
+    input      [ 1: 0] ID_EX_LS_bit,
+    input              ID_EX_MemtoReg,
+    input              ID_EX_MemWrite,
+    input              ID_EX_RegWrite,
+    input              ID_EX_Ext_op,
+    input      [63: 0] prod,
+    input      [31: 0] mux5_out,
+    input      [31: 0] mux3_out,
+    input      [ 5: 0] mux1_out,
+
+    output reg [ 1: 0] EX_MEM_LS_bit,
+    output reg         EX_MEM_MemtoReg,
+    output reg         EX_MEM_MemWrite,
+    output reg         EX_MEM_RegWrite,
+    output reg         EX_MEM_Ext_op,
+    output reg [63: 0] EX_MEM_prod,
+    output reg [31: 0] EX_MEM_mux5_out,
+    output reg [31: 0] EX_MEM_mux3_out,
+    output reg [ 5: 0] EX_MEM_mux1_out
+);
+
+    always @(posedge clock) begin
+        EX_MEM_LS_bit   <=   ID_EX_LS_bit;
+        EX_MEM_MemtoReg <=   ID_EX_MemtoReg;
+        EX_MEM_MemWrite <=   ID_EX_MemWrite;
+        EX_MEM_RegWrite <=   ID_EX_RegWrite;
+        EX_MEM_Ext_op   <=   ID_EX_Ext_op;
+        EX_MEM_prod     <=   prod;
+        EX_MEM_mux5_out <=   mux5_out;
+        EX_MEM_mux3_out <=   mux3_out;
+        EX_MEM_mux1_out <=   mux1_out;
+    end
+
+endmodule // EX_MEM

MipsDesign/src/DataPath/Pipe/ID_EX.v

@@ -0,0 +1,65 @@
+module ID_EX (
+    input               clock,
+    input               reset,
+    input       [ 1: 0] mux7_LS_bit,
+    input       [ 2: 0] mux7_RegDst,
+    input       [ 2: 0] mux7_DataDst,
+    input               mux7_MemtoReg,
+    input       [ 3: 0] mux7_ALUOp,
+    input               mux7_MemWrite,
+    input               mux7_ALUSrc,
+    input               mux7_ShamtSrc,
+    input               mux7_RegWrite,
+    input               mux7_Ext_op,
+    input       [ 3: 0] mux7_ExcCode,
+    input       [31: 0] low_out,
+    input       [31: 0] high_out,
+    input       [31: 0] IF_ID_pc_add_out,
+    input       [31: 0] mux8_out,
+    input       [31: 0] mux9_out,
+    input       [31: 0] Ext_out,
+    input       [25: 0] instr26,
+
+    output reg  [ 1: 0] ID_EX_LS_bit,
+    output reg  [ 2: 0] ID_EX_RegDst,
+    output reg  [ 2: 0] ID_EX_DataDst,
+    output reg          ID_EX_MemtoReg,
+    output reg  [ 3: 0] ID_EX_ALUOp,
+    output reg          ID_EX_MemWrite,
+    output reg          ID_EX_ALUSrc,
+    output reg          ID_EX_ShamtSrc,
+    output reg          ID_EX_RegWrite,
+    output reg          ID_EX_Ext_op,
+    output reg  [ 3: 0] ID_EX_ExcCode,
+    output reg  [31: 0] ID_EX_low_out,
+    output reg  [31: 0] ID_EX_high_out,
+    output reg  [31: 0] ID_EX_pc_add_out,
+    output reg  [31: 0] ID_EX_mux8_out,
+    output reg  [31: 0] ID_EX_mux9_out,
+    output reg  [31: 0] ID_EX_Ext_out,
+    output reg  [25: 0] ID_EX_instr26
+    
+);
+
+    always @(posedge clock) begin
+        ID_EX_LS_bit      <=   mux7_LS_bit;
+        ID_EX_RegDst      <=   mux7_RegDst;
+        ID_EX_DataDst     <=   mux7_DataDst;
+        ID_EX_MemtoReg    <=   mux7_MemtoReg;
+        ID_EX_ALUOp       <=   mux7_ALUOp;
+        ID_EX_MemWrite    <=   mux7_MemWrite;
+        ID_EX_ALUSrc      <=   mux7_ALUSrc;
+        ID_EX_ShamtSrc    <=   mux7_ShamtSrc;
+        ID_EX_RegWrite    <=   mux7_RegWrite;
+        ID_EX_Ext_op      <=   mux7_Ext_op;
+        ID_EX_ExcCode     <=   mux7_ExcCode;
+        ID_EX_low_out     <=   low_out;
+        ID_EX_high_out    <=   high_out;
+        ID_EX_pc_add_out  <=   IF_ID_pc_add_out;
+        ID_EX_mux8_out    <=   mux8_out;
+        ID_EX_mux9_out    <=   mux9_out;
+        ID_EX_Ext_out     <=   Ext_out;
+        ID_EX_instr26     <=   instr26;
+    end
+
+endmodule //ID_EX

MipsDesign/src/DataPath/Pipe/IF_ID.v

@@ -0,0 +1,29 @@
+module IF_ID #(
+    parameter NOP = 32'h20080000            // addi $t0, $zero, 0
+)(
+    input              clock,
+    input              reset,
+    input              OR2_out,
+    input              OR4_out,
+    input      [31: 0] pc_add_out,
+    input      [31: 0] im_out,
+    output reg [31: 0] IF_ID_pc_add_out,
+    output reg [31: 0] IF_ID_im_out
+);
+    /*
+        OR2_out : IF_ID_Stall
+        OR4_out : IF_Flush
+    */
+    always @(posedge clock) 
+    begin
+        if (!OR2_out)                // update iff IF_ID_Write
+        begin
+            if (OR4_out)
+                IF_ID_im_out = NOP;  // use NOP to flush and the pc_add_out won't be used later, so we don't care about pc_add_out there
+            else
+                IF_ID_im_out = im_out;
+            IF_ID_pc_add_out = pc_add_out;
+        end
+    end
+
+endmodule //IF_ID

MipsDesign/src/DataPath/Pipe/MEM_WB.v

@@ -0,0 +1,28 @@
+module MEM_WB (
+    input               clock,
+    input               reset,
+    input               EX_MEM_MemtoReg,
+    input               EX_MEM_RegWrite,
+    input       [31: 0] dm_out,
+    input       [31: 0] EX_MEM_mux5_out,
+    input       [ 5: 0] EX_MEM_mux1_out,
+    input       [63: 0] EX_MEM_prod,
+
+    output reg          MEM_WB_MemtoReg,
+    output reg          MEM_WB_RegWrite,
+    output reg  [31: 0] MEM_WB_dm_out,
+    output reg  [31: 0] MEM_WB_mux5_out,
+    output reg  [ 5: 0] MEM_WB_mux1_out,
+    output reg  [63: 0] MEM_WB_prod
+);
+
+    always @(posedge clock) begin
+        MEM_WB_MemtoReg <=   EX_MEM_MemtoReg;
+        MEM_WB_RegWrite <=   EX_MEM_RegWrite;
+        MEM_WB_dm_out   <=   dm_out;
+        MEM_WB_mux5_out <=   EX_MEM_mux5_out;
+        MEM_WB_mux1_out <=   EX_MEM_mux1_out;
+        MEM_WB_prod     <=   EX_MEM_prod;
+    end
+
+endmodule //MEM_WB

MipsDesign/src/DataPath/Utils/BU.v

@@ -0,0 +1,34 @@
+module BU #(
+    parameter BEQ       = 4'b0000,              // branch equal
+    parameter BNE       = 4'b0001,              // branch not equal 
+    parameter BGEZ      = 4'b0010,              // branch greater than or equal to zero
+    parameter BGTZ      = 4'b0011,              // branch greater than zero
+    parameter BLEZ      = 4'b0100,              // branch less than or equal to zero
+    parameter BLTZ      = 4'b0101,              // branch less than zero
+    parameter BGEZAL    = 4'b0110,              // branch greater than or equal to zero and link
+    parameter BLTZAL    = 4'b0111,              // branch less than zero and link
+    parameter NO_BRANCH = 4'b1000               // no branch
+)(
+    input      [ 3: 0] Branch,
+    input      [31: 0] mux8_out,
+    input      [31: 0] mux9_out,
+    output reg         BU_out
+);
+
+
+    always @(*) begin
+        case(Branch)
+            BEQ       : BU_out = (mux8_out == mux9_out) ? 1 : 0;
+            BNE       : BU_out = (mux8_out == mux9_out) ? 0 : 1;
+            BGEZ      : BU_out = ($signed(mux8_out) > 0 || mux8_out == 0) ? 1 : 0;
+            BGTZ      : BU_out = ($signed(mux8_out) > 0) ? 1 : 0;
+            BLEZ      : BU_out = ($signed(mux8_out) < 0 || mux8_out == 0) ? 1 : 0;
+            BLTZ      : BU_out = ($signed(mux8_out) < 0) ? 1 : 0;
+            // part of link will be thrown to cooperation of controller, pc_add_out and mux5
+            BGEZAL    : BU_out = ($signed(mux8_out) > 0 || mux8_out == 0) ? 1 : 0;
+            BLTZAL    : BU_out = ($signed(mux8_out) < 0) ? 1 : 0;
+            NO_BRANCH : BU_out = 0;
+        endcase
+    end
+
+endmodule //BU

MipsDesign/src/DataPath/Utils/Ext.v

@@ -0,0 +1,13 @@
+module Ext (
+    input              Ext_op,
+    input      [31: 0] IF_ID_im_out,
+    output reg [31: 0] Ext_out
+);
+    always @(*) begin
+        if (Ext_op)
+            Ext_out = {{16{IF_ID_im_out[15]}}, IF_ID_im_out[15: 0]};
+        else 
+            Ext_out = {{16{1'b0}}, IF_ID_im_out[15: 0]};
+    end
+
+endmodule //Ext

MipsDesign/src/DataPath/Utils/FU.v

@@ -0,0 +1,10 @@
+module FU (
+    input   BU_out,
+    input   Jump,
+    input   Jr,
+    output  Skip_IF_Flush
+);
+
+    assign Skip_IF_Flush = BU_out | Jump | Jr;
+
+endmodule //FU

MipsDesign/src/DataPath/Utils/OR.v

@@ -0,0 +1,38 @@
+module OR1 (
+    input  PcStall1,
+    input  PcStall2,
+    output OR1_out 
+);
+    assign OR1_out = PcStall1 | PcStall2;
+
+endmodule //OR
+
+module OR2 (
+    input  IF_ID_Stall1,
+    input  IF_ID_Stall2,
+    output OR2_out  
+);
+    assign OR2_out = IF_ID_Stall1 | IF_ID_Stall2;
+
+endmodule //OR
+
+module OR3 (
+    input  HDU1_block,
+    input  HDU2_block,
+    input  Cause_block,
+    output OR3_out
+);
+
+    assign OR3_out = HDU1_block | HDU2_block | Cause_block;
+
+endmodule //OR
+
+module OR4 (
+    input  Skip_IF_Flush,
+    input  Cause_IF_Flush,
+    output OR4_out
+);
+
+    assign OR4_out = Skip_IF_Flush | Cause_IF_Flush;
+
+endmodule //OR

MipsDesign/src/DataPath/Utils/alu.v

@@ -0,0 +1,190 @@
+module alu #(
+    /*
+        alu_ctrl_out field
+    */
+    parameter ADD_OP     = 5'b00000,
+    parameter ADDU_OP    = 5'b00001,
+    parameter SUB_OP     = 5'b00010,
+    parameter SUBU_OP    = 5'b00011,
+    parameter SLT_OP     = 5'b00100,
+    parameter SLTU_OP    = 5'b00101,
+    parameter MULT_OP    = 5'b00110,
+    parameter MULTU_OP   = 5'b00111,
+    parameter DIV_OP     = 5'b01000,
+    parameter DIVU_OP    = 5'b01001,
+    parameter AND_OP     = 5'b01010,
+    parameter OR_OP      = 5'b01011,
+    parameter NOR_OP     = 5'b01100,
+    parameter XOR_OP     = 5'b01101,
+    parameter LUI_OP     = 5'b01110,
+    parameter SLL_OP     = 5'b01111,
+    parameter SRL_OP     = 5'b10000,
+    parameter SRA_OP     = 5'b10001,
+    parameter MTHI_OP    = 5'b10010,
+    parameter MTLO_OP    = 5'b10011    
+)(
+    input              clock,
+    input              reset,
+    input      [ 4: 0] alu_ctrl_out,
+    input      [31: 0] op1,
+    input      [31: 0] op2,
+    input      [ 4: 0] shamt,
+    output reg [31: 0] alu_out,
+    output reg [63: 0] prod,
+    output reg         overflow,
+    output reg         divideZero
+);
+    reg [32: 0] temp; 
+    always @(posedge clock or posedge reset) begin
+        overflow <= 0;
+        divideZero <= 0;
+    end
+
+    always @(*) begin
+        case (alu_ctrl_out)
+            // 1. add with overflow detection
+            ADD_OP  : begin
+                temp = {op1[31], op1} + {op2[31], op2};
+                if (temp[32:0] == {temp[31], temp[31:0]})
+                begin
+                    alu_out = temp;
+                    overflow = 1'b0;
+                end
+                else 
+                    overflow = 1'b1;
+                divideZero = 0;
+            end
+            // 2. add without overflow detectiom
+            ADDU_OP : begin
+                temp = op1 + op2;
+                alu_out = temp;
+                divideZero = 0;
+            end
+            // 3. sub with overflow detection
+            SUB_OP : begin
+                temp = {op1[31], op1} - {op2[31], op2};
+                if (temp[32:0] == {temp[31],temp[31:0]})
+                begin
+                    alu_out = temp;
+                    overflow = 1'b0;
+                end
+                else 
+                    overflow = 1'b1;
+                divideZero = 0;
+            end
+            // 4. sub without overflow detection
+            SUBU_OP : begin
+                temp = op1 - op2;
+                alu_out = temp;
+                overflow = 0;
+                divideZero = 0;
+            end
+            SLT_OP : begin
+                if ($signed(op1) < $signed(op2))
+                    alu_out = 1;
+                else 
+                    alu_out = 0;
+                overflow = 0;
+                divideZero = 0;
+            end
+            SLTU_OP : begin
+                if ({1'b0, op1} < {1'b0, op2})
+                    alu_out = 1;
+                else 
+                    alu_out = 0;
+                overflow = 0;
+                divideZero = 0;
+            end
+            MULT_OP : begin
+                prod = op1 * op2;
+                overflow = 0;
+                divideZero = 0;
+            end
+            MULTU_OP : begin
+                prod = {1'b0, op1} * {1'b0, op2};
+                overflow = 0;
+                divideZero = 0;
+            end
+            DIV_OP : begin
+                if (op2 == 0)
+                begin
+                    divideZero = 1;
+                end
+                else begin
+                    prod[63:32] = op1 % op2;
+                    prod[31: 0] = op1 / op2;
+                    divideZero = 0;
+                end
+                overflow = 0;
+            end
+            DIVU_OP : begin
+                if (op2 == 0)
+                begin
+                    divideZero = 1;
+                end
+                else begin
+                    prod[63:32] = $signed({1'b0, op1} % {1'b0, op2});
+                    prod[31: 0] = $signed({1'b0, op1} / {1'b0, op2});
+                    divideZero = 0;
+                end
+                overflow = 0;
+            end
+            AND_OP : begin
+                alu_out = op1 & op2;
+                overflow = 0;
+                divideZero = 0;
+            end
+            OR_OP : begin
+                alu_out = op1 | op2;
+                overflow = 0;
+                divideZero = 0;
+            end
+            NOR_OP : begin
+                alu_out = ~(op1 | op2);
+                overflow = 0;
+                divideZero = 0;
+            end
+            XOR_OP : begin
+                alu_out = op1 ^ op2;
+                overflow = 0;
+                divideZero = 0;
+            end
+            LUI_OP : begin
+                alu_out = {op2, {16{1'b0}}};
+                overflow = 0;
+                divideZero = 0;
+            end
+            SLL_OP : begin
+                temp = op2 << shamt;
+                alu_out = temp;
+                overflow = 0;
+                divideZero = 0;
+            end
+            SRL_OP : begin
+                temp = op2 >> shamt;
+                alu_out = temp;
+                overflow = 0;
+                divideZero = 0;
+            end
+            SRA_OP : begin
+                temp = $signed(op2) >>> shamt;
+                alu_out = temp;
+                overflow = 0;
+                divideZero = 0;
+            end
+            // HI ← GPR[rs]
+            MTHI_OP : begin
+                alu_out = op1;
+                overflow = 0;
+                divideZero = 0;
+            end
+            // LO ← GPR[rs]
+            MTLO_OP : begin
+                alu_out = op1;
+                overflow = 0;
+                divideZero = 0;
+            end
+        endcase
+    end
+
+endmodule // alu

MipsDesign/src/DataPath/Utils/alu_ctrl.v

@@ -0,0 +1,116 @@
+module alu_ctrl #(
+    /*
+        ALUOp field
+    */
+    parameter USE_R_TYPE = 4'b0000,
+    parameter USE_ADD    = 4'b0001,
+    parameter USE_ADDU   = 4'b0010,
+    parameter USE_SUB    = 4'b0011,
+    parameter USE_SUBU   = 4'b0100,
+    parameter USE_SLT    = 4'b0101,
+    parameter USE_SLTU   = 4'b0110,
+    parameter USE_AND    = 4'b0111,
+    parameter USE_OR     = 4'b1000,
+    parameter USE_NOR    = 4'b1001,
+    parameter USE_XOR    = 4'b1010,
+    parameter USE_LUI    = 4'b1011,
+    /*
+        alu_ctrl_out field
+    */
+    parameter ADD_OP     = 5'b00000,
+    parameter ADDU_OP    = 5'b00001,
+    parameter SUB_OP     = 5'b00010,
+    parameter SUBU_OP    = 5'b00011,
+    parameter STL_OP     = 5'b00100,
+    parameter STLU_OP    = 5'b00101,
+    parameter MULT_OP    = 5'b00110,
+    parameter MULTU_OP   = 5'b00111,
+    parameter DIV_OP     = 5'b01000,
+    parameter DIVU_OP    = 5'b01001,
+    parameter AND_OP     = 5'b01010,
+    parameter OR_OP      = 5'b01011,
+    parameter NOR_OP     = 5'b01100,
+    parameter XOR_OP     = 5'b01101,
+    parameter LUI_OP     = 5'b01110,
+    parameter SLL_OP     = 5'b01111,
+    parameter SRL_OP     = 5'b10000,
+    parameter SRA_OP     = 5'b10001,
+    parameter MTHI_OP    = 5'b10010,
+    parameter MTLO_OP    = 5'b10011                 
+)(
+    input      [ 3: 0] ID_EX_ALUOp,
+    input      [25: 0] ID_EX_instr26,          // funct extracted from this
+    output reg [ 4: 0] alu_ctrl_out
+);
+
+    /*
+        funct field
+    */
+    parameter funct_is_ADD    = 6'b100000;
+    parameter funct_is_ADDU   = 6'b100001;
+    parameter funct_is_SUB    = 6'b100010;
+    parameter funct_is_SUBU   = 6'b100011;
+    parameter funct_is_SLT    = 6'b101010;
+    parameter funct_is_SLTU   = 6'b101011;
+    parameter funct_is_MULT   = 6'b011000;
+    parameter funct_is_MULTU  = 6'b011001;
+    parameter funct_is_DIV    = 6'b011010;
+    parameter funct_is_DIVU   = 6'b011011;
+    parameter funct_is_AND    = 6'b100100;
+    parameter funct_is_OR     = 6'b100101;
+    parameter funct_is_NOR    = 6'b100111;
+    parameter funct_is_XOR    = 6'b100110;
+    parameter funct_is_SLL    = 6'b000000;
+    parameter funct_is_SLLV   = 6'b000100;
+    parameter funct_is_SRL    = 6'b000010;
+    parameter funct_is_SRLV   = 6'b000110; 
+    parameter funct_is_SRA    = 6'b000011;
+    parameter funct_is_SRAV   = 6'b000111; 
+    parameter funct_is_MTHI   = 6'b010001;
+    parameter funct_is_MTLO   = 6'b010011;  
+
+
+    always @(*) begin
+        case (ID_EX_ALUOp)
+            USE_R_TYPE : begin
+                case (ID_EX_instr26[ 5: 0])
+                    funct_is_ADD    : alu_ctrl_out = ADD_OP;
+                    funct_is_ADDU   : alu_ctrl_out = ADDU_OP;
+                    funct_is_SUB    : alu_ctrl_out = SUB_OP;
+                    funct_is_SLT    : alu_ctrl_out = STL_OP;
+                    funct_is_SLTU   : alu_ctrl_out = STLU_OP;
+                    funct_is_MULT   : alu_ctrl_out = MULT_OP;
+                    funct_is_MULTU  : alu_ctrl_out = MULTU_OP;
+                    funct_is_DIV    : alu_ctrl_out = DIV_OP;
+                    funct_is_DIVU   : alu_ctrl_out = DIVU_OP;
+                    funct_is_AND    : alu_ctrl_out = AND_OP;
+                    funct_is_OR     : alu_ctrl_out = OR_OP;
+                    funct_is_NOR    : alu_ctrl_out = NOR_OP;
+                    funct_is_XOR    : alu_ctrl_out = XOR_OP;
+                    funct_is_SLL    : alu_ctrl_out = SLL_OP;
+                    funct_is_SLLV   : alu_ctrl_out = SLL_OP;
+                    funct_is_SRL    : alu_ctrl_out = SRL_OP;
+                    funct_is_SRLV   : alu_ctrl_out = SRL_OP;
+                    funct_is_SRA    : alu_ctrl_out = SRA_OP;
+                    funct_is_SRAV   : alu_ctrl_out = SRA_OP; 
+                    funct_is_MTHI   : alu_ctrl_out = MTHI_OP;
+                    funct_is_MTLO   : alu_ctrl_out = MTLO_OP;   
+                endcase
+            end
+            USE_ADD   : alu_ctrl_out = ADD_OP;
+            USE_ADDU  : alu_ctrl_out = ADDU_OP;
+            USE_SUB   : alu_ctrl_out = SUB_OP;
+            USE_SUBU  : alu_ctrl_out = SUBU_OP;
+            USE_SLT   : alu_ctrl_out = STL_OP;
+            USE_SLTU  : alu_ctrl_out = STLU_OP;
+            USE_AND   : alu_ctrl_out = AND_OP;
+            USE_OR    : alu_ctrl_out = OR_OP;
+            USE_NOR   : alu_ctrl_out = NOR_OP;
+            USE_XOR   : alu_ctrl_out = XOR_OP;
+            USE_LUI   : alu_ctrl_out = LUI_OP;
+        endcase
+    end         
+
+
+
+endmodule //alu_ctrl

MipsDesign/src/DataPath/Utils/mux.v

@@ -0,0 +1,257 @@
+module mux1 #(
+    parameter RT         = 3'b000,              // to GPR[rt]
+    parameter RD         = 3'b001,              // to GPR[rd]
+    parameter RA         = 3'b010,              // to GPR[31]
+    parameter HI         = 3'b011,              // to GPR[32]
+    parameter LO         = 3'b100,              // to GPR[33]
+    parameter PROD       = 3'b101               // to HI and LO 
+)(
+    input       [ 2: 0] ID_EX_RegDst,
+    input       [25: 0] ID_EX_instr26,
+    output reg  [ 5: 0] mux1_out
+);
+
+    always @(*) begin
+        case (ID_EX_RegDst)
+            RT      : mux1_out = ID_EX_instr26[20:16];
+            RD      : mux1_out = ID_EX_instr26[15:11];
+            RA      : mux1_out = 31;
+            HI      : mux1_out = 32;
+            LO      : mux1_out = 33;
+            PROD    : mux1_out = 34;
+        endcase
+    end
+
+endmodule // mux1
+
+module mux2 (
+    input      [ 1: 0] Forward2A,
+    input      [31: 0] ID_EX_mux8_out,
+    input      [31: 0] mux6_out,
+    input      [31: 0] EX_MEM_mux5_out,
+    output reg [31: 0] mux2_out
+);  
+    always @(*) begin
+        case (Forward2A)
+            2'b10 : mux2_out = EX_MEM_mux5_out;
+            2'b01 : mux2_out = mux6_out;
+            2'b00 : mux2_out = ID_EX_mux8_out;
+        endcase    
+    end
+endmodule // mux2
+
+module mux3 (
+    input      [ 1: 0] Forward2B,
+    input      [31: 0] ID_EX_mux9_out,
+    input      [31: 0] mux6_out,
+    input      [31: 0] EX_MEM_mux5_out,
+    output reg [31: 0] mux3_out
+);
+    always @(*) begin
+        case (Forward2B)
+            2'b10 : mux3_out = EX_MEM_mux5_out;
+            2'b01 : mux3_out = mux6_out;
+            2'b00 : mux3_out = ID_EX_mux9_out;
+        endcase
+    end
+endmodule // mux3
+
+
+module mux4 (
+    input              ID_EX_ALUSrc,
+    input      [31: 0] ID_EX_Ext_out,
+    input      [31: 0] mux3_out,
+    output reg [31: 0] mux4_out
+);
+    always @(*) begin
+        case (ID_EX_ALUSrc)
+            1'b1 : mux4_out = ID_EX_Ext_out;
+            1'b0 : mux4_out = mux3_out;
+        endcase
+    end
+endmodule // mux4
+
+module mux5 (
+    input      [ 2: 0] ID_EX_DataDst,
+    input      [31: 0] mux11_out,
+    input      [31: 0] mux12_out,
+    input      [31: 0] ID_EX_pc_add_out,
+    input      [31: 0] alu_out,
+    output reg [31: 0] mux5_out
+);
+    always @(*) begin
+        case (ID_EX_DataDst)
+            3'b011 : mux5_out = mux11_out;
+            3'b010 : mux5_out = mux12_out;
+            3'b001 : mux5_out = ID_EX_pc_add_out;
+            3'b000 : mux5_out = alu_out;
+        endcase
+    end
+endmodule // mux5
+
+module mux6 (
+    input              MEM_WB_MemtoReg,
+    input      [31: 0] MEM_WB_dm_out,
+    input      [31: 0] MEM_WB_mux5_out,
+    output reg [31: 0] mux6_out
+);
+    always @(*) begin
+        if (MEM_WB_MemtoReg)
+            mux6_out = MEM_WB_dm_out;
+        else 
+            mux6_out = MEM_WB_mux5_out;
+    end
+endmodule // mux6
+
+module mux7 (
+    input               OR3_out,
+
+    input       [ 1: 0] LS_bit,
+    input       [ 2: 0] RegDst,
+    input       [ 2: 0] DataDst,
+    input               MemtoReg,
+    input       [ 3: 0] ALUOp,
+    input               MemWrite,
+    input               ALUSrc,
+    input               ShamtSrc,
+    input               RegWrite,
+    input               Ext_op,
+    input       [ 3: 0] ExcCode,
+
+    output reg  [ 1: 0] mux7_LS_bit,
+    output reg  [ 2: 0] mux7_RegDst,
+    output reg  [ 2: 0] mux7_DataDst,
+    output reg          mux7_MemtoReg,
+    output reg  [ 3: 0] mux7_ALUOp,
+    output reg          mux7_MemWrite,
+    output reg          mux7_ALUSrc,
+    output reg          mux7_ShamtSrc,
+    output reg          mux7_RegWrite,
+    output reg          mux7_Ext_op,
+    output reg  [ 3: 0] mux7_ExcCode
+);
+
+    always @(*) begin
+        if (OR3_out)            // if block
+        begin
+            mux7_LS_bit    =  2'b00;          
+            mux7_RegDst    =  3'b000;      
+            mux7_DataDst   =  3'b000;     
+            mux7_MemtoReg  =  1'b0;     
+            mux7_ALUOp     =  4'b0000;  
+            mux7_MemWrite  =  1'b0;     
+            mux7_ALUSrc    =  1'b0;   
+            mux7_ShamtSrc  =  1'b0;     
+            mux7_RegWrite  =  1'b0;     
+            mux7_Ext_op    =  1'b0;   
+            mux7_ExcCode   =  4'b0000;    
+        end
+        else begin
+            mux7_LS_bit    =  LS_bit;      
+            mux7_RegDst    =  RegDst;   
+            mux7_DataDst   =  DataDst;   
+            mux7_MemtoReg  =  MemtoReg; 
+            mux7_ALUOp     =  ALUOp; 
+            mux7_MemWrite  =  MemWrite; 
+            mux7_ALUSrc    =  ALUSrc;
+            mux7_ShamtSrc  =  ShamtSrc; 
+            mux7_RegWrite  =  RegWrite; 
+            mux7_Ext_op    =  Ext_op;
+            mux7_ExcCode   =  ExcCode;   
+        end
+    end
+endmodule // mux7
+
+module mux8 (
+    input      [ 1: 0] Forward1A,
+    input      [31: 0] regfile_out1,
+    input      [31: 0] EX_MEM_mux5_out,
+    input      [31: 0] mux6_out,
+    output reg [31: 0] mux8_out
+);
+    always @(*) begin
+        case(Forward1A)
+            2'b10 : mux8_out = EX_MEM_mux5_out;
+            2'b01 : mux8_out = mux6_out;
+            3'b00 : mux8_out = regfile_out1;
+        endcase
+    end
+endmodule // mux8
+
+
+module mux9 (
+    input      [ 1: 0] Forward1B,
+    input      [31: 0] regfile_out2,
+    input      [31: 0] EX_MEM_mux5_out,
+    input      [31: 0] mux6_out,
+    output reg [31: 0] mux9_out
+);
+    always @(*) begin
+        case(Forward1B)
+            2'b10 : mux9_out = EX_MEM_mux5_out;
+            2'b01 : mux9_out = mux6_out;
+            2'b00 : mux9_out = regfile_out2;
+        endcase
+    end
+endmodule // mux9
+
+
+module mux10 (
+    input               ShamtSrc,
+    input       [25: 0] ID_EX_instr26,
+    input       [ 4: 0] mux2_out,
+    output  reg [ 4: 0] mux10_out
+);
+    always @(*) begin
+        case (ShamtSrc)
+            1'b0 : mux10_out = ID_EX_instr26[10: 6];
+            1'b1 : mux10_out = mux2_out;
+        endcase
+    end
+
+endmodule // mux10
+
+
+// forward LO
+module mux11 (
+    input      [ 2: 0] Forward3A,
+    input      [31: 0] ID_EX_low_out,
+    input      [31: 0] EX_MEM_mux5_out,
+    input      [31: 0] MEM_WB_mux5_out,
+    input      [63: 0] EX_MEM_prod,
+    input      [63: 0] MEM_WB_prod,
+    output reg [31: 0] mux11_out
+);
+
+    always @(*) begin
+        case (Forward3A)
+            3'b100 : mux11_out = EX_MEM_prod[31: 0];
+            3'b011 : mux11_out = MEM_WB_prod[31: 0];
+            3'b010 : mux11_out = EX_MEM_mux5_out;
+            3'b001 : mux11_out = MEM_WB_mux5_out;
+            3'b000 : mux11_out = ID_EX_low_out;
+        endcase
+    end
+
+endmodule // mux11
+
+// forward HI
+module mux12 (
+    input      [ 2: 0] Forward3B,
+    input      [31: 0] ID_EX_high_out,
+    input      [31: 0] EX_MEM_mux5_out,
+    input      [31: 0] MEM_WB_mux5_out,
+    input      [63: 0] EX_MEM_prod,
+    input      [63: 0] MEM_WB_prod,
+    output reg [31: 0] mux12_out
+);
+    always @(*) begin
+        case (Forward3B)
+            3'b100 : mux12_out = EX_MEM_prod[63: 32];
+            3'b011 : mux12_out = MEM_WB_prod[63: 32];
+            3'b010 : mux12_out = EX_MEM_mux5_out;
+            3'b001 : mux12_out = MEM_WB_mux5_out;
+            3'b000 : mux12_out = ID_EX_high_out;
+        endcase
+    end
+endmodule // mux12

MipsDesign/src/DataPath/Utils/npc.v

@@ -0,0 +1,29 @@
+module npc (
+    input              Jr,                  // use jr, jump register
+    input              Jump,                // use jump, jump addr 
+    input              BU_out,              // use branch, jump base + ext_out
+    input      [31: 0] pc_add_out,
+    input      [31: 0] IF_ID_im_out,        // im_out,  for jump
+    input      [31: 0] Ext_out,             // Ext out, for branch
+    input      [31: 0] mux8_out,            // GPR[rs], for jr
+    output reg [31: 0] npc_out
+);
+    reg        [31: 0] PC;                  // resume the origin current pc value
+
+    always @(*) begin
+        if (Jr) begin
+            npc_out = mux8_out;
+        end
+        else if (Jump) begin
+            PC = pc_add_out - 4;
+            npc_out = {PC[31:28], {IF_ID_im_out[25: 0] << 2}};
+        end
+        else if (BU_out) begin
+            npc_out = (Ext_out << 2) + pc_add_out - 4;
+        end
+        else begin
+            npc_out = pc_add_out;
+        end
+    end
+
+endmodule // npc

MipsDesign/src/DataPath/Utils/pc.v

@@ -0,0 +1,20 @@
+module pc #(
+    parameter initial_addr = 32'h0000_3000
+)(
+    input              clock,
+    input              reset,
+    input      [31: 0] npc_out,
+    input              OR1_out,
+    output reg [31: 0] pc_out
+);
+    // initial 
+    always @(posedge reset) begin
+        pc_out <= initial_addr;
+    end
+
+    always @(posedge clock && reset == 1) begin
+        if (!OR1_out)              // OR1_out represents stall or not
+            pc_out <= npc_out;
+    end
+
+endmodule // pc

MipsDesign/src/DataPath/Utils/pc_add.v

@@ -0,0 +1,7 @@
+module pc_add (
+    input  [31: 0] pc_out,
+    output [31: 0] pc_add_out
+);
+    assign pc_add_out = pc_out + 4;
+
+endmodule //pc_add

MipsDesign/src/DataPath/Utils/regfile.v

@@ -0,0 +1,52 @@
+module regfile (
+    input              clock,
+    input              reset,
+    input              MEM_WB_RegWrite,
+    input      [ 4: 0] rs,
+    input      [ 4: 0] rt,                    
+    input      [ 5: 0] MEM_WB_mux1_out, // rd      
+    input      [31: 0] mux6_out,        // data
+    input      [63: 0] MEM_WB_prod,     // prod               
+    output reg [31: 0] low_out,
+    output reg [31: 0] high_out,
+    output reg [31: 0] regfile_out1,
+    output reg [31: 0] regfile_out2
+);
+    /*
+        0~31 : general registers
+        32   : $hi
+        33   : $lo
+    */
+
+    reg    [31: 0] registers[34: 0];
+    integer        i;
+    
+    // load data from regfile
+    always @(negedge clock) begin           // we should load data in the latter half of the cycle in order to let update appear first
+        // half of the cycle
+        high_out     = registers[32];
+        low_out      = registers[33];
+        regfile_out1 = (rs == 0) ? 0 : registers[rs];
+        regfile_out2 = (rt == 0) ? 0 : registers[rt];
+    end
+    
+    always @(posedge reset) begin
+        for (i = 0; i < 34; i = i + 1)
+            registers[i] = 0;
+    end
+
+    // Write mux6_out to regfile
+    always @(posedge clock) begin
+        if (MEM_WB_RegWrite && MEM_WB_mux1_out != 0)
+        begin
+            if (MEM_WB_mux1_out == 34)           // result of mult of div
+            begin
+                registers[32] = MEM_WB_prod[63:32];     // high
+                registers[33] = MEM_WB_prod[31: 0];     // low
+            end
+            else  
+                registers[MEM_WB_mux1_out] = mux6_out;
+        end            
+    end
+    
+endmodule //regfile

MipsDesign/src/DataPath/datapath.v

@@ -0,0 +1,814 @@
+`include "./Pipe/IF_ID.v"
+`include "./Pipe/ID_EX.v"
+`include "./Pipe/EX_MEM.v"
+`include "./Pipe/MEM_WB.v"
+`include "./Memory/dm_8k.v"
+`include "./Memory/im_8k.v"
+`include "./Hazard/ForwardUnit.v"
+`include "./Hazard/HDU.v"
+`include "./Utils/alu_ctrl.v"
+`include "./Utils/alu.v"
+`include "./Utils/BU.v"
+`include "./Utils/Ext.v"
+`include "./Utils/FU.v"
+`include "./Utils/mux.v"
+`include "./Utils/npc.v"
+`include "./Utils/OR.v"
+`include "./Utils/pc_add.v"
+`include "./Utils/pc.v"
+`include "./Utils/regfile.v"
+
+`define WIDTH 32
+
+module datapath (
+    input          clock,       // clock
+    input          reset,       // reset
+    input          use_stage,   // use_stage
+    input  [ 1: 0] LS_bit,
+    input  [ 2: 0] RegDst,
+    input  [ 2: 0] DataDst,
+    input          MemtoReg,    
+    input  [ 3: 0] ALUOp,
+    input          MemWrite,
+    input          ALUSrc,
+    input          ShamtSrc,
+    input          RegWrite,
+    input          Ext_op,              // 1 : signed ext  0 : unsigned ext
+    input  [ 3: 0] ExcCode,
+    input  [ 3: 0] Branch,
+    input          Jump,
+    input          Jr,
+    output [31: 0] IF_ID_im_out 
+);
+    /*
+        IF module
+    */
+    wire [31: 0] 	npc_out;
+    wire [31: 0] 	pc_out;
+    wire [31: 0] 	pc_add_out;
+    wire [31: 0] 	im_out;
+    wire   	        OR1_out;
+    wire   	        OR2_out;
+    wire   	        OR3_out;
+    wire        	OR4_out;
+    wire [31: 0] 	IF_ID_pc_add_out;
+    wire [31: 0] 	IF_ID_im_out;
+    wire   	        Skip_IF_Flush;
+    wire [31: 0] 	Ext_out;
+    wire   	        PcStall1;
+    wire   	        IF_ID_Stall1;
+    wire   	        HDU1_block;
+    wire   	        PcStall2;
+    wire   	        IF_ID_Stall2;
+    wire   	        HDU2_block;
+    wire [ 1: 0] 	mux7_LS_bit;
+    wire [ 2: 0] 	mux7_RegDst;
+    wire [ 2: 0] 	mux7_DataDst;
+    wire         	mux7_MemtoReg;
+    wire [ 3: 0] 	mux7_ALUOp;
+    wire         	mux7_MemWrite;
+    wire         	mux7_ALUSrc;
+    wire         	mux7_ShamtSrc;
+    wire         	mux7_RegWrite;
+    wire         	mux7_Ext_op;
+    wire [ 3: 0] 	mux7_ExcCode;
+    wire [31: 0] 	low_out;
+    wire [31: 0] 	high_out;
+    wire [31: 0] 	regfile_out1;
+    wire [31: 0] 	regfile_out2;
+    wire [31: 0] 	mux8_out;
+    wire [31: 0] 	mux9_out;
+    wire   	        BU_out;
+    wire [ 1: 0] 	Forward1A;
+    wire [ 1: 0] 	Forward1B;
+
+    wire [ 1: 0] 	ID_EX_LS_bit;
+    wire [ 2: 0] 	ID_EX_RegDst;
+    wire [ 2: 0] 	ID_EX_DataDst;
+    wire         	ID_EX_MemtoReg;
+    wire [ 3: 0] 	ID_EX_ALUOp;
+    wire         	ID_EX_MemWrite;
+    wire         	ID_EX_ALUSrc;
+    wire         	ID_EX_ShamtSrc;
+    wire         	ID_EX_RegWrite;
+    wire         	ID_EX_Ext_op;
+    wire [ 3: 0] 	ID_EX_ExcCode;
+    wire [31: 0] 	ID_EX_low_out;
+    wire [31: 0] 	ID_EX_high_out;
+    wire [31: 0] 	ID_EX_pc_add_out;
+    wire [31: 0] 	ID_EX_mux8_out;
+    wire [31: 0] 	ID_EX_mux9_out;
+    
+    wire [31: 0] 	ID_EX_Ext_out;
+    wire [25: 0] 	ID_EX_instr26;
+
+    wire [31: 0] 	alu_out;
+    wire [63: 0] 	prod;
+    wire         	overflow;
+    wire         	divideZero;
+    wire [ 5: 0] 	mux1_out;
+    wire [ 2: 0] 	Forward3A;
+    wire [ 2: 0] 	Forward3B;
+    wire [31: 0] 	mux11_out;
+    wire [31: 0] 	mux12_out;
+    wire [31: 0] 	mux2_out;
+    wire [31: 0] 	mux3_out;
+    wire [31: 0] 	mux4_out;
+    wire [ 4: 0] 	alu_ctrl_out;
+    wire [ 4: 0] 	mux10_out;
+    wire [ 1: 0] 	Forward2A;
+    wire [ 1: 0] 	Forward2B;
+    wire [31: 0] 	mux5_out;
+    wire [ 1: 0] 	EX_MEM_LS_bit;
+    wire         	EX_MEM_MemtoReg;
+    wire         	EX_MEM_MemWrite;
+    wire         	EX_MEM_RegWrite;
+    wire         	EX_MEM_Ext_op;
+    wire [63: 0] 	EX_MEM_prod;
+    wire [31: 0] 	EX_MEM_mux5_out;
+    wire [31: 0] 	EX_MEM_mux3_out;
+    wire [ 5: 0] 	EX_MEM_mux1_out;
+    wire         	MEM_WB_MemtoReg;
+    wire         	MEM_WB_RegWrite;
+    wire [31: 0] 	MEM_WB_dm_out;
+    wire [31: 0] 	MEM_WB_mux5_out;
+    wire [ 5: 0] 	MEM_WB_mux1_out;
+    wire [63: 0] 	MEM_WB_prod;
+    wire [31: 0] 	mux6_out;
+
+    npc u_npc(
+        //input
+        .Jr           		( Jr           		),
+        .Jump         		( Jump         		),
+        .BU_out       		( BU_out       		),
+        .pc_add_out   		( pc_add_out   		),
+        .IF_ID_im_out 		( IF_ID_im_out 		),
+        .Ext_out      		( Ext_out      		),
+        .mux8_out     		( mux8_out     		),
+
+        //output
+        .npc_out      		( npc_out      		)
+    );
+
+    
+
+    pc #(
+        .initial_addr 		( 32'h0000_3000 		))
+    u_pc(
+        //input
+        .clock   		( clock   		),
+        .reset   		( reset   		),
+        .npc_out 		( npc_out 		),
+        .OR1_out 		( OR1_out 		),
+
+        //output
+        .pc_out  		( pc_out  		)
+    );
+
+
+
+    pc_add u_pc_add(
+        //input
+        .pc_out     		( pc_out     		),
+
+        //output
+        .pc_add_out 		( pc_add_out 		)
+    );
+
+    
+
+    im_8k u_im_8k(
+        //input
+        .clock  		( clock  		),
+        .reset  		( reset  		),
+        .pc_out 		( pc_out 		),
+
+        //output
+        .im_out 		( im_out 		)
+    );
+
+    
+
+    OR1 u_OR1(
+        //input
+        .PcStall1 		( PcStall1 		),
+        .PcStall2 		( PcStall2 		),
+
+        //output
+        .OR1_out  		( OR1_out  		)
+    );
+
+    
+
+    OR2 u_OR2(
+        //input
+        .IF_ID_Stall1 		( IF_ID_Stall1 		),
+        .IF_ID_Stall2 		( IF_ID_Stall2 		),
+
+        //output
+        .OR2_out      		( OR2_out      		)
+    );
+
+    /*
+        ID module
+    */
+    
+
+    IF_ID #(
+        .NOP 		( 32'h20080000                                  		))
+    u_IF_ID(
+        //input
+        .clock            		( clock            		),
+        .reset            		( reset            		),
+        .OR2_out          		( OR2_out          		),
+        .OR4_out          		( OR4_out          		),
+        .pc_add_out       		( pc_add_out       		),
+        .im_out           		( im_out           		),
+
+        //output
+        .IF_ID_pc_add_out 		( IF_ID_pc_add_out 		),
+        .IF_ID_im_out     		( IF_ID_im_out     		)
+    );
+
+    
+
+    OR3 u_OR3(
+        //input
+        .HDU1_block  		( HDU1_block  		),
+        .HDU2_block  		( HDU2_block  		),
+        .Cause_block 		( Cause_block 		),
+
+        //output
+        .OR3_out     		( OR3_out     		)
+    );
+
+    
+
+    OR4 u_OR4(
+        //input
+        .Skip_IF_Flush  		( Skip_IF_Flush  		),
+        .Cause_IF_Flush 		( Cause_IF_Flush 		),
+
+        //output
+        .OR4_out        		( OR4_out        		)
+    );
+
+    
+
+    FU u_FU(
+        //input
+        .BU_out        		( BU_out        		),
+        .Jump          		( Jump          		),
+        .Jr            		( Jr            		),
+
+        //output
+        .Skip_IF_Flush 		( Skip_IF_Flush 		)
+    );
+
+    
+
+    Ext u_Ext(
+        //input
+        .Ext_op       		( Ext_op       		),
+        .IF_ID_im_out 		( IF_ID_im_out 		),
+
+        //output
+        .Ext_out      		( Ext_out      		)
+    );
+
+    
+
+    HDU1 u_HDU1(
+        //input
+        .clock                  ( clock                 ),
+        .reset                  ( reset                 ),
+        .use_stage       		( use_stage       		),
+        .ID_EX_RegWrite  		( ID_EX_RegWrite  		),
+        .EX_MEM_LS_bit   		( EX_MEM_LS_bit   		),
+        .EX_MEM_MemWrite 		( EX_MEM_MemWrite 		),
+        .rs              		( IF_ID_im_out[25:21] 	),
+        .rt              		( IF_ID_im_out[20:16]  	),
+        .mux1_out        		( mux1_out        		),
+        .EX_MEM_mux1_out 		( EX_MEM_mux1_out 		),
+
+        //output
+        .PcStall1        		( PcStall1        		),
+        .IF_ID_Stall1    		( IF_ID_Stall1    		),
+        .HDU1_block      		( HDU1_block      		)
+    );
+
+    
+    HDU2 u_HDU2(
+        //input
+        .clock                  ( clock                 ),
+        .reset                  ( reset                 ),
+        .use_stage      		( use_stage      		),
+        .ID_EX_LS_bit   		( ID_EX_LS_bit   		),
+        .ID_EX_MemWrite 		( ID_EX_MemWrite 		),
+        .rs             		( IF_ID_im_out[25:21] 	),
+        .rt             		( IF_ID_im_out[20:16]  	),
+        .mux1_out       		( mux1_out       		),
+
+        //output
+        .PcStall2       		( PcStall2       		),
+        .IF_ID_Stall2   		( IF_ID_Stall2   		),
+        .HDU2_block     		( HDU2_block     		)
+    );
+
+    
+
+    mux7 u_mux7(
+        //input
+        .OR3_out       		( OR3_out       		),
+        .LS_bit        		( LS_bit        		),
+        .RegDst        		( RegDst        		),
+        .DataDst       		( DataDst       		),
+        .MemtoReg      		( MemtoReg      		),
+        .ALUOp         		( ALUOp         		),
+        .MemWrite      		( MemWrite      		),
+        .ALUSrc        		( ALUSrc        		),
+        .ShamtSrc      		( ShamtSrc      		),
+        .RegWrite      		( RegWrite      		),
+        .Ext_op        		( Ext_op        		),
+        .ExcCode       		( ExcCode       		),
+
+        //output
+        .mux7_LS_bit   		( mux7_LS_bit   		),
+        .mux7_RegDst   		( mux7_RegDst   		),
+        .mux7_DataDst  		( mux7_DataDst  		),
+        .mux7_MemtoReg 		( mux7_MemtoReg 		),
+        .mux7_ALUOp    		( mux7_ALUOp    		),
+        .mux7_MemWrite 		( mux7_MemWrite 		),
+        .mux7_ALUSrc   		( mux7_ALUSrc   		),
+        .mux7_ShamtSrc 		( mux7_ShamtSrc 		),
+        .mux7_RegWrite 		( mux7_RegWrite 		),
+        .mux7_Ext_op   		( mux7_Ext_op   		),
+        .mux7_ExcCode  		( mux7_ExcCode  		)
+    );
+
+
+    regfile u_regfile(
+        //input
+        .clock           		( clock           		),
+        .reset           		( reset           		),
+        .MEM_WB_RegWrite 		( MEM_WB_RegWrite 		),
+        .rs              		( IF_ID_im_out[25:21]   ),
+        .rt              		( IF_ID_im_out[20:16]   ),
+        .MEM_WB_mux1_out 		( MEM_WB_mux1_out 		),
+        .mux6_out        		( mux6_out        		),
+        .MEM_WB_prod     		( MEM_WB_prod     		),
+
+        //output
+        .low_out         		( low_out         		),
+        .high_out        		( high_out        		),
+        .regfile_out1    		( regfile_out1    		),
+        .regfile_out2    		( regfile_out2    		)
+    );
+
+    
+
+    mux8 u_mux8(
+        //input
+        .Forward1A       		( Forward1A       		),
+        .regfile_out1    		( regfile_out1    		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+        .mux6_out        		( mux6_out        		),
+
+        //output
+        .mux8_out        		( mux8_out        		)
+
+        //inout
+    );
+
+    
+
+    mux9 u_mux9(
+        //input
+        .Forward1B       		( Forward1B       		),
+        .regfile_out2    		( regfile_out2    		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+        .mux6_out        		( mux6_out        		),
+
+        //output
+        .mux9_out        		( mux9_out        		)
+    );
+
+    
+
+    BU #(
+        .BEQ       		( 4'b0000                            		),
+        .BNE       		( 4'b0001                            		),
+        .BGEZ      		( 4'b0010                            		),
+        .BGTZ      		( 4'b0011                            		),
+        .BLEZ      		( 4'b0100                            		),
+        .BLTZ      		( 4'b0101                            		),
+        .BGEZAL    		( 4'b0110                            		),
+        .BLTZAL    		( 4'b0111                            		),
+        .NO_BRANCH 		( 4'b1000                            		))
+    u_BU(
+        //input
+        .Branch   		( Branch   		),
+        .mux8_out 		( mux8_out 		),
+        .mux9_out 		( mux9_out 		),
+
+        //output
+        .BU_out   		( BU_out   		)
+    );
+
+
+    ForwardUnit1 u_ForwardUnit1(
+        //input
+        .rs              		( IF_ID_im_out[25:21]  	),
+        .rt              		( IF_ID_im_out[20:16]  	),
+        .EX_MEM_RegWrite 		( EX_MEM_RegWrite 		),
+        .EX_MEM_mux1_out 		( EX_MEM_mux1_out 		),
+        .MEM_WB_RegWrite 		( MEM_WB_RegWrite 		),
+        .MEM_WB_mux1_out 		( MEM_WB_mux1_out 		),
+
+        //output
+        .Forward1A       		( Forward1A       		),
+        .Forward1B       		( Forward1B       		)
+    );
+
+    // EX module
+    ID_EX u_ID_EX(
+        //input
+        .clock            		( clock            		),
+        .reset            		( reset            		),
+        .mux7_LS_bit      		( mux7_LS_bit      		),
+        .mux7_RegDst      		( mux7_RegDst      		),
+        .mux7_DataDst     		( mux7_DataDst     		),
+        .mux7_MemtoReg    		( mux7_MemtoReg    		),
+        .mux7_ALUOp       		( mux7_ALUOp       		),
+        .mux7_MemWrite    		( mux7_MemWrite    		),
+        .mux7_ALUSrc      		( mux7_ALUSrc      		),
+        .mux7_ShamtSrc    		( mux7_ShamtSrc    		),
+        .mux7_RegWrite    		( mux7_RegWrite    		),
+        .mux7_Ext_op      		( mux7_Ext_op      		),
+        .mux7_ExcCode     		( mux7_ExcCode     		),
+        .low_out          		( low_out          		),
+        .high_out         		( high_out         		),
+        .IF_ID_pc_add_out 		( IF_ID_pc_add_out 		),
+        .mux8_out         		( mux8_out         		),
+        .mux9_out         		( mux9_out         		),
+        .Ext_out          		( Ext_out          		),
+        .instr26     		    ( IF_ID_im_out[25: 0]   ),
+
+        //output
+        .ID_EX_LS_bit     		( ID_EX_LS_bit     		),
+        .ID_EX_RegDst     		( ID_EX_RegDst     		),
+        .ID_EX_DataDst    		( ID_EX_DataDst    		),
+        .ID_EX_MemtoReg   		( ID_EX_MemtoReg   		),
+        .ID_EX_ALUOp      		( ID_EX_ALUOp      		),
+        .ID_EX_MemWrite   		( ID_EX_MemWrite   		),
+        .ID_EX_ALUSrc     		( ID_EX_ALUSrc     		),
+        .ID_EX_ShamtSrc   		( ID_EX_ShamtSrc   		),
+        .ID_EX_RegWrite   		( ID_EX_RegWrite   		),
+        .ID_EX_Ext_op     		( ID_EX_Ext_op     		),
+        .ID_EX_ExcCode    		( ID_EX_ExcCode    		),
+        .ID_EX_low_out    		( ID_EX_low_out    		),
+        .ID_EX_high_out   		( ID_EX_high_out   		),
+        .ID_EX_pc_add_out 		( ID_EX_pc_add_out 		),
+        .ID_EX_mux8_out   		( ID_EX_mux8_out   		),
+        .ID_EX_mux9_out   		( ID_EX_mux9_out   		),
+        .ID_EX_Ext_out    		( ID_EX_Ext_out    		),
+        .ID_EX_instr26    		( ID_EX_instr26    		)
+    );
+
+    
+
+    ForwardUnit3 u_ForwardUnit3(
+        //input
+        .EX_MEM_RegWrite 		( EX_MEM_RegWrite 		),
+        .EX_MEM_mux1_out 		( EX_MEM_mux1_out 		),
+        .MEM_WB_RegWrite 		( MEM_WB_RegWrite 		),
+        .MEM_WB_mux1_out 		( MEM_WB_mux1_out 		),
+        .EX_MEM_prod     		( EX_MEM_prod     		),
+        .MEM_WB_prod     		( MEM_WB_prod     		),
+
+        //output
+        .Forward3A       		( Forward3A       		),
+        .Forward3B       		( Forward3B       		)
+
+        //inout
+    );
+
+    
+
+    mux11 u_mux11(
+        //input
+        .Forward3A      		( Forward3A      		),
+        .ID_EX_low_out  		( ID_EX_low_out  		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+        .MEM_WB_mux5_out 		( MEM_WB_mux5_out 		),
+        .EX_MEM_prod    		( EX_MEM_prod    		),
+        .MEM_WB_prod    		( MEM_WB_prod    		),
+
+        //output
+        .mux11_out      		( mux11_out      		)
+
+        //inout
+    );
+
+    
+
+    mux12 u_mux12(
+        //input
+        .Forward3B      		( Forward3B      		),
+        .ID_EX_high_out 		( ID_EX_high_out 		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+        .MEM_WB_mux5_out 		( MEM_WB_mux5_out 		),
+        .EX_MEM_prod    		( EX_MEM_prod    		),
+        .MEM_WB_prod    		( MEM_WB_prod    		),
+
+        //output
+        .mux12_out      		( mux12_out      		)
+
+        //inout
+    );
+
+    mux2 u_mux2(
+        //input
+        .Forward2A       		( Forward2A       		),
+        .ID_EX_mux8_out  		( ID_EX_mux8_out  		),
+        .mux6_out        		( mux6_out        		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+
+        //output
+        .mux2_out        		( mux2_out        		)
+    );
+
+
+    mux3 u_mux3(
+        //input
+        .Forward2B       		( Forward2B       		),
+        .ID_EX_mux9_out  		( ID_EX_mux9_out  		),
+        .mux6_out        		( mux6_out        		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+
+        //output
+        .mux3_out        		( mux3_out        		)
+    );
+
+    
+    mux4 u_mux4(
+        //input
+        .ID_EX_ALUSrc  		( ID_EX_ALUSrc  		),
+        .ID_EX_Ext_out 		( ID_EX_Ext_out 		),
+        .mux3_out      		( mux3_out      		),
+
+        //output
+        .mux4_out      		( mux4_out      		)
+    );
+
+    
+    alu_ctrl #(
+        .USE_R_TYPE     		( 4'b0000                   		),
+        .USE_ADD        		( 4'b0001                   		),
+        .USE_ADDU       		( 4'b0010                   		),
+        .USE_SUB        		( 4'b0011                   		),
+        .USE_SUBU       		( 4'b0100                   		),
+        .USE_SLT        		( 4'b0101                   		),
+        .USE_SLTU       		( 4'b0110                   		),
+        .USE_AND        		( 4'b0111                   		),
+        .USE_OR         		( 4'b1000                   		),
+        .USE_NOR        		( 4'b1001                   		),
+        .USE_XOR        		( 4'b1010                   		),
+        .USE_LUI        		( 4'b1011                   		),
+        .ADD_OP         		( 5'b00000                  		),
+        .ADDU_OP        		( 5'b00001                  		),
+        .SUB_OP         		( 5'b00010                  		),
+        .SUBU_OP        		( 5'b00011                  		),
+        .STL_OP         		( 5'b00100                  		),
+        .STLU_OP        		( 5'b00101                  		),
+        .MULT_OP        		( 5'b00110                  		),
+        .MULTU_OP       		( 5'b00111                  		),
+        .DIV_OP         		( 5'b01000                  		),
+        .DIVU_OP        		( 5'b01001                  		),
+        .AND_OP         		( 5'b01010                  		),
+        .OR_OP          		( 5'b01011                  		),
+        .NOR_OP         		( 5'b01100                  		),
+        .XOR_OP         		( 5'b01101                  		),
+        .LUI_OP         		( 5'b01110                  		),
+        .SLL_OP         		( 5'b01111                  		),
+        .SRL_OP         		( 5'b10000                  		),
+        .SRA_OP         		( 5'b10001                  		),
+        .MTHI_OP        		( 5'b10010                  		),
+        .MTLO_OP        		( 5'b10011                  		),
+        .funct_is_ADD   		( 6'b100000                 		),
+        .funct_is_ADDU  		( 6'b100001                 		),
+        .funct_is_SUB   		( 6'b100010                 		),
+        .funct_is_SUBU  		( 6'b100011                 		),
+        .funct_is_SLT   		( 6'b101010                 		),
+        .funct_is_SLTU  		( 6'b101011                 		),
+        .funct_is_MULT  		( 6'b011000                 		),
+        .funct_is_MULTU 		( 6'b011001                 		),
+        .funct_is_DIV   		( 6'b011010                 		),
+        .funct_is_DIVU  		( 6'b011011                 		),
+        .funct_is_AND   		( 6'b100100                 		),
+        .funct_is_OR    		( 6'b100101                 		),
+        .funct_is_NOR   		( 6'b100111                 		),
+        .funct_is_XOR   		( 6'b100110                 		),
+        .funct_is_SLL   		( 6'b000000                 		),
+        .funct_is_SLLV  		( 6'b000100                 		),
+        .funct_is_SRL   		( 6'b000010                 		),
+        .funct_is_SRLV  		( 6'b000110                 		),
+        .funct_is_SRA   		( 6'b000011                 		),
+        .funct_is_SRAV  		( 6'b000111                 		),
+        .funct_is_MTHI  		( 6'b010001                 		),
+        .funct_is_MTLO  		( 6'b010011                 		))
+    u_alu_ctrl(
+        //input
+        .ID_EX_ALUOp   		( ID_EX_ALUOp   		),
+        .ID_EX_instr26 		( ID_EX_instr26 		),
+
+        //output
+        .alu_ctrl_out  		( alu_ctrl_out  		)
+
+        //inout
+    );
+
+    alu #(
+        .ADD_OP   		( 5'b00000     		),
+        .ADDU_OP  		( 5'b00001     		),
+        .SUB_OP   		( 5'b00010     		),
+        .SUBU_OP  		( 5'b00011     		),
+        .SLT_OP   		( 5'b00100     		),
+        .SLTU_OP  		( 5'b00101     		),
+        .MULT_OP  		( 5'b00110     		),
+        .MULTU_OP 		( 5'b00111     		),
+        .DIV_OP   		( 5'b01000     		),
+        .DIVU_OP  		( 5'b01001     		),
+        .AND_OP   		( 5'b01010     		),
+        .OR_OP    		( 5'b01011     		),
+        .NOR_OP   		( 5'b01100     		),
+        .XOR_OP   		( 5'b01101     		),
+        .LUI_OP   		( 5'b01110     		),
+        .SLL_OP   		( 5'b01111     		),
+        .SRL_OP   		( 5'b10000     		),
+        .SRA_OP   		( 5'b10001     		),
+        .MTHI_OP  		( 5'b10010     		),
+        .MTLO_OP  		( 5'b10011     		))
+    u_alu(
+        //input
+        .clock        		( clock        		),
+        .reset        		( reset        		),
+        .alu_ctrl_out 		( alu_ctrl_out 		),
+        .op1          		( mux2_out     		),
+        .op2          		( mux4_out    		),
+        .shamt        		( mux10_out    		),
+
+        //output
+        .alu_out      		( alu_out      		),
+        .prod         		( prod         		),
+        .overflow     		( overflow     		),
+        .divideZero   		( divideZero   		)
+    );
+
+    
+
+    mux1 #(
+        .RT   		( 3'b000                                		),
+        .RD   		( 3'b001                                		),
+        .RA   		( 3'b010                                		),
+        .HI   		( 3'b011                                		),
+        .LO   		( 3'b100                                		),
+        .PROD 		( 3'b101                                		))
+    u_mux1(
+        //input
+        .ID_EX_RegDst  		( ID_EX_RegDst  		),
+        .ID_EX_instr26 		( ID_EX_instr26 		),
+
+        //output
+        .mux1_out      		( mux1_out      		)
+    );
+
+    
+
+    mux10 u_mux10(
+        //input
+        .ShamtSrc      		( ShamtSrc      		),
+        .ID_EX_instr26 		( ID_EX_instr26 		),
+        .mux2_out      		( mux2_out[ 4: 0] 		),
+
+        //output
+        .mux10_out     		( mux10_out     		)
+    );
+
+
+    ForwardUnit2 u_ForwardUnit2(
+        //input
+        .ID_EX_rs        		( ID_EX_instr26[25:21]  ),
+        .ID_EX_rt        		( ID_EX_instr26[20:16]  ),
+        .EX_MEM_RegWrite 		( EX_MEM_RegWrite 		),
+        .EX_MEM_mux1_out 		( EX_MEM_mux1_out 		),
+        .MEM_WB_RegWrite 		( MEM_WB_RegWrite 		),
+        .MEM_WB_mux1_out 		( MEM_WB_mux1_out 		),
+
+        //output
+        .Forward2A       		( Forward2A       		),
+        .Forward2B       		( Forward2B       		)
+    );
+
+    
+
+    mux5 u_mux5(
+        //input
+        .ID_EX_DataDst    		( ID_EX_DataDst    		),
+        .mux11_out    		( mux11_out    		),
+        .mux12_out   		( mux12_out   		),
+        .ID_EX_pc_add_out 		( ID_EX_pc_add_out 		),
+        .alu_out          		( alu_out          		),
+
+        //output
+        .mux5_out         		( mux5_out         		)
+    );
+
+    /*
+        MEM module
+    */
+    
+
+    EX_MEM u_EX_MEM(
+        //input
+        .clock           		( clock           		),
+        .reset           		( reset           		),
+        .ID_EX_LS_bit    		( ID_EX_LS_bit    		),
+        .ID_EX_MemtoReg  		( ID_EX_MemtoReg  		),
+        .ID_EX_MemWrite  		( ID_EX_MemWrite  		),
+        .ID_EX_RegWrite  		( ID_EX_RegWrite  		),
+        .ID_EX_Ext_op    		( ID_EX_Ext_op    		),
+        .prod            		( prod            		),
+        .mux5_out        		( mux5_out        		),
+        .mux3_out        		( mux3_out        		),
+        .mux1_out        		( mux1_out        		),
+
+        //output
+        .EX_MEM_LS_bit   		( EX_MEM_LS_bit   		),
+        .EX_MEM_MemtoReg 		( EX_MEM_MemtoReg 		),
+        .EX_MEM_MemWrite 		( EX_MEM_MemWrite 		),
+        .EX_MEM_RegWrite 		( EX_MEM_RegWrite 		),
+        .EX_MEM_Ext_op   		( EX_MEM_Ext_op   		),
+        .EX_MEM_prod     		( EX_MEM_prod     		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+        .EX_MEM_mux3_out 		( EX_MEM_mux3_out 		),
+        .EX_MEM_mux1_out 		( EX_MEM_mux1_out 		)
+    );
+
+
+
+    wire [31: 0] 	dm_out;
+
+    dm_8k #(
+        .NONE 		( 2'b00 		),
+        .WORD 		( 2'b01 		),
+        .HALF 		( 2'b10 		),
+        .BYTE 		( 2'b11 		))
+    u_dm_8k(
+        //input
+        .clock           		( clock           		),
+        .reset           		( reset           		),
+        .EX_MEM_LS_bit   		( EX_MEM_LS_bit   		),
+        .EX_MEM_MemWrite 		( EX_MEM_MemWrite 		),
+        .EX_MEM_Ext_op   		( EX_MEM_Ext_op   		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+        .EX_MEM_mux3_out 		( EX_MEM_mux3_out 		),
+
+        //output
+        .dm_out          		( dm_out          		)
+    );
+
+    
+
+    MEM_WB u_MEM_WB(
+        //input
+        .clock           		( clock           		),
+        .reset           		( reset           		),
+        .EX_MEM_MemtoReg 		( EX_MEM_MemtoReg 		),
+        .EX_MEM_RegWrite 		( EX_MEM_RegWrite 		),
+        .dm_out          		( dm_out          		),
+        .EX_MEM_mux5_out 		( EX_MEM_mux5_out 		),
+        .EX_MEM_mux1_out 		( EX_MEM_mux1_out 		),
+        .EX_MEM_prod     		( EX_MEM_prod     		),
+
+        //output
+        .MEM_WB_MemtoReg 		( MEM_WB_MemtoReg 		),
+        .MEM_WB_RegWrite 		( MEM_WB_RegWrite 		),
+        .MEM_WB_dm_out   		( MEM_WB_dm_out   		),
+        .MEM_WB_mux5_out 		( MEM_WB_mux5_out 		),
+        .MEM_WB_mux1_out 		( MEM_WB_mux1_out 		),
+        .MEM_WB_prod     		( MEM_WB_prod     		)
+    );
+
+
+    mux6 u_mux6(
+        //input
+        .MEM_WB_MemtoReg 		( MEM_WB_MemtoReg 		),
+        .MEM_WB_dm_out   		( MEM_WB_dm_out   		),
+        .MEM_WB_mux5_out 		( MEM_WB_mux5_out 		),
+
+        //output
+        .mux6_out        		( mux6_out        		)
+    );
+
+endmodule // datapath

MipsDesign/src/MyCpu.v

@@ -0,0 +1,170 @@
+`include "./Controller/controller.v"
+`include "./DataPath/datapath.v"
+
+`define COUNT_1 100
+`define COUNT_2 200
+`define COUNT_3 300
+
+module MyCpu (
+    input       clock,      // clock
+    input       reset       // reset
+);
+
+    wire [31: 0] 	IF_ID_im_out;     // IF_ID_im_out comment
+    wire         	use_stage;
+    wire [ 1: 0] 	LS_bit;
+    wire [ 2: 0] 	RegDst;
+    wire [ 2: 0] 	DataDst;
+    wire         	MemtoReg;
+    wire [ 3: 0] 	ALUOp;
+    wire         	MemWrite;
+    wire         	ALUSrc;
+    wire         	ShamtSrc;
+    wire         	RegWrite;
+    wire         	Ext_op;
+    wire [ 3: 0] 	ExcCode;
+    wire [ 3: 0] 	Branch;
+    wire         	Jump;
+    wire         	Jr;
+
+    datapath u_datapath(
+        //input
+        .clock        		( clock        		),
+        .reset        		( reset        		),
+        .use_stage    		( use_stage    		),
+        .LS_bit       		( LS_bit       		),
+        .RegDst       		( RegDst       		),
+        .DataDst      		( DataDst      		),
+        .MemtoReg     		( MemtoReg     		),
+        .ALUOp        		( ALUOp        		),
+        .MemWrite     		( MemWrite     		),
+        .ALUSrc       		( ALUSrc       		),
+        .ShamtSrc     		( ShamtSrc     		),
+        .RegWrite     		( RegWrite     		),
+        .Ext_op       		( Ext_op       		),
+        .ExcCode      		( ExcCode      		),
+        .Branch       		( Branch       		),
+        .Jump         		( Jump         		),
+        .Jr           		( Jr           		),
+
+        //output
+        .IF_ID_im_out 		( IF_ID_im_out 		)
+    );
+    
+
+    // comtroller
+    controller #(
+        .T                		( 1'b1      		),
+        .F                		( 1'b0      		),
+        .ID               		( 1'b0      		),
+        .EX               		( 1'b1      		),
+        .NONE             		( 2'b00     		),
+        .WORD             		( 2'b01     		),
+        .HALF             		( 2'b10     		),
+        .BYTE             		( 2'b11     		),
+        .BEQ              		( 4'b0000   		),
+        .BNE              		( 4'b0001   		),
+        .BGEZ             		( 4'b0010   		),
+        .BGTZ             		( 4'b0011   		),
+        .BLEZ             		( 4'b0100   		),
+        .BLTZ             		( 4'b0101   		),
+        .BGEZAL           		( 4'b0110   		),
+        .BLTZAL           		( 4'b0111   		),
+        .NO_BRANCH        		( 4'b1000   		),
+        .RT               		( 3'b000    		),
+        .RD               		( 3'b001    		),
+        .RA               		( 3'b010    		),
+        .HI               		( 3'b011    		),
+        .LO               		( 3'b100    		),
+        .PROD             		( 3'b101    		),
+        .ALU_OUT          		( 3'b000    		),
+        .PC_ADD_OUT       		( 3'b001    		),
+        .HIGH_OUT         		( 3'b010    		),
+        .LOW_OUT          		( 3'b011    		),
+        .CP0_OUT          		( 3'b100    		),
+        .USE_R_TYPE       		( 4'b0000   		),
+        .USE_ADD          		( 4'b0001   		),
+        .USE_ADDU         		( 4'b0010   		),
+        .USE_SUB          		( 4'b0011   		),
+        .USE_SUBU         		( 4'b0100   		),
+        .USE_SLT          		( 4'b0101   		),
+        .USE_SLTU         		( 4'b0110   		),
+        .USE_AND          		( 4'b0111   		),
+        .USE_OR           		( 4'b1000   		),
+        .USE_NOR          		( 4'b1001   		),
+        .USE_XOR          		( 4'b1010   		),
+        .USE_LUI          		( 4'b1011   		),
+        .NO_EXC           		( 4'b0000   		),
+        .opcode_is_RType  		( 6'b000000 		),
+        .opcode_is_BEQ    		( 6'b000100 		),
+        .opcode_is_BNE    		( 6'b000101 		),
+        .opcode_is_BGTZ   		( 6'b000111 		),
+        .opcode_is_BLEZ   		( 6'b000110 		),
+        .opcode_is_REGIMM 		( 6'b000001 		),
+        .rt_is_BGEZ       		( 5'b00001  		),
+        .rt_is_BLTZ       		( 5'b00000  		),
+        .rt_is_BGEZAL     		( 5'b10001  		),
+        .rt_is_BLTZAL     		( 5'b10000  		),
+        .opcode_is_ADDI   		( 6'b001000 		),
+        .opcode_is_ADDIU  		( 6'b001001 		),
+        .opcode_is_SLTI   		( 6'b001010 		),
+        .opcode_is_SLTIU  		( 6'b001011 		),
+        .opcode_is_ANDI   		( 6'b001100 		),
+        .opcode_is_LUI    		( 6'b001111 		),
+        .opcode_is_ORI    		( 6'b001101 		),
+        .opcode_is_XORI   		( 6'b001110 		),
+        .opcode_is_LW     		( 6'b100011 		),
+        .opcode_is_LH     		( 6'b100001 		),
+        .opcode_is_LHU    		( 6'b100101 		),
+        .opcode_is_LB     		( 6'b100000 		),
+        .opcode_is_LBU    		( 6'b100100 		),
+        .opcode_is_SW     		( 6'b101011 		),
+        .opcode_is_SH     		( 6'b101001 		),
+        .opcode_is_SB     		( 6'b101000 		),
+        .opcode_is_J      		( 6'b000010 		),
+        .opcode_is_JAL    		( 6'b000011 		),
+        .opcode_is_COP0   		( 6'b010000 		),
+        .rs_is_MFC0       		( 5'b00000  		),
+        .rs_is_MTC0       		( 5'b00100  		),
+        .funct_is_ERET    		( 6'b011000 		),
+        .funct_is_MULT    		( 6'b011000 		),
+        .funct_is_MULTU   		( 6'b011001 		),
+        .funct_is_DIV     		( 6'b011010 		),
+        .funct_is_DIVU    		( 6'b011011 		),
+        .funct_is_JR      		( 6'b001000 		),
+        .funct_is_SLLV    		( 6'b000100 		),
+        .funct_is_SRLV    		( 6'b000110 		),
+        .funct_is_SRAV    		( 6'b000111 		),
+        .funct_is_MFHI    		( 6'b010000 		),
+        .funct_is_MFLO    		( 6'b010010 		),
+        .funct_is_MTHI    		( 6'b010001 		),
+        .funct_is_MTLO    		( 6'b010011 		))
+    u_controller(
+        // input
+        .opcode    		( IF_ID_im_out[31:26]),
+        .rs        		( IF_ID_im_out[25:21]),
+        .rt        		( IF_ID_im_out[20:16]),
+        .funct     		( IF_ID_im_out[ 5: 0]),
+
+        // output
+        .use_stage 		( use_stage 		),
+        .LS_bit    		( LS_bit    		),
+        .RegDst    		( RegDst    		),
+        .DataDst   		( DataDst   		),
+        .MemtoReg  		( MemtoReg  		),
+        .ALUOp     		( ALUOp     		),
+        .MemWrite  		( MemWrite  		),
+        .ALUSrc    		( ALUSrc    		),
+        .ShamtSrc  		( ShamtSrc  		),
+        .RegWrite  		( RegWrite  		),
+        .Ext_op    		( Ext_op    		),
+        .ExcCode   		( ExcCode   		),
+        .Branch    		( Branch    		),
+        .Jump      		( Jump      		),
+        .Jr        		( Jr        		)
+    );
+
+    
+
+
+endmodule //MyCpu

README.md

@@ -1,7 +1,8 @@
 # Digital-Test
 
+DIDE 项目开发使用的测试项目文件。
 
-默认property.json:
+为了避免测试负载过大，使用默认的property.json:
 
 ```json
 {
@@ -16,3 +17,5 @@
 	"device": "none"
 }
 ```
+
+也就是说，只有`./user/Hardware/src`下的文件会被解析。如果需要测试具体的任务，请自行更换ppy的配置参数。

Simulate/.gitignore

@@ -0,0 +1,3 @@
+prj
+./*.log
+./*.str

Simulate/.vscode/property.json

@@ -0,0 +1,11 @@
+{
+	"TOOL_CHAIN": "xilinx",
+	"PRJ_NAME": {
+		"FPGA": "FFT_IFFT_IP"
+	},
+	"SOC_MODE": {
+		"soc": "none"
+	},
+	"enableShowlog": false,
+	"Device": "xc7a35tftg256-1"
+}

Simulate/Makefile

@@ -0,0 +1,44 @@
+ROOT_PATH:= /home/project/ASIC/simulate
+PRJ_PATH:= ${ROOT_PATH}/prj
+USR_PATH:= ${ROOT_PATH}/user
+
+# $(info $(test))
+VERSION:=v0.3
+SYN_SCRIPT:= ${USR_PATH}/script/synth.tcl
+# 综合参数设置
+SYN_PATH:= ${PRJ_PATH}/SYN${VERSION}
+P&R_PATH:= ${PRJ_PATH}/P&R${VERSION}
+SYN_ARGE:= -f ${SYN_SCRIPT}
+SYN_ARGE+= -output_log_file synth.log
+
+.PHONY: synth
+synth :
+	-mkdir ${PRJ_PATH}
+	rm -rf command.log && rm -rf ${SYN_PATH} && mkdir ${SYN_PATH}
+	cd ${SYN_PATH} && dc_shell ${SYN_ARGE}
+
+
+LIB2DB_SCRIPT:= ${USR_PATH}/script/lib2db.tcl
+.PHONY: lib2db
+lib2db :
+	lc_shell -f ${LIB2DB_SCRIPT}
+	rm -rf ${ROOT_PATH}/lc_shell_command.log
+
+
+P&R_SCRIPT:= ${USR_PATH}/script/p&r.tcl
+P&R_ARGE:= -f ${P&R_SCRIPT}
+P&R_ARGE+= -output_log_file p&r.log
+
+.PHONY: p&r
+p&r : 
+	-mkdir ${P&R_PATH}
+	rm -rf command.log && rm -rf ${P&R_PATH} && mkdir ${P&R_PATH}
+	cd ${P&R_PATH} && icc_shell ${SYN_ARGE}
+
+include mem.mk
+include sim.mk
+
+.PHONY: clean
+clean : 
+	rm -rf ${PRJ_PATH}
+

Simulate/README.md

@@ -0,0 +1,20 @@
+<!--
+ * #Author       : sterben(Duan)
+ * #LastAuthor   : sterben(Duan)
+ * #Date         : 2020-02-04 22:52:33
+ * #lastTime     : 2020-02-04 22:53:26
+ * #FilePath     : \README.md
+ * #Description  : 
+ -->
+
+# FFT_IFFT_IP
+
+文件结构基于vscode下Digital-IDE插件
+
+使用方式：
+1. 安装插件
+2. setting中设置vivado安装路径
+3. launch -> simulate
+
+make sim 进行仿真
+

Simulate/mem.mk

@@ -0,0 +1,53 @@
+RAM_PATH:= /mnt/d/Project/ASIC/FFT_IFFT_IP/user/src/utils/RAM
+ROM_PATH:= /mnt/d/Project/ASIC/FFT_IFFT_IP/user/src/utils/ROM
+BIN_PATH:= /mnt/d/Project/ASIC/FFT_IFFT_IP/user/data/twiddle/bin
+
+S018VM:= /mnt/d/Project/ASIC/library/smic180/mem/S018VM_V0P1PC_CDK
+S018SP:= /mnt/d/Project/ASIC/library/smic180/mem/S018SP_v0p1pc_CDK
+S018DP:= /mnt/d/Project/ASIC/library/smic180/mem/S018DP_v0p2pa_CDK
+S018RF2P:= /mnt/d/Project/ASIC/library/smic180/mem/S018RF2P_v0p2pb_CDK
+
+# 共用参数
+MEM_ARGE:= -bits 48 # 数据位宽
+MEM_ARGE+= -v # 生成Verilog代码	
+MEM_ARGE+= -lib # 生成lib文件
+MEM_ARGE+= -cdl
+MEM_ARGE+= -gds
+MEM_ARGE+= -lef
+MEM_ARGE+= -pdf
+MEM_ARGE+= -mbist
+# MEM_ARGE+= -bitwrite  # 支持bit位读写(DRAM)   
+MEM_ARGE+= -powermesh
+# MEM_ARGE+= -powerring -ringwidth 4
+MEM_ARGE+= -savepath # 放在最后方便设置保存路径
+
+RAM_LEN:= 512
+.PHONY: ram
+ram : 
+	rm -rf ${RAM_PATH}/2048FP
+	mkdir ${RAM_PATH}/2048FP
+	mkdir ${RAM_PATH}/2048FP/db
+	cd ${S018RF2P} && \
+	java -jar ./S018RF2P.jar ${MEM_ARGE} ${RAM_PATH}/2048FP \
+		 -instname FRAM${RAM_LEN} \
+		 -words ${RAM_LEN} \
+		 -mux 2
+	rm -rf ${RAM_PATH}/2048FP/gds ${RAM_PATH}/2048FP/log 
+	
+ROM_STEP:=8
+ROM_LEN:=64
+.PHONY: rom
+rom :
+# rm -rf ${ROM_PATH}/twiddle${ROM_STEP}
+# mkdir ${ROM_PATH}/twiddle${ROM_STEP}
+	cd ${S018VM} && \
+	java -jar ./S018VM.jar ${MEM_ARGE} ${ROM_PATH}/twiddle${ROM_STEP} \
+		 -words ${ROM_LEN} \
+		 -mux 16 \
+		 -codefile ${BIN_PATH}/twiddle${ROM_STEP} \
+		 -instname twiddle${ROM_STEP}
+	rm -rf ${ROM_PATH}/twiddle${ROM_STEP}/gds ${ROM_PATH}/twiddle${ROM_STEP}/log 
+
+.PHONY: clean-mem
+clean-mem :
+	rm -rf ${RAM_PATH} ${ROM_PATH}

Simulate/sim.mk

@@ -0,0 +1,32 @@
+# 仿真参数设置
+SIM_VERSION:= v0.3
+SIM_PATH:= ${PRJ_PATH}/SIM${SIM_VERSION}
+SIM_FILE:= ${USR_PATH}/sim/tb_file/top_tb.f
+# SIM_FILE:= ${USR_PATH}/sim/tb_file/FFT_FLOW_tb.f
+# SIM_FILE:= ${USR_PATH}/sim/tb_file/Flow_FFT_IFFT/fft_ifft_tb.f
+SIM_NAME:= simv
+
+SIM_ARGE:= -f ${SIM_FILE}
+SIM_ARGE+= -o ${SIM_NAME}
+SIM_ARGE+= -l ./vcs.log
+SIM_ARGE+= +v2k # 是使VCS兼容verilog 2001以前的标准
+SIM_ARGE+= -debug_all # 用于产生debug所需的文件
+SIM_ARGE+= +vcs+initreg+random
+SIM_ARGE+= +notimingcheck
+SIM_ARGE+= -Mupdate # 增量编译
+# SIM_ARGE+= -ucli # 使用用户命令行进行仿真调试
+SIM_ARGE+= -gui
+SIM_ARGE+= -error=IWNF +lint=TFIPC-L # 加强约束
+SIM_ARGE+= $(CM) $(CM_NAME) $(CM_DIR) # 覆盖率选项
+
+# Code coverage command  #覆盖率检查
+CM = -cm line+cond+fsm+branch+tgl #收集的代码覆盖率类型
+CM_NAME = -cm_name $(SIM_NAME) #表示覆盖率的文件名
+CN_DIR  = -cm_dir ${SIM_PATH}/$(SIM_NAME).vdb #覆盖率文件的存放目录
+
+.PHONY: sim
+sim :
+	-mkdir ${PRJ_PATH}
+	rm -rf ${SIM_PATH} && mkdir ${SIM_PATH}
+	cd ${SIM_PATH} && vcs ${SIM_ARGE}
+	cd ${SIM_PATH} && ./${SIM_NAME} -l sim.log

Simulate/user/data/PADs/pads.py

@@ -0,0 +1,37 @@
+
+ofp = open('./user/src/top.v', 'r')
+content = ofp.read()
+
+def generateInput(name):
+    str = '// Parallel signal input PAD'
+    for i in range(12):
+        str += f'''
+PIDR {name}{i}_PAD(
+    .IE(1'b1),
+    .PAD({name}{i}),
+    .c({name.lower()}[{i}])
+);
+'''
+    print(str)
+    return str
+
+def generateOutput(name):
+    str = '// Parallel signal output PAD'
+    for i in range(12):
+        str += f'''
+POT12R {name}{i}_PAD(
+    .OEN(1'b1),
+    .PAD({name}{i}),
+    .I({name.lower()}[{i}])
+);
+'''
+    print(str)
+    return str
+
+generateInput('IREAL')
+generateInput('IIMAG')
+
+generateOutput('OREAL')
+generateOutput('OIMAG')
+
+# ofp.write(content)

Simulate/user/data/constraint/timing.sdc

@@ -0,0 +1,61 @@
+# 设置周期 curr : 200MHz
+set T 5
+set_case_analysis 1 [get_ports MODE]
+# 首先创建时钟
+create_clock -name clk -period $T [get_ports CLK]
+
+### note: ------ margin 余量约束设置严格一点
+
+# 路径、器件等造成的延迟
+set_clock_latency       1.2 [get_clocks clk]  
+
+# 边沿跳变的压摆率导致的延迟与不确定
+set_clock_transition    0.4 [get_clocks clk]  
+
+# jitter抖动造成的不稳定
+set_clock_uncertainty   [expr $T*0.25] [get_clocks clk]    
+
+# reg_to_reg
+
+# input/output_to_reg
+# 告诉EDA，模块外部有多大的延迟，软件自动计算内部的延迟(设置的值一般都是经验值)
+# Tclk-q : FF传输时间
+# Tm  : 最大外部延迟
+# clk : 同步的时钟
+# A : 输入的端口
+# B : 输出的端口
+# max 60% min 0
+set InputMaxDelay  [ expr $T * 0.6 ]
+set OutputMaxDelay [ expr $T * 0.6 ]
+#--Option
+set InputMinDelay  [ expr $T * 0 ]
+set OutputMinDelay [ expr $T * 0 ]
+
+set_input_delay $InputMaxDelay -max [all_inputs] -clock [get_clocks clk]   
+set_input_delay $InputMinDelay -min [all_inputs] -clock [get_clocks clk]   
+
+set_output_delay $OutputMaxDelay -max [all_outputs] -clock [get_clocks clk]   
+set_output_delay $OutputMinDelay -min [all_outputs] -clock [get_clocks clk]   
+
+# env attributes
+# 导入模型的R&C，让DC去估算延迟
+# set_load [load of lib/cell_pin] [all_port]
+# set_driving_cell -lib_cell and2a0 [all_port]
+
+set_max_transition  0.5 [current_design]
+# set_max_capacitance # 不必设置直接遵循lib里的约束即可
+set_max_fanout 64 [current_design]
+
+# false path
+# set_false_path -from [get_ports RSTN]
+
+#set_multicycle_path -setup  2 -from A -to B
+#set_multicycle_path -hold   1 -from A -to B
+
+set compile_enable_constant_propagation_with_no_boundary_opt false
+set timing_enable_multiple_clocks_per_reg true
+set enable_recovery_removal_arcs true
+
+set_max_leakage_power 0 
+set_max_area 0
+

Simulate/user/data/twiddle/64乘64系数矩阵.txt

@@ -0,0 +1,64 @@
+4096 + 0i	4096 + 0i	    4096 + 0i	    4096 + 0i	    4096 + 0i	    4096 + 0i	    4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i	4096 + 0i
+4096 + 0i	4076 - 401i	    4017 - 799i	    3920 - 1189i	3784 - 1567i	3612 - 1931i	3406 - 2276i	3166 - 2598i	2896 - 2896i	2598 - 3166i	2276 - 3406i	1931 - 3612i	1567 - 3784i	1189 - 3920i	799 - 4017i	401 - 4076i	0 - 4096i	-401 - 4076i	-799 - 4017i	-1189 - 3920i	-1567 - 3784i	-1931 - 3612i	-2276 - 3406i	-2598 - 3166i	-2896 - 2896i	-3166 - 2598i	-3406 - 2276i	-3612 - 1931i	-3784 - 1567i	-3920 - 1189i	-4017 - 799i	-4076 - 401i	-4096 + -0i	-4076 + 401i	-4017 + 799i	-3920 + 1189i	-3784 + 1567i	-3612 + 1931i	-3406 + 2276i	-3166 + 2598i	-2896 + 2896i	-2598 + 3166i	-2276 + 3406i	-1931 + 3612i	-1567 + 3784i	-1189 + 3920i	-799 + 4017i	-401 + 4076i	0 + 4096i	401 + 4076i	799 + 4017i	1189 + 3920i	1567 + 3784i	1931 + 3612i	2276 + 3406i	2598 + 3166i	2896 + 2896i	3166 + 2598i	3406 + 2276i	3612 + 1931i	3784 + 1567i	3920 + 1189i	4017 + 799i	4076 + 401i
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+4096 + 0i	3784 - 1567i	2896 - 2896i	1567 - 3784i	0 - 4096i	    -1567 - 3784i	-2896 - 2896i	-3784 - 1567i	-4096 + -0i	-3784 + 1567i	-2896 + 2896i	-1567 + 3784i	0 + 4096i	1567 + 3784i	2896 + 2896i	3784 + 1567i	4096 + 0i	3784 - 1567i	2896 - 2896i	1567 - 3784i	0 - 4096i	-1567 - 3784i	-2896 - 2896i	-3784 - 1567i	-4096 + -0i	-3784 + 1567i	-2896 + 2896i	-1567 + 3784i	0 + 4096i	1567 + 3784i	2896 + 2896i	3784 + 1567i	4096 + 0i	3784 - 1567i	2896 - 2896i	1567 - 3784i	0 - 4096i	-1567 - 3784i	-2896 - 2896i	-3784 - 1567i	-4096 + -0i	-3784 + 1567i	-2896 + 2896i	-1567 + 3784i	0 + 4096i	1567 + 3784i	2896 + 2896i	3784 + 1567i	4096 + 0i	3784 - 1567i	2896 - 2896i	1567 - 3784i	0 - 4096i	-1567 - 3784i	-2896 - 2896i	-3784 - 1567i	-4096 + -0i	-3784 + 1567i	-2896 + 2896i	-1567 + 3784i	0 + 4096i	1567 + 3784i	2896 + 2896i	3784 + 1567i
+4096 + 0i	3612 - 1931i	2276 - 3406i	401 - 4076i	    -1567 - 3784i	-3166 - 2598i	-4017 - 799i	-3920 + 1189i	-2896 + 2896i	-1189 + 3920i	799 + 4017i	2598 + 3166i	3784 + 1567i	4076 - 401i	3406 - 2276i	1931 - 3612i	0 - 4096i	-1931 - 3612i	-3406 - 2276i	-4076 - 401i	-3784 + 1567i	-2598 + 3166i	-799 + 4017i	1189 + 3920i	2896 + 2896i	3920 + 1189i	4017 - 799i	3166 - 2598i	1567 - 3784i	-401 - 4076i	-2276 - 3406i	-3612 - 1931i	-4096 + -0i	-3612 + 1931i	-2276 + 3406i	-401 + 4076i	1567 + 3784i	3166 + 2598i	4017 + 799i	3920 - 1189i	2896 - 2896i	1189 - 3920i	-799 - 4017i	-2598 - 3166i	-3784 - 1567i	-4076 + 401i	-3406 + 2276i	-1931 + 3612i	0 + 4096i	1931 + 3612i	3406 + 2276i	4076 + 401i	3784 - 1567i	2598 - 3166i	799 - 4017i	-1189 - 3920i	-2896 - 2896i	-3920 - 1189i	-4017 + 799i	-3166 + 2598i	-1567 + 3784i	401 + 4076i	2276 + 3406i	3612 + 1931i
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Simulate/user/data/twiddle/bin/twiddle11

@@ -0,0 +1,512 @@
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Simulate/user/data/twiddle/bin/twiddle3

@@ -0,0 +1,2 @@
+011111111111000000000000
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Simulate/user/data/twiddle/bin/twiddle4

@@ -0,0 +1,4 @@
+011111111111000000000000
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Simulate/user/data/twiddle/bin/twiddle5

@@ -0,0 +1,8 @@
+011111111111000000000000
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Simulate/user/data/twiddle/bin/twiddle6

@@ -0,0 +1,16 @@
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Simulate/user/data/twiddle/bin/twiddle7

@@ -0,0 +1,32 @@
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Simulate/user/data/twiddle/bin/twiddle8

@@ -0,0 +1,64 @@
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Simulate/user/data/twiddle/bin/twiddle9

@@ -0,0 +1,128 @@
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Simulate/user/data/twiddle/example/im

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Simulate/user/data/twiddle/example/re

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Simulate/user/data/twiddle/twiddle.py

@@ -0,0 +1,167 @@
+from math import cos, sin
+from math import pi
+import matplotlib.pyplot as plt
+import logic as lc
+
+total=11
+owidth=12 # 实际输出数据的有效位数
+M=pow(2, owidth-1)-1 
+
+template = '''
+`timescale 1ns/1ps
+module ftwiddle  #(
+    parameter    FTWI_STAGE = 11, // stage of twiddle
+    parameter    REAL_WIDTH = 12, // data width of real
+    parameter    IMGN_WIDTH = 12  // data width of imgn
+) (
+	input  [FTWI_STAGE-1:0] idx, // index (head addr) input 
+	output [REAL_WIDTH-1:0] ore, // output part of real (signed)
+	output [IMGN_WIDTH-1:0] oim  // output part of imgn (signed)
+);
+
+wire [REAL_WIDTH:0] re;
+wire [IMGN_WIDTH:0] im;
+
+localparam DATA_WIDTH = REAL_WIDTH + IMGN_WIDTH;
+localparam DATA_DEPTH = 2**(FTWI_STAGE-3)-1;
+wire [DATA_WIDTH-1:0] rom[DATA_DEPTH:0];
+
+wire [1:0] haddr = idx[FTWI_STAGE-1:FTWI_STAGE-2];
+wire [FTWI_STAGE-3:0] addr = idx[FTWI_STAGE-3:0];
+
+assign {ore, oim} = haddr == 2'b00 ? {  re,  im } : 
+                    haddr == 2'b01 ? {  im, -re } :
+                    haddr == 2'b10 ? { -re, -im } :
+                    haddr == 2'b11 ? { -im,  re } :
+                    0;
+                    
+assign {re, im} = rom[addr];
+
+generate 
+    if(FTWI_STAGE == 3) begin : stage3
+        // stage 3 rom
+    end
+    else if(FTWI_STAGE == 4) begin : stage4
+        // stage 4 rom
+    end
+    else if(FTWI_STAGE == 5) begin : stage5
+        // stage 5 rom
+    end
+    else if(FTWI_STAGE == 6) begin : stage6
+        // stage 6 rom
+    end
+    else if(FTWI_STAGE == 7) begin : stage7
+        // stage 7 rom
+    end
+    else if(FTWI_STAGE == 8) begin : stage8
+        // stage 8 rom
+    end
+    else if(FTWI_STAGE == 9) begin : stage9
+        // stage 9 rom
+    end
+    else if(FTWI_STAGE == 10) begin : stage10
+        // stage 10 rom
+    end
+    else if(FTWI_STAGE == 11) begin : stage11
+        // stage 11 rom
+    end
+endgenerate
+
+endmodule
+'''
+
+ofbin = "./bin/twiddle"
+ftwid = open("../../src/Parallel_FFT_IFFT/ptwiddle.sv",'w')
+
+# 输入路径
+ifre = open("./example/re",'r')
+ifim = open("./example/im",'r')
+
+# 用于直接进行画图
+def show(x, y):
+    # plt.savefig("Figure_r.png")
+    plt.plot(list(range(1, x)), y)
+    plt.show()
+
+# 虽然是18位的但没实际用满，只用了16位
+def test():
+    i=0;
+    for line in ifre :
+        str = line.strip()
+        out = lc.str2dec(str, 16, 18, True)
+        print("%d : %s",i, out)
+        i=i+1
+
+    i=0;
+    for line in ifim :
+        str = line.strip()
+        out = lc.str2dec(str, 16, 18, True)
+        print("%d : %s",i, out)
+        i=i+1
+
+def twiddle(m, N, width):
+    T = pow(2, width-1)-1 
+    re =  round(T*cos(2*pi*m/N))
+    im = -round(T*sin(2*pi*m/N))
+    # print('re:%d, im:%d\n' % (re, im))
+    reStr = lc.dec2bin(re, width, True)
+    imStr = lc.dec2bin(im, width, True)
+    return reStr + imStr
+
+def rtwiddle(m, N, width):
+    T = pow(2, width-1)-1 
+    re =  round(T*cos(2*pi*m/N))
+    im = -round(T*sin(2*pi*m/N))
+    # print('re:%d, im:%d\n' % (re, im))
+    reStr = lc.dec2bin(re, width, True)
+    return reStr
+
+def itwiddle(m, N, width):
+    T = pow(2, width-1)-1 
+    re =  round(T*cos(2*pi*m/N))
+    im = -round(T*sin(2*pi*m/N))
+    # print('re:%d, im:%d\n' % (re, im))
+    imStr = lc.dec2bin(im, width, True)
+    return imStr
+
+def generate(step):
+    str = ''
+    index = pow(2, step)
+    # fbin  = open('%s%d' % (ofbin, step), 'w')
+    for i in range(int(index/4)):
+        re =  round(M*cos(2*pi*i/index))
+        im = -round(M*sin(2*pi*i/index))
+
+        re = lc.dec2bin(re, owidth, True) 
+        im = lc.dec2bin(im, owidth, True)
+        str += '        assign rom[%d] = %d\'b%s%s;\n' % (i, 2*owidth, re, im)
+        # fbin.write(str)
+
+        # re = str2dec(re, 2, owidth, True) 
+        # im = str2dec(im, 2, owidth, True)
+        # print(i, re, im)
+    # fbin.close()
+    return str
+
+# test()
+# generate(8)
+# for i in range(3, total+1) :
+#     flag = '// stage %d rom\n' % (i)
+#     template = template.replace(flag, flag + generate(i))
+
+# ftwid.write(template)
+# ftwid.close()
+
+str = f'''module ptwiddle (
+        output [12:0] rtwiddle [63:0],
+        output [12:0] itwiddle [63:0]
+    );
+'''
+for m in range(8) :
+        for n in range(8) :
+            str += '        assign rtwiddle[%d] = 13\'b%s;\n' % ((m*8+n), rtwiddle(n*m, 64, 13))
+            str += '        assign itwiddle[%d] = 13\'b%s;\n' % ((m*8+n), rtwiddle(n*m, 64, 13))
+str += 'endmodule'
+print(str)
+ftwid.write(str)
+ftwid.close()   

Simulate/user/script/DC/00_des.tcl

@@ -0,0 +1,17 @@
+#common setting
+set TOP sy13
+set_svf "./result/${TOP}.svf"
+source ./scr/rtl_list_2.lst
+
+#set library
+#timing lib
+set LIB_CORNER      wc
+set USER_LIB_SET "9T_HVT_RVT_POK_SYNOPSYS"
+#->source /home/xian001/SY1301_XIAN/backend/common/lib_common_synopsys_cbai.tcl
+source /home/xian001/SY1301_XIAN/backend/common/lib_common_synopsys_cbai_update.tcl
+#dc setting
+set DW_PATH "/tools/synopsys/dc/J-2014.09-SP3/libraries/syn"
+set search_path ". $search_path $DW_PATH"
+set synthetic_library dw_foundation.sldb
+set link_library "$link_library $synthetic_library"
+define_design_lib work -path ./work

Simulate/user/script/DC/01_read_verilog.tcl

@@ -0,0 +1,14 @@
+#intial setting
+#->read_verilog -netlist xxx
+set_app_var dc_allow_rtl_pg true
+lappend DEFINE_LIST ""
+analyze -format verilog -l work -define $DEFINE_LIST $RTL_FILE_LIST
+#link design
+elaborate $TOP
+current_design $TOP
+set_fix_multiple_port_nets -all -buffer_constants
+link > ./rpt/00_link_design.log
+set uniquify_naming_style ${TOP}_%s_%d
+uniquify -force
+check_design > ./rpt/01_check_design.log
+write -format ddc -h -out ./result/${TOP}_elaborate.ddc

Simulate/user/script/DC/02_compile.tcl

@@ -0,0 +1,82 @@
+#read sdc constraints
+remove_sdc
+source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180502_sdc/sy13_top_con.tcl > ./rpt/02_read_sdc.log
+source -echo -verbose ./scr/sdc/get_mem.tcl >> ./rpt/02_read_sdc.log
+source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180403_sdc/update_0410/scan_dont_touch.tcl >> ./rpt/02_read_sdc.log
+#->source /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180403_sdc/sdc_update.tcl >> ./rpt/02_read_sdc.log
+#->source ./scr/group_path.tcl
+#group_path -name REG2REG -from [all_registers] -to [all_registers] -critical_range 0.5 -weight 10
+#group_path -name FROM_MEM -from [all_registers] to [all_registers] -critical_range 0.5 -weight 10
+#--dont touch   --------------------------------------------
+#set_dont_touch ae210_chip
+#set_dont_touch [get_cells * -hierarchical -filter "full_name =~ ae210_chip/ae210_core/*/*"] true
+#set_dont_touch [get_nets * -hierarchical -filter "full_name =~ ae210_chip/ae210_core/*/*"] true
+set_dont_touch ae210_chip
+set_dont_touch u_mcu/u_sys_top
+set_dont_touch u_mcu/u_aoss_wrap
+set_operating_condition SS0P99V125C
+#--add upf   --------------------------------------------
+set mv_enabke_power_domain_power_net_check false
+set upf_create_implicit_supply_sets false
+set upf_iso_filter_elements_with_applies_to ENABLE
+remove_upf
+#->load_upf /home/xian001/SY1301_XIAN/backend/user/slpeng/pr/20180326/scripts/upf/rtl_20170721.upf > ./rpt/03_read_upf.log
+#->load_upf /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180425_upf/syn13.0422.upf > ./rpt/03_read_upf.log
+source -echo -verbose ./scr/create_vddq_en_pin.tcl > ./rpt/03_read_upf.log
+load_upf /home/xian001/temp_work/upf/0423/sy13.upf >> ./rpt/03_read_upf.log
+source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180425_upf/modify/set_voltage.0429.tcl >> ./rpt/03_read_upf.log
+set mv_upf_check_pg_pins_of_target_lib_cells true
+check_mv_design > ./rpt/check_mv_design.rpt
+
+#start to compile
+#setting
+set_fix_multiple_port_nets -all -buffer_constants
+set_max_area 0
+set verilogout_equation false
+set compile_seqmap_propagate_constants false
+set compile_seqmap_propagate_high_effort false
+set set_ultra_optimization "true"
+set compile_seqmap_identify_shift_registers false
+#--dont touch false for iso   --------------------------------------------
+#->source ./scr/dont_touch_port.lst
+#->set_dont_touch [get_nets -of [get_ports $iso_ports]] false
+#compile
+check_timing  > ./rpt/03_check_timing.rpt
+#-- first compile  --------------------------------------------
+#compile_ultra -timing_high_effort_script -no_autoungroup -no_seq_output_inversion -gate_clock -scan -no_design_rule
+#compile_ultra -no_autoungroup -gate_clock -scan -no_auto_layer_optimization
+compile_ultra -gate_clock -no_seq_output_inversion -scan -no_autoungroup -timing_high_effort_script
+#->save_upf ./result/syn_done_v1.upf
+#report
+
+#change name & output verilog
+source ./scr/change_name.tcl
+write -hier -format verilog -out ./result/${TOP}.v
+write -format ddc -h -out ./result/${TOP}.ddc
+report_constraint -max_delay -nosplit -all_violators -significant_digits 3 > ./rpt/${TOP}.report_constraint.rpt
+report_constraint -max_delay -nosplit -all_violators -max_delay -verbose > ./rpt/${TOP}.report_constraint_verbose.rpt
+report_qor > ./rpt/${TOP}.qor
+
+write_sdc -nosplit ./result/${TOP}.sdc
+save_upf ./result/${TOP}.upf
+#--dont touch list   --------------------------------------------
+set_dont_touch [get_cells -hierarchical -filter "full_name =~ u_mcu/u_aoss_wrap/u_aoss_pad_ring/* && is_hierarchical == false"] true
+set_dont_touch [get_nets -of [get_cells * -hierarchical -filter "full_name =~ *DLY*"]] true
+#set_dont_touch [get_nets -of [get_cells -hierarchical -filter "full_name =~ u_mcu/u_aoss_wrap/u_aoss_pad_ring/* && is_hierarchical == false"]] true
+set dont_touch_cells [get_cells -hier * -filter {@is_hierarchical==false && @dont_touch == true}]
+foreach_in_collection cell $dont_touch_cells {
+	redirect -append ./result/dont_touch.lst {puts [get_att [get_cells $cell] full_name]}
+}
+#set dont_touch_nets [get_nets -hierarchical -filter "dont_touch == true"]
+set dont_touch_dly_nets [get_nets -of [get_cells * -hierarchical -filter "full_name =~ *DLY*"]]
+foreach_in_collection net $dont_touch_dly_nets {
+        redirect -append ./result/dont_touch.lst {puts [get_att [get_nets $net] full_name]}
+}
+
+report_clock_gating -nosplit > ./rpt/04_report_clock_gating.rpt
+check_design > ./rpt/05_check_design.log
+check_timing  > ./rpt/06_check_timing.rpt
+source ./scr/gpio_timing.tcl
+source ./scr/disconnect_net.tcl
+write -hier -format verilog -out ./result/${TOP}_disconnect.v
+set_svf -off

Simulate/user/script/DC/ae210_core_sdc.tcl

@@ -0,0 +1,105 @@
+#################clock################
+set CLOCKS_LIST [ list \
+    hclk       2.5 0  1.25 \
+    hclk2      2.5 0  1.25 \
+    core_clk   2.5 0  1.25 \
+    pclk       5.0 0  2.5 \
+    uart2_clk  5.0 0  2.5 \
+    T4CLK      5.0 0  2.5 \
+    T5CLK      5.0 0  2.5 \
+    T6CLK      5.0 0  2.5 \
+    T7CLK      5.0 0  2.5 \
+]
+#->hclkdiv3   7.5 0  3.75
+set  pre_clock_margin 0.8
+
+foreach [ list CKPORT PRD R F ] $CLOCKS_LIST {
+	echo "INFO : Defining Clock: $CKPORT"
+	lappend CLOCKS_NAME_LIST $CKPORT
+        set PRD_WM  [expr $PRD * $pre_clock_margin]
+        set RW_WM   [expr $R   * $pre_clock_margin]
+        set FW_WM   [expr $F   * $pre_clock_margin]
+	create_clock -name $CKPORT [get_ports $CKPORT] -period $PRD_WM -waveform [list $RW_WM $FW_WM]
+        set_dont_touch_network $CKPORT
+        set_ideal_network $CKPORT
+        set_clock_uncertainty [ expr 0.03 * $PRD_WM] [ get_clocks $CKPORT ]
+}
+echo "INFO : Clocks Defined : $CLOCKS_NAME_LIST"
+set_clock_transition 0.2 [all_clocks]
+
+################reset##############
+set RESETS_LIST [ list \
+        hresetn \
+        hreset2_n \
+        core_resetn \
+        presetn \
+	globalresetn \
+]
+#-> WdtResetn
+if { [ llength RESETS_LIST ] > 0 } {
+    foreach RstName $RESETS_LIST {
+      #/***********************************************************************/
+      #/*   create reset
+      #/***********************************************************************/
+      echo "INFO : Defining Reset : $RstName"
+      set_drive 0 [get_ports $RstName -filter {@port_direction == in} -quiet]
+      set_false_path -from [get_ports $RstName -filter {@port_direction == in} -quiet]
+      set_ideal_network -no_propagate [get_nets -of_object [get_ports $RstName -filter {@port_direction == in} -quiet] -quiet]
+    }
+}
+
+##########input/output delay##############
+set clkname hclk
+set CLKPERIOD [ get_attribute [get_clocks $clkname] period ]
+set InputMaxDelay  [ expr $CLKPERIOD * 0.7 ]
+
+set OutputMaxDelay [ expr $CLKPERIOD * 0.7 ]
+#--Option
+set InputMinDelay  [ expr $CLKPERIOD * 0 ]
+set OutputMinDelay [ expr $CLKPERIOD * 0 ]
+set MaxDelay 0.2
+
+set AllInputNoClkRst [remove_from_collection [all_inputs] [list hresetn hreset2_n core_resetn presetn uart_rstn hclk hclk2 core_clk pclk uart2_clk T4CLK T5CLK T6CLK T7CLK scan_enable scan_test] ]
+set AllOutput [ all_outputs ]
+
+set_input_delay $InputMaxDelay -max -clock $clkname $AllInputNoClkRst
+set_input_delay $InputMinDelay -min -clock $clkname $AllInputNoClkRst
+
+set_output_delay $OutputMaxDelay -max -clock $clkname $AllOutput
+set_output_delay $OutputMinDelay -min -clock $clkname $AllOutput
+
+
+set OutputMaxDelay_0p4 [ expr $CLKPERIOD * 0.4 ]
+set_max_delay [ expr $MaxDelay + $InputMaxDelay + $OutputMaxDelay ] -from $AllInputNoClkRst -to $AllOutput
+
+########################exceptions###############
+#false path
+#->set_false_path -from [get_clock  hclkdiv3] -to [get_clocks {list uart2_clk pclk T4CLK T5CLK T6CLK T7CLK}]
+#->set_false_path -from [get_clocks {list uart2_clk pclk T4CLK T5CLK T6CLK T7CLK} ] -to [get_clock  hclkdiv3]
+#multi cycle path
+set_multicycle_path 2 -setup -end -from [get_clocks [list pclk uart2_clk]] -to [get_clocks  [list hclk hclk2 core_clk]]
+set_multicycle_path 1 -hold  -end -from [get_clocks [list pclk uart2_clk]] -to [get_clocks [list hclk hclk2 core_clk]]
+
+set_multicycle_path 2 -setup -start -to [get_clocks [list pclk uart2_clk]] -from [get_clocks [list hclk hclk2 core_clk]]
+set_multicycle_path 1 -hold  -start -to [get_clocks [list pclk uart2_clk]] -from [get_clocks [list hclk hclk2 core_clk]]
+
+
+#->set_multicycle_path 3 -setup -end -from [get_clocks hclkdiv3] -to [get_clocks {list hclk hclk2 core_clk}]
+#->set_multicycle_path 2 -hold  -end -from [get_clocks hclkdiv3] -to [get_clocks {list hclk hclk2 core_clk }]
+
+#->set_multicycle_path 3 -setup -start -to [get_clocks hclkdiv3] -from [get_clocks {list hclk hclk2 core_clk }]
+#->set_multicycle_path 2 -hold  -start -to [get_clocks hclkdiv3] -from [get_clocks {list hclk hclk2 core_clk }]
+
+set_multicycle_path 2 -setup -from [get_pins u_sram*/*u_sram8Kx64_*/CLK ] -to [get_pins  u_sram*/Q_reg*/data_in]
+set_multicycle_path 1 -hold  -from [get_pins u_sram*/*u_sram8Kx64_*/CLK ] -to [get_pins  u_sram*/Q_reg*/data_in]
+
+
+
+set mem_cells [get_cells -hierarchical -filter "ref_name == sadsls7k41p8192x64m8b4w1c0p0d0t0ss10"]
+
+foreach_in_collection mem_cell $mem_cells {
+	set mem_cell_full_name [get_attribute [get_cells $mem_cell] full_name]
+	echo "$mem_cell_full_name"
+	set_multicycle_path  2 -setup -from [get_pins $mem_cell_full_name/CLK]
+	set_multicycle_path  1 -hold  -from [get_pins $mem_cell_full_name/CLK]
+}

Simulate/user/script/DC/change_name.tcl

@@ -0,0 +1,6 @@
+set_fix_multiple_port_nets -all -buffer_constants [get_designs *]
+set hdlout_internal_busses true
+set bus_inference_style "%s\[%d\]"
+set veriligout_no_tri true
+define_name_rules verilog -check_bus_indexing -allowed {a-zA-Z0-9_} -remove_internal_net_bus -flatten_multi_dimension_busses -first_restricted "\\"
+change_names -rules verilog -hier -verbose

Simulate/user/script/DC/common_setting.tcl

@@ -0,0 +1,48 @@
+#dc common setting
+set_host_options -max_cores 8
+set compile_enable_register_merging false
+set svf_file_records_change_names_changes true
+set enable_recovery_removal_arcs true
+set case_analysis_with_logic_constants true
+set timing_enable_multiple_clocks_per_reg "true"
+set compile_instance_name_prefix "U"
+set verilogout_no_tri true
+set verilogout_show_unconnected_pins true
+set bind_unused_hierarchical_pins false
+
+#CLOCK gating setting
+set compile_clock_gating_through_hierarchy false
+set power_cg_gated_clock_net_naming_style "pckg_net_wc_suffix"
+set power_cg_cell_naming_style "pckg_wc_midfix_wd_suffix"
+set power_cg_module_naming_style "pckg_wp_wd_suffix"
+#->set power_cg_auto_identify true
+#->positive_edge_logic integrated
+set_clock_gating_style \
+        -sequential_cell latch \
+        -control_point before \
+        -control_signal scan_enable \
+        -observation_point false \
+        -positive_edge_logic integrated:${lib_icg_name}/${ICG_NAME} \
+        -max_fanout 16 \
+        -minimum_bitwidth 4
+#--append   --------------------------------------------
+set pwr_hdlc_split_cg_cells                 true
+set timing_scgc_override_library_setup_hold true
+set power_keep_license_after_power_commands true
+set verilogout_equation false
+set compile_seqmap_propagate_constants false
+set compile_seqmap_propagate_high_effort false
+set set_ultra_optimization "true"
+set compile_seqmap_identify_shift_registers false
+set compile_seqmap_no_scan_cell true
+set compile_seqmap_propagate_constants false
+set compile_delete_unloaded_seqential_cells false
+set timing_report_unconstrained_paths true
+set hdlin_enable_vpp                            true
+set power_keep_license_after_power_command      true
+set single_group_per_sheet                      true
+set auto_wire_load_selection false
+
+set timing_disable_recovery_removal_checks false
+set enable_recovery_removal_arcs true
+

Simulate/user/script/DC/create_vddq_en_pin.tcl

@@ -0,0 +1,8 @@
+# u_mcu/u_sys_top/u_sys/uEFC/u_vddq_en_1/X is floating signal.
+
+create_cell dummyBuf ts40n7khpdt_ss0p99v125c/PEH_BUF_PSW_1P5
+#->connect_pin -from u_mcu/u_sys_top/u_sys/uEFC/u_vddq_en_1/X -to dummyBuf/A -port vddq_en_X
+connect_pin -from u_mcu/u_sys_top/VDDQ_FUSE_PG_en -to dummyBuf/A -port vddq_fuse_pg_en_X
+#->remove_cell dummyBuf
+set_dont_touch [get_cells dummyBuf] true
+

Simulate/user/script/DC/dd

@@ -0,0 +1,70 @@
+30,31d29
+< /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac_cm0 \
+< /home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/i_eh2h_s3m1 \
+234a233
+> /home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hyperram/AhbToAxi/Axi_undef.v \
+301a301
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/spi_dw/spi_DW_apb_ssi-undef.v \
+346a347
+> /home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/i_dmac/src/DW_ahb_dmac-undef.v \
+408a410
+> /home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/i_eh2h_s2m1/s2m1_DW_ahb_eh2h-undef.v \
+725a728
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/BusMatrix_2s10m/verilog/rtl_source/BmDefaultSlave.v \
+752a756,789
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_arb_mask.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_arb_req_mi.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_arb_top.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_arbiter_dp.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_bcm01.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_bcm06.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_bcm52.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_bcm54.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_bcm57.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_begen.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_busmux.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_central_tfr_ctl.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_ch_dmux.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_ch_dst_sm.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_ch_src_sm.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_ch_tfr_ctrl.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_ch_to_mi_mux.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_ch_top.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_channelregs.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_commonregs.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_fifo.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_fifo_ctrl.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_fifo_top.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_hs.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_intrif.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_lock_clr.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_master_top.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_mbiu.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_mi_to_ch_mux.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_mst_endian.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_regblockif.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac_sbiu.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_dmac/src/DW_ahb_dmac-undef.v \
+755a793,805
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_async.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_bcm02.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_bcm21.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_begen.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_core.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_dreg.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_macros.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_mbiu.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_mfsm.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_sbiu.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_sfsm.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h_sync.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i_h2h_async/src/DW_ahb_h2h-undef.v \
+921a972,973
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/ssi/DW_apb_ssi-undef.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/timer/cm0ik_t.v \
+922a975,978
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/vpwm/cm0ik_vpwm.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/vpwm/vpwm.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/vpwm/vpwm_fifo.v \
+> /home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/vpwm/vpwm_par_reg.v \

Simulate/user/script/DC/disconnect_net.tcl

@@ -0,0 +1,8 @@
+set float_pin_collections [get_pins -hierarchical -filter "full_name =~ *RTO* || full_name =~ *SNS*"]
+set float_pins [get_att $float_pin_collections full_name]
+foreach float_pin $float_pins {
+	if {[sizeof_collection [all_connected $float_pin ]] != 0} {
+		redirect ./all_float_pins {puts $float_pin} -append
+		disconnect_net [all_connected $float_pin ] $float_pin
+	}
+}

Simulate/user/script/DC/dont_touch_port.lst

@@ -0,0 +1,403 @@
+set iso_ports {
+ae210_chip/ae210_core/gpioa_padout[31]
+ae210_chip/ae210_core/gpioa_padout[30]
+ae210_chip/ae210_core/gpioa_padout[29]
+ae210_chip/ae210_core/gpioa_padout[28]
+ae210_chip/ae210_core/gpioa_padout[27]
+ae210_chip/ae210_core/gpioa_padout[26]
+ae210_chip/ae210_core/gpioa_padout[25]
+ae210_chip/ae210_core/gpioa_padout[24]
+ae210_chip/ae210_core/gpioa_padout[23]
+ae210_chip/ae210_core/gpioa_padout[22]
+ae210_chip/ae210_core/gpioa_padout[21]
+ae210_chip/ae210_core/gpioa_padout[20]
+ae210_chip/ae210_core/gpioa_padout[19]
+ae210_chip/ae210_core/gpioa_padout[18]
+ae210_chip/ae210_core/gpioa_padout[17]
+ae210_chip/ae210_core/gpioa_padout[16]
+ae210_chip/ae210_core/gpioa_padout[15]
+ae210_chip/ae210_core/gpioa_padout[14]
+ae210_chip/ae210_core/gpioa_padout[13]
+ae210_chip/ae210_core/gpioa_padout[12]
+ae210_chip/ae210_core/gpioa_padout[11]
+ae210_chip/ae210_core/gpioa_padout[10]
+ae210_chip/ae210_core/gpioa_padout[9]
+ae210_chip/ae210_core/gpioa_padout[8]
+ae210_chip/ae210_core/gpioa_padout[7]
+ae210_chip/ae210_core/gpioa_padout[6]
+ae210_chip/ae210_core/gpioa_padout[5]
+ae210_chip/ae210_core/gpioa_padout[4]
+ae210_chip/ae210_core/gpioa_padout[3]
+ae210_chip/ae210_core/gpioa_padout[2]
+ae210_chip/ae210_core/gpioa_padout[1]
+ae210_chip/ae210_core/gpioa_padout[0]
+ae210_chip/ae210_core/gpioa_padoen[31]
+ae210_chip/ae210_core/gpioa_padoen[30]
+ae210_chip/ae210_core/gpioa_padoen[29]
+ae210_chip/ae210_core/gpioa_padoen[28]
+ae210_chip/ae210_core/gpioa_padoen[27]
+ae210_chip/ae210_core/gpioa_padoen[26]
+ae210_chip/ae210_core/gpioa_padoen[25]
+ae210_chip/ae210_core/gpioa_padoen[24]
+ae210_chip/ae210_core/gpioa_padoen[23]
+ae210_chip/ae210_core/gpioa_padoen[22]
+ae210_chip/ae210_core/gpioa_padoen[21]
+ae210_chip/ae210_core/gpioa_padoen[20]
+ae210_chip/ae210_core/gpioa_padoen[19]
+ae210_chip/ae210_core/gpioa_padoen[18]
+ae210_chip/ae210_core/gpioa_padoen[17]
+ae210_chip/ae210_core/gpioa_padoen[16]
+ae210_chip/ae210_core/gpioa_padoen[15]
+ae210_chip/ae210_core/gpioa_padoen[14]
+ae210_chip/ae210_core/gpioa_padoen[13]
+ae210_chip/ae210_core/gpioa_padoen[12]
+ae210_chip/ae210_core/gpioa_padoen[11]
+ae210_chip/ae210_core/gpioa_padoen[10]
+ae210_chip/ae210_core/gpioa_padoen[9]
+ae210_chip/ae210_core/gpioa_padoen[8]
+ae210_chip/ae210_core/gpioa_padoen[7]
+ae210_chip/ae210_core/gpioa_padoen[6]
+ae210_chip/ae210_core/gpioa_padoen[5]
+ae210_chip/ae210_core/gpioa_padoen[4]
+ae210_chip/ae210_core/gpioa_padoen[3]
+ae210_chip/ae210_core/gpioa_padoen[2]
+ae210_chip/ae210_core/gpioa_padoen[1]
+ae210_chip/ae210_core/gpioa_padoen[0]
+ae210_chip/ae210_core/gpioa_pull_en[31]
+ae210_chip/ae210_core/gpioa_pull_en[30]
+ae210_chip/ae210_core/gpioa_pull_en[29]
+ae210_chip/ae210_core/gpioa_pull_en[28]
+ae210_chip/ae210_core/gpioa_pull_en[27]
+ae210_chip/ae210_core/gpioa_pull_en[26]
+ae210_chip/ae210_core/gpioa_pull_en[25]
+ae210_chip/ae210_core/gpioa_pull_en[24]
+ae210_chip/ae210_core/gpioa_pull_en[23]
+ae210_chip/ae210_core/gpioa_pull_en[22]
+ae210_chip/ae210_core/gpioa_pull_en[21]
+ae210_chip/ae210_core/gpioa_pull_en[20]
+ae210_chip/ae210_core/gpioa_pull_en[19]
+ae210_chip/ae210_core/gpioa_pull_en[18]
+ae210_chip/ae210_core/gpioa_pull_en[17]
+ae210_chip/ae210_core/gpioa_pull_en[16]
+ae210_chip/ae210_core/gpioa_pull_en[15]
+ae210_chip/ae210_core/gpioa_pull_en[14]
+ae210_chip/ae210_core/gpioa_pull_en[13]
+ae210_chip/ae210_core/gpioa_pull_en[12]
+ae210_chip/ae210_core/gpioa_pull_en[11]
+ae210_chip/ae210_core/gpioa_pull_en[10]
+ae210_chip/ae210_core/gpioa_pull_en[9]
+ae210_chip/ae210_core/gpioa_pull_en[8]
+ae210_chip/ae210_core/gpioa_pull_en[7]
+ae210_chip/ae210_core/gpioa_pull_en[6]
+ae210_chip/ae210_core/gpioa_pull_en[5]
+ae210_chip/ae210_core/gpioa_pull_en[4]
+ae210_chip/ae210_core/gpioa_pull_en[3]
+ae210_chip/ae210_core/gpioa_pull_en[2]
+ae210_chip/ae210_core/gpioa_pull_en[1]
+ae210_chip/ae210_core/gpioa_pull_en[0]
+ae210_chip/ae210_core/gpiob_padout[31]
+ae210_chip/ae210_core/gpiob_padout[30]
+ae210_chip/ae210_core/gpiob_padout[29]
+ae210_chip/ae210_core/gpiob_padout[28]
+ae210_chip/ae210_core/gpiob_padout[27]
+ae210_chip/ae210_core/gpiob_padout[26]
+ae210_chip/ae210_core/gpiob_padout[25]
+ae210_chip/ae210_core/gpiob_padout[24]
+ae210_chip/ae210_core/gpiob_padout[23]
+ae210_chip/ae210_core/gpiob_padout[22]
+ae210_chip/ae210_core/gpiob_padout[21]
+ae210_chip/ae210_core/gpiob_padout[20]
+ae210_chip/ae210_core/gpiob_padout[19]
+ae210_chip/ae210_core/gpiob_padout[18]
+ae210_chip/ae210_core/gpiob_padout[17]
+ae210_chip/ae210_core/gpiob_padout[16]
+ae210_chip/ae210_core/gpiob_padout[15]
+ae210_chip/ae210_core/gpiob_padout[14]
+ae210_chip/ae210_core/gpiob_padout[13]
+ae210_chip/ae210_core/gpiob_padout[12]
+ae210_chip/ae210_core/gpiob_padout[11]
+ae210_chip/ae210_core/gpiob_padout[10]
+ae210_chip/ae210_core/gpiob_padout[9]
+ae210_chip/ae210_core/gpiob_padout[8]
+ae210_chip/ae210_core/gpiob_padout[7]
+ae210_chip/ae210_core/gpiob_padout[6]
+ae210_chip/ae210_core/gpiob_padout[5]
+ae210_chip/ae210_core/gpiob_padout[4]
+ae210_chip/ae210_core/gpiob_padout[3]
+ae210_chip/ae210_core/gpiob_padout[2]
+ae210_chip/ae210_core/gpiob_padout[1]
+ae210_chip/ae210_core/gpiob_padout[0]
+ae210_chip/ae210_core/gpiob_padoen[31]
+ae210_chip/ae210_core/gpiob_padoen[30]
+ae210_chip/ae210_core/gpiob_padoen[29]
+ae210_chip/ae210_core/gpiob_padoen[28]
+ae210_chip/ae210_core/gpiob_padoen[27]
+ae210_chip/ae210_core/gpiob_padoen[26]
+ae210_chip/ae210_core/gpiob_padoen[25]
+ae210_chip/ae210_core/gpiob_padoen[24]
+ae210_chip/ae210_core/gpiob_padoen[23]
+ae210_chip/ae210_core/gpiob_padoen[22]
+ae210_chip/ae210_core/gpiob_padoen[21]
+ae210_chip/ae210_core/gpiob_padoen[20]
+ae210_chip/ae210_core/gpiob_padoen[19]
+ae210_chip/ae210_core/gpiob_padoen[18]
+ae210_chip/ae210_core/gpiob_padoen[17]
+ae210_chip/ae210_core/gpiob_padoen[16]
+ae210_chip/ae210_core/gpiob_padoen[15]
+ae210_chip/ae210_core/gpiob_padoen[14]
+ae210_chip/ae210_core/gpiob_padoen[13]
+ae210_chip/ae210_core/gpiob_padoen[12]
+ae210_chip/ae210_core/gpiob_padoen[11]
+ae210_chip/ae210_core/gpiob_padoen[10]
+ae210_chip/ae210_core/gpiob_padoen[9]
+ae210_chip/ae210_core/gpiob_padoen[8]
+ae210_chip/ae210_core/gpiob_padoen[7]
+ae210_chip/ae210_core/gpiob_padoen[6]
+ae210_chip/ae210_core/gpiob_padoen[5]
+ae210_chip/ae210_core/gpiob_padoen[4]
+ae210_chip/ae210_core/gpiob_padoen[3]
+ae210_chip/ae210_core/gpiob_padoen[2]
+ae210_chip/ae210_core/gpiob_padoen[1]
+ae210_chip/ae210_core/gpiob_padoen[0]
+ae210_chip/ae210_core/gpiob_pull_en[31]
+ae210_chip/ae210_core/gpiob_pull_en[30]
+ae210_chip/ae210_core/gpiob_pull_en[29]
+ae210_chip/ae210_core/gpiob_pull_en[28]
+ae210_chip/ae210_core/gpiob_pull_en[27]
+ae210_chip/ae210_core/gpiob_pull_en[26]
+ae210_chip/ae210_core/gpiob_pull_en[25]
+ae210_chip/ae210_core/gpiob_pull_en[24]
+ae210_chip/ae210_core/gpiob_pull_en[23]
+ae210_chip/ae210_core/gpiob_pull_en[22]
+ae210_chip/ae210_core/gpiob_pull_en[21]
+ae210_chip/ae210_core/gpiob_pull_en[20]
+ae210_chip/ae210_core/gpiob_pull_en[19]
+ae210_chip/ae210_core/gpiob_pull_en[18]
+ae210_chip/ae210_core/gpiob_pull_en[17]
+ae210_chip/ae210_core/gpiob_pull_en[16]
+ae210_chip/ae210_core/gpiob_pull_en[15]
+ae210_chip/ae210_core/gpiob_pull_en[14]
+ae210_chip/ae210_core/gpiob_pull_en[13]
+ae210_chip/ae210_core/gpiob_pull_en[12]
+ae210_chip/ae210_core/gpiob_pull_en[11]
+ae210_chip/ae210_core/gpiob_pull_en[10]
+ae210_chip/ae210_core/gpiob_pull_en[9]
+ae210_chip/ae210_core/gpiob_pull_en[8]
+ae210_chip/ae210_core/gpiob_pull_en[7]
+ae210_chip/ae210_core/gpiob_pull_en[6]
+ae210_chip/ae210_core/gpiob_pull_en[5]
+ae210_chip/ae210_core/gpiob_pull_en[4]
+ae210_chip/ae210_core/gpiob_pull_en[3]
+ae210_chip/ae210_core/gpiob_pull_en[2]
+ae210_chip/ae210_core/gpiob_pull_en[1]
+ae210_chip/ae210_core/gpiob_pull_en[0]
+ae210_chip/ae210_core/gpioc_padout[31]
+ae210_chip/ae210_core/gpioc_padout[30]
+ae210_chip/ae210_core/gpioc_padout[29]
+ae210_chip/ae210_core/gpioc_padout[28]
+ae210_chip/ae210_core/gpioc_padout[27]
+ae210_chip/ae210_core/gpioc_padout[26]
+ae210_chip/ae210_core/gpioc_padout[25]
+ae210_chip/ae210_core/gpioc_padout[24]
+ae210_chip/ae210_core/gpioc_padout[23]
+ae210_chip/ae210_core/gpioc_padout[22]
+ae210_chip/ae210_core/gpioc_padout[21]
+ae210_chip/ae210_core/gpioc_padout[20]
+ae210_chip/ae210_core/gpioc_padout[19]
+ae210_chip/ae210_core/gpioc_padout[18]
+ae210_chip/ae210_core/gpioc_padout[17]
+ae210_chip/ae210_core/gpioc_padout[16]
+ae210_chip/ae210_core/gpioc_padout[15]
+ae210_chip/ae210_core/gpioc_padout[14]
+ae210_chip/ae210_core/gpioc_padout[13]
+ae210_chip/ae210_core/gpioc_padout[12]
+ae210_chip/ae210_core/gpioc_padout[11]
+ae210_chip/ae210_core/gpioc_padout[10]
+ae210_chip/ae210_core/gpioc_padout[9]
+ae210_chip/ae210_core/gpioc_padout[8]
+ae210_chip/ae210_core/gpioc_padout[7]
+ae210_chip/ae210_core/gpioc_padout[6]
+ae210_chip/ae210_core/gpioc_padout[5]
+ae210_chip/ae210_core/gpioc_padout[4]
+ae210_chip/ae210_core/gpioc_padout[3]
+ae210_chip/ae210_core/gpioc_padout[2]
+ae210_chip/ae210_core/gpioc_padout[1]
+ae210_chip/ae210_core/gpioc_padout[0]
+ae210_chip/ae210_core/gpioc_padoen[31]
+ae210_chip/ae210_core/gpioc_padoen[30]
+ae210_chip/ae210_core/gpioc_padoen[29]
+ae210_chip/ae210_core/gpioc_padoen[28]
+ae210_chip/ae210_core/gpioc_padoen[27]
+ae210_chip/ae210_core/gpioc_padoen[26]
+ae210_chip/ae210_core/gpioc_padoen[25]
+ae210_chip/ae210_core/gpioc_padoen[24]
+ae210_chip/ae210_core/gpioc_padoen[23]
+ae210_chip/ae210_core/gpioc_padoen[22]
+ae210_chip/ae210_core/gpioc_padoen[21]
+ae210_chip/ae210_core/gpioc_padoen[20]
+ae210_chip/ae210_core/gpioc_padoen[19]
+ae210_chip/ae210_core/gpioc_padoen[18]
+ae210_chip/ae210_core/gpioc_padoen[17]
+ae210_chip/ae210_core/gpioc_padoen[16]
+ae210_chip/ae210_core/gpioc_padoen[15]
+ae210_chip/ae210_core/gpioc_padoen[14]
+ae210_chip/ae210_core/gpioc_padoen[13]
+ae210_chip/ae210_core/gpioc_padoen[12]
+ae210_chip/ae210_core/gpioc_padoen[11]
+ae210_chip/ae210_core/gpioc_padoen[10]
+ae210_chip/ae210_core/gpioc_padoen[9]
+ae210_chip/ae210_core/gpioc_padoen[8]
+ae210_chip/ae210_core/gpioc_padoen[7]
+ae210_chip/ae210_core/gpioc_padoen[6]
+ae210_chip/ae210_core/gpioc_padoen[5]
+ae210_chip/ae210_core/gpioc_padoen[4]
+ae210_chip/ae210_core/gpioc_padoen[3]
+ae210_chip/ae210_core/gpioc_padoen[2]
+ae210_chip/ae210_core/gpioc_padoen[1]
+ae210_chip/ae210_core/gpioc_padoen[0]
+ae210_chip/ae210_core/gpioc_pull_en[31]
+ae210_chip/ae210_core/gpioc_pull_en[30]
+ae210_chip/ae210_core/gpioc_pull_en[29]
+ae210_chip/ae210_core/gpioc_pull_en[28]
+ae210_chip/ae210_core/gpioc_pull_en[27]
+ae210_chip/ae210_core/gpioc_pull_en[26]
+ae210_chip/ae210_core/gpioc_pull_en[25]
+ae210_chip/ae210_core/gpioc_pull_en[24]
+ae210_chip/ae210_core/gpioc_pull_en[23]
+ae210_chip/ae210_core/gpioc_pull_en[22]
+ae210_chip/ae210_core/gpioc_pull_en[21]
+ae210_chip/ae210_core/gpioc_pull_en[20]
+ae210_chip/ae210_core/gpioc_pull_en[19]
+ae210_chip/ae210_core/gpioc_pull_en[18]
+ae210_chip/ae210_core/gpioc_pull_en[17]
+ae210_chip/ae210_core/gpioc_pull_en[16]
+ae210_chip/ae210_core/gpioc_pull_en[15]
+ae210_chip/ae210_core/gpioc_pull_en[14]
+ae210_chip/ae210_core/gpioc_pull_en[13]
+ae210_chip/ae210_core/gpioc_pull_en[12]
+ae210_chip/ae210_core/gpioc_pull_en[11]
+ae210_chip/ae210_core/gpioc_pull_en[10]
+ae210_chip/ae210_core/gpioc_pull_en[9]
+ae210_chip/ae210_core/gpioc_pull_en[8]
+ae210_chip/ae210_core/gpioc_pull_en[7]
+ae210_chip/ae210_core/gpioc_pull_en[6]
+ae210_chip/ae210_core/gpioc_pull_en[5]
+ae210_chip/ae210_core/gpioc_pull_en[4]
+ae210_chip/ae210_core/gpioc_pull_en[3]
+ae210_chip/ae210_core/gpioc_pull_en[2]
+ae210_chip/ae210_core/gpioc_pull_en[1]
+ae210_chip/ae210_core/gpioc_pull_en[0]
+ae210_chip/ae210_core/gpiod_padoen[31]
+ae210_chip/ae210_core/gpiod_padoen[30]
+ae210_chip/ae210_core/gpiod_padoen[29]
+ae210_chip/ae210_core/gpiod_padoen[28]
+ae210_chip/ae210_core/gpiod_padoen[27]
+ae210_chip/ae210_core/gpiod_padoen[26]
+ae210_chip/ae210_core/gpiod_padoen[25]
+ae210_chip/ae210_core/gpiod_padoen[24]
+ae210_chip/ae210_core/gpiod_padoen[23]
+ae210_chip/ae210_core/gpiod_padoen[22]
+ae210_chip/ae210_core/gpiod_padoen[21]
+ae210_chip/ae210_core/gpiod_padoen[20]
+ae210_chip/ae210_core/gpiod_padoen[19]
+ae210_chip/ae210_core/gpiod_padoen[18]
+ae210_chip/ae210_core/gpiod_padoen[17]
+ae210_chip/ae210_core/gpiod_padoen[16]
+ae210_chip/ae210_core/gpiod_padoen[15]
+ae210_chip/ae210_core/gpiod_padoen[14]
+ae210_chip/ae210_core/gpiod_padoen[13]
+ae210_chip/ae210_core/gpiod_padoen[12]
+ae210_chip/ae210_core/gpiod_padoen[11]
+ae210_chip/ae210_core/gpiod_padoen[10]
+ae210_chip/ae210_core/gpiod_padoen[9]
+ae210_chip/ae210_core/gpiod_padoen[8]
+ae210_chip/ae210_core/gpiod_padoen[7]
+ae210_chip/ae210_core/gpiod_padoen[6]
+ae210_chip/ae210_core/gpiod_padoen[5]
+ae210_chip/ae210_core/gpiod_padoen[4]
+ae210_chip/ae210_core/gpiod_padoen[3]
+ae210_chip/ae210_core/gpiod_padoen[2]
+ae210_chip/ae210_core/gpiod_padoen[1]
+ae210_chip/ae210_core/gpiod_padoen[0]
+ae210_chip/ae210_core/HADDRahb2cm0_async[31]
+ae210_chip/ae210_core/HADDRahb2cm0_async[30]
+ae210_chip/ae210_core/HADDRahb2cm0_async[29]
+ae210_chip/ae210_core/HADDRahb2cm0_async[28]
+ae210_chip/ae210_core/HADDRahb2cm0_async[27]
+ae210_chip/ae210_core/HADDRahb2cm0_async[26]
+ae210_chip/ae210_core/HADDRahb2cm0_async[25]
+ae210_chip/ae210_core/HADDRahb2cm0_async[24]
+ae210_chip/ae210_core/HADDRahb2cm0_async[23]
+ae210_chip/ae210_core/HADDRahb2cm0_async[22]
+ae210_chip/ae210_core/HADDRahb2cm0_async[21]
+ae210_chip/ae210_core/HADDRahb2cm0_async[20]
+ae210_chip/ae210_core/HADDRahb2cm0_async[19]
+ae210_chip/ae210_core/HADDRahb2cm0_async[18]
+ae210_chip/ae210_core/HADDRahb2cm0_async[17]
+ae210_chip/ae210_core/HADDRahb2cm0_async[16]
+ae210_chip/ae210_core/HADDRahb2cm0_async[15]
+ae210_chip/ae210_core/HADDRahb2cm0_async[14]
+ae210_chip/ae210_core/HADDRahb2cm0_async[13]
+ae210_chip/ae210_core/HADDRahb2cm0_async[12]
+ae210_chip/ae210_core/HADDRahb2cm0_async[11]
+ae210_chip/ae210_core/HADDRahb2cm0_async[10]
+ae210_chip/ae210_core/HADDRahb2cm0_async[9]
+ae210_chip/ae210_core/HADDRahb2cm0_async[8]
+ae210_chip/ae210_core/HADDRahb2cm0_async[7]
+ae210_chip/ae210_core/HADDRahb2cm0_async[6]
+ae210_chip/ae210_core/HADDRahb2cm0_async[5]
+ae210_chip/ae210_core/HADDRahb2cm0_async[4]
+ae210_chip/ae210_core/HADDRahb2cm0_async[3]
+ae210_chip/ae210_core/HADDRahb2cm0_async[2]
+ae210_chip/ae210_core/HADDRahb2cm0_async[1]
+ae210_chip/ae210_core/HADDRahb2cm0_async[0]
+ae210_chip/ae210_core/HTRANSahb2cm0_async[1]
+ae210_chip/ae210_core/HTRANSahb2cm0_async[0]
+ae210_chip/ae210_core/HWRITEahb2cm0_async
+ae210_chip/ae210_core/HSIZEahb2cm0_async[2]
+ae210_chip/ae210_core/HSIZEahb2cm0_async[1]
+ae210_chip/ae210_core/HSIZEahb2cm0_async[0]
+ae210_chip/ae210_core/HBURSTahb2cm0_async[2]
+ae210_chip/ae210_core/HBURSTahb2cm0_async[1]
+ae210_chip/ae210_core/HBURSTahb2cm0_async[0]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[31]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[30]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[29]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[28]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[27]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[26]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[25]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[24]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[23]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[22]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[21]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[20]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[19]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[18]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[17]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[16]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[15]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[14]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[13]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[12]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[11]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[10]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[9]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[8]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[7]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[6]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[5]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[4]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[3]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[2]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[1]
+ae210_chip/ae210_core/HWDATAahb2cm0_async[0]
+ae210_chip/ae210_core/int_locsc0
+ae210_chip/ae210_core/int_timer7
+ae210_chip/ae210_core/int_timer6
+ae210_chip/ae210_core/int_timer5
+ae210_chip/ae210_core/int_spi1
+ae210_chip/ae210_core/int_uart2
+ae210_chip/ae210_core/int_gpio
+ae210_chip/ae210_core/int_lcd
+}

Simulate/user/script/DC/dont_use.tcl

@@ -0,0 +1,25 @@
+foreach one_lib_name [ list \
+                    ${LIB_SC_9T_HVT_NAME_SYNOPSYS}  \
+                    ${LIB_SC_9T_RVT_NAME_SYNOPSYS}  \
+                  ] {
+set_dont_use $one_lib_name/*_0P*
+set_dont_use $one_lib_name/SE*_BUF_*1
+set_dont_use $one_lib_name/SE*_INV_*1
+set_dont_use $one_lib_name/*_12
+set_dont_use $one_lib_name/*_16
+set_dont_use $one_lib_name/*_20
+set_dont_use $one_lib_name/*_24
+set_dont_use $one_lib_name/*_32
+set_dont_use $one_lib_name/*_64
+set_dont_use $one_lib_name/*_*Y2_*
+set_dont_use $one_lib_name/*CAP*
+set_dont_use $one_lib_name/*_DEL*
+set_dont_use $one_lib_name/*_CK*
+set_dont_use $one_lib_name/*_TIE*
+set_dont_use $one_lib_name/*_LD*
+set_dont_use $one_lib_name/*_FSD*
+set_dont_use $one_lib_name/SE*_CKGTNLT*
+set_dont_use $one_lib_name/SE*_CKGTPLS*
+}
+remove_attribute ${LIB_SC_9T_HVT_NAME_SYNOPSYS}/*_LD* dont_use
+remove_attribute ${LIB_SC_9T_RVT_NAME_SYNOPSYS}/*_LD* dont_use

Simulate/user/script/DC/gpio_timing.tcl

@@ -0,0 +1,4 @@
+set gpio_ports [get_ports * -filter "full_name =~ *GPIO*"]
+foreach_in_collection gpio_port $gpio_ports {
+	report_timing -through $gpio_port -nosp >> ./rpt/GPIO_timing.rpt 
+}

Simulate/user/script/DC/group_path.tcl

@@ -0,0 +1,16 @@
+remove_path_group -all
+set clock_ports [get_ports -quiet [all_fanout -clock_tree -flat]]
+set all_inputs [all_inputs]
+set all_outputs [all_outputs]
+set all_nonclk_inputs [remove_from_collection $all_inputs $clock_ports]
+set all_nonclk_outputs [remove_from_collection $all_outputs $clock_ports]
+set all_icgs [get_cells -hier -filter "is_integrated_clock_gating_cell == true"]
+set all_reg [all_registers]
+set all_reg [remove_from_collection $all_reg $all_icgs]
+
+group_path -from $all_reg -to $all_reg -name reg2reg
+group_path -from $all_reg -to $all_nonclk_outputs -name reg2out
+group_path -from $all_nonclk_inputs -to $all_reg -name in2reg
+group_path -from $all_nonclk_inputs -to $all_nonclk_outputs -name in2out
+#group_path -from $all_reg -to $all_icgs -name reg2gate
+report_path_group

Simulate/user/script/DC/kk

@@ -0,0 +1,519 @@
+#========================================
+# List all IPs RTL file here
+# NOTE: no blank line allowed
+#========================================
+
+set search_path [list $search_path \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/include \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/define \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/apc \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/scm \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/locsc \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/pwm \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/user_define \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/gpio \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/tbench/verilog \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/scm \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/logical/cortexm0_dap/verilog \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/logical/ualdis/verilog \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/hash \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/rng \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/fd \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/crc \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/vpwm \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/rsa \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/eaag \
+]
+set RTL_FILE_LIST [list \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/ae210_chip.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/ae210_core.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/interconnect/sy13.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/cm0ikmcu/verilog/CM0IKMCU.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2Apb/AhbToApb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2Apb/peripheral.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/async_clkmux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio/n10_pad_mux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio/n10_gpio.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/nds_lib.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/ip_fpga/BUFG.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/ae210_cpu_subsystem_n10.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl/n10_core.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/sqi/txdatactl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/edm/hdl/reg_jtagedm_ver.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/fcu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_arbiter.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_cctl_path.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_control_path.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_lru_policy_manager.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_random_policy_manager.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_control_unit.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_data_path.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_memory.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ilm_arbiter.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_addr_mux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_adsp_load_alignment.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_cntrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_data_mux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_dirty_mem.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_fb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_load_alignment.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_lru_mem.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_mem.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/memory/model/icache_ram.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/memory/model/dcache_ram.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_sb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_store_alignment.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_wb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/dtlb_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/hptwk_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/itlb_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mmu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mmu_gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mtlb_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mtlb_plru.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/pcu/hdl/pcu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl/reset_gen.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/b16_bnrtr_dtt.v \
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+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_bcm06.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_bcm21.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_bcm41.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_bcm57.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_biu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_clk_gen.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_dma.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_fifo.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_intctl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_mstfsm.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_regfile.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_rx_filter.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_rx_shift.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_slvfsm.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_sync.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_toggle.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c_tx_shift.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/i2c_dw/DW_apb_i2c-undef.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_cc_constants.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_bcm_params.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_async_rst_gen.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_bclk_gen.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_bcm06.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_bcm21.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_bcm23.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_bcm25.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_bcm57.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_biu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_fifo.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_mc_sync.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_regfile.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_rst.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_rx.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_sync.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/uart_dw/DW_apb_uart_to_det.v \

Simulate/user/script/DC/report_constraint

@@ -0,0 +1,447 @@
+2.  Synopsys Commands                                        Command Reference
+                               report_constraint
+
+NAME
+       report_constraint
+              Displays constraint-related information about a design.
+
+SYNTAX
+       status report_constraint
+               [-all_violators]
+               [-verbose]
+               [-significant_digits digits]
+               [-max_area]
+               [-max_delay]
+               [-critical_range]
+               [-min_delay]
+               [-max_capacitance]
+               [-min_capacitance]
+               [-max_transition]
+               [-max_fanout]
+               [-cell_degradation]
+               [-max_toggle_rate]
+               [-min_porosity]
+               [-max_dynamic_power]
+               [-max_leakage_power]
+               [-max_total_power]
+               [-max_net_length]
+               [-connection_class]
+               [-multiport_net]
+               [-nosplit]
+               [-min_pulse_width]
+               [-min_period]
+               [-scenarios scenario_list]
+               [-ignore_infeasible_paths]
+
+   Data Types
+       digits            integer
+       scenario_list     list
+
+ARGUMENTS
+       -all_violators
+              Displays  a  summary  of all of the optimization and design rule
+              constraints with violations in the current design.  The -verbose
+              option  provides  detailed  information  about constraint viola-
+              tions.  Multiple violations for a given constraint are listed in
+              order from largest to smallest violation.
+
+       -verbose
+              Displays more detail about constraint calculations.
+
+       -significant_digits digits
+              Specifies the number of digits to the right of the decimal point
+              that are to be reported.  The digits value must be between 0 and
+              13.   The  default is 2.  This option overrides the value set by
+              the report_default_significant_digits variable.
+
+       -max_area
+              Displays only the max_area constraint information.  The  default
+              behavior (without this option and similar options) is to display
+              all optimization and design rule constraints.
+
+       -max_delay
+              Displays only the max_delay and setup information.
+
+       -critical_range
+              Displays  only  the  critical_range  information.   The   criti-
+              cal_range  is  a  design  rule that directs the tool to optimize
+              near-critical paths along with the most critical path.
+
+       -min_delay
+              Displays only the min_delay and hold information.
+
+       -max_capacitance
+              Displays only the max_capacitance constraint  information.   The
+              max_capacitance  constraint  is  a  design  rule that limits the
+              total capacitance on a net.
+
+       -min_capacitance
+              Displays only the min_capacitance constraint  information.   The
+              min_capacitance constraint is a design rule that ensures a mini-
+              mum total capacitance on a net.
+
+       -max_transition
+              Displays only the max_transition  constraint  information.   The
+              max_transition constraint is a design rule that limits the tran-
+              sition time on a net.  If  the  library  uses  the  cmos2  delay
+              model, this option shows the max_edge_rate information.
+
+       -max_fanout
+              Displays  only  the max_fanout constraint information.  The con-
+              straint is a design rule that limits the fanout_load on a net.
+
+       -cell_degradation
+              Displays only the cell_degradation constraint information.   The
+              cell_degradation  constraint  is  a  design rule that limits the
+              total capacitance on a net, with  the  limit  depending  on  the
+              transition times at the inputs of the cell.
+
+       -max_toggle_rate
+              Displays only the max_toggle_rate constraint information.
+
+       -min_porosity
+              Displays  only  the  min_porosity  constraint  information.  The
+              min_porosity  constraint  is  an  optimization  constraint   for
+              routability.
+
+       -max_dynamic_power
+              Displays only the max_dynamic_power constraint information.  The
+              default behavior (without this option and similar  power-related
+              options)  is  to  display all types of power constraint informa-
+              tion.  Queries for power constraint information are  valid  only
+              if a power-related license is available.
+
+       -max_leakage_power
+              Displays only the max_leakage_power constraint information.
+
+       -max_total_power
+              Displays only the max_total_power constraint information.
+
+       -max_net_length
+              Displays   only   max_net_length  constraint  information.   The
+              max_net_length constraint is a design rule that limits the route
+              length  of a net. For more information, see the man page for the
+              set_max_net_length command.
+
+       -connection_class
+              Displays only the connection_class constraint information.   The
+              connection_class constraint is displayed only if there is a con-
+              nection_class violation. For more information, see the man  page
+              for the set_connection_class command.
+
+       -multiport_net
+              Displays  only  the  multiport_net constraint information.  This
+              constraint specifies whether multiple output ports can  be  con-
+              nected  to  a  given net. For more information, see the man page
+              for the set_fix_multiple_port_nets command.
+
+       -nosplit
+              Prevents line splitting and facilitates writing applications  to
+              extract  information from the report output.  Most of the design
+              information is listed in fixed-width columns.  If  the  informa-
+              tion for a given field exceeds the width of the column, the next
+              field begins on a new line, starting in the correct column.
+
+       -min_pulse_width
+              Displays only the min_pulse_width constraint  information.   The
+              min_pulse_width constraint is a design rule that limits the min-
+              imum duration of clock pulses in the clock network.
+
+       -min_period
+              Displays only the minimum period  constraint  information.   The
+              min_period  constraint  is  a  design  rule  that sets a minimum
+              period on a clock signal. The min_period check is supported only
+              for ideal clocks.
+
+       -scenarios scenario_list
+              Reports  constraints for the specified scenarios of a multi-sce-
+              nario design.  Each scenario is reported  separately.   Inactive
+              scenarios are not reported.
+
+              If  you  do  not  use this option, the report_constraint command
+              reports constraints on all active scenarios, except when you use
+              the -all_violators or -verbose option.  If you use these options
+              but not the -scenarios  option,  the  report_constraint  command
+              reports constraints only on the current scenario.
+
+       -ignore_infeasible_paths
+              Ignores  all  the  paths flagged as infeasible during the latest
+              compilation.
+
+DESCRIPTION
+       The report_constraint command displays the  following  information  for
+       the constraints on the current design:
+
+        o Whether the constraint was violated or met
+
+        o By how much the constraint value was violated or met
+
+        o The design object that was the worst violator
+
+       The  maximum delay information shows cost by path group.  This includes
+       violations of setup time on registers or ports with  output  delay,  as
+       well  as violations of set_max_delay commands.  The total maximum delay
+       cost is the sum of each group's weighted cost.  For details on creating
+       path groups, refer to the group_path command man page.  To see the cur-
+       rent path groups in the design, use the report_path_group command.
+
+       The minimum delay cost includes violations of hold time on registers or
+       ports  with  output  delay  as well as violations of set_min_delay com-
+       mands.
+
+       In the path delay reports, if a pin drives a high-fanout net,  this  is
+       indicated  in the report by a # symbol between the incremental and path
+       timing values.  Creation and  usage  of  scenarios  is  available  with
+       Design Compiler Graphical.
+
+   Multicorner-Multimode Support
+       By  default,  this  command uses information from all active scenarios.
+       You can select different scenarios by using the -scenarios option.
+
+EXAMPLES
+       The following example shows brief constraint information for  the  cur-
+       rent design:
+
+         prompt> report_constraint
+
+         ****************************************
+         Report : constraint
+         Design : counter
+         Version: 1998.02
+         Date   : Fri Dec 26 15:49:46 1997
+         ****************************************
+
+                                                            Weighted
+             Group (max_delay/setup)      Cost     Weight     Cost
+             -----------------------------------------------------
+             CLK                          0.00      1.00      0.00
+             default                      0.00      1.00      0.00
+             -----------------------------------------------------
+             max_delay/setup                                  0.00
+
+                                       Total Neg  Critical
+             Group (critical_range)      Slack    Endpoints   Cost
+             -----------------------------------------------------
+             CLK                          0.00         0      0.00
+             default                      0.00         0      0.00
+             -----------------------------------------------------
+             critical_range                                   0.00
+
+             Constraint                                       Cost
+             -----------------------------------------------------
+             max_transition                                   0.00 (MET)
+             max_fanout                                       0.00 (MET)
+             max_delay/setup                                  0.00 (MET)
+             sequential_clock_pulse_width                     0.00 (MET)
+             critical_range                                   0.00 (MET)
+             min_delay/hold                                   0.40 (VIOLATED)
+             max_leakage_power                                6.00 (VIOLATED)
+             max_dynamic_power                               14.03 (VIOLATED)
+             max_area                                        48.00 (VIOLATED)
+
+       The  following example displays detailed constraint information for the
+       current design:
+
+         prompt> report_constraint -verbose
+
+         ****************************************
+         Report : constraint
+                 -verbose
+         Design : counter
+         Version: v3.1a
+         Date   : Tue 1992
+         ****************************************
+
+           Startpoint: ffb (rising edge-triggered flip-flop clocked by CLK)
+           Endpoint: ffd (rising edge-triggered flip-flop clocked by CLK)
+           Path Group: CLK
+           Path Type: max
+
+           Point                                    Incr       Path
+           -----------------------------------------------------------
+           clock CLK (rise edge)                    0.00       0.00
+           startpoint clock skew (ideal)            0.00       0.00
+           startpoint clock uncertainty             0.00       0.00
+           ffb/CP (FD3)                             0.00       0.00 r
+           ffb/QN (FD3)                             2.42       2.42 r
+           w/Z (ND4)                                0.59       3.01 f
+           q/Z (EO)                                 1.13       4.14 f
+           j/Z (AO2)                                1.08       5.22 r
+           ffd/D (FDS2)                             0.00       5.22 r
+           data arrival time                                   5.22
+
+           clock CLK (rise edge)                   10.00      10.00
+           endpoint clock skew (ideal)              0.00      10.00
+           endpoint clock uncertainty               0.00      10.00
+           ffd/CP (FDS2)                            0.00      10.00 r
+           library setup time                      -0.90       9.10
+           data required time                                  9.10
+           -----------------------------------------------------------
+           data required time                                  9.10
+           data arrival time                                  -5.22
+           -----------------------------------------------------------
+           slack (MET)                                         3.88
+
+             Design: counter
+
+             max_area              30.00
+           - Current Area          78.00
+           ------------------------------
+             Slack                -48.00  (VIOLATED)
+
+             Design: counter
+
+             max_leakage_power         70.00
+           - Current Leakage Power     76.00
+           ----------------------------------
+             Slack                     -6.00  (VIOLATED)
+
+             Design: counter
+
+             max_dynamic_power        500.00
+           - Current Dynamic Power    514.03
+           ----------------------------------
+             Slack                    -14.03  (VIOLATED)
+
+       The following example displays detailed information on only those  con-
+       straints that have violations:
+
+         prompt> report_constraint -all_violators -verbose
+
+         ****************************************
+         Report : constraint
+                 -all_violators
+                 -verbose
+         Design : led
+         Version: v3.2a
+         Date   : Tue Jan  3 13:00:45 1995
+         ****************************************
+
+           Startpoint: b (input port)
+           Endpoint: z5 (output port)
+           Path Group: default
+           Path Type: max
+
+           Point                                    Incr       Path
+           -----------------------------------------------------------
+           input external delay                     0.00       0.00 r
+           b (in)                                   0.00       0.00 r
+           U5/Z (IV)                                1.32       1.32 f
+           U3/Z (NR2)                               3.35       4.67 r
+           U18/Z (AO6)                              0.73       5.40 f
+           U22/Z (AO4)                              1.42       6.82 r
+           z5 (out)                                 0.00       6.82 r
+           data arrival time                                   6.82
+
+           max_delay                                6.50       6.50
+           output external delay                    0.00       6.50
+           data required time                                  6.50
+           -----------------------------------------------------------
+           data required time                                  6.50
+           data arrival time                                  -6.82
+           -----------------------------------------------------------
+           slack (VIOLATED)                                   -0.32
+
+           Startpoint: c (input port)
+           Endpoint: z3 (output port)
+           Path Group: default
+           Path Type: max
+
+           Point                                    Incr       Path
+           -----------------------------------------------------------
+           input external delay                     0.00       0.00 r
+           c (in)                                   0.00       0.00 r
+           U6/Z (IV)                                1.34       1.34 f
+           U2/Z (NR2)                               3.35       4.69 r
+           U15/Z (AO7)                              0.87       5.56 f
+           U24/Z (AO3)                              1.02       6.57 r
+           z3 (out)                                 0.00       6.57 r
+           data arrival time                                   6.57
+
+           max_delay                                6.50       6.50
+           output external delay                    0.00       6.50
+           data required time                                  6.50
+           -----------------------------------------------------------
+           data required time                                  6.50
+           data arrival time                                  -6.57
+           -----------------------------------------------------------
+           slack (VIOLATED)                                   -0.07
+
+             Net: a
+
+             max_transition         1.00
+           - Transition Time        1.26
+           ------------------------------
+             Slack                 -0.26  (VIOLATED)
+
+             Net: a
+
+             max_fanout             5.00
+           - Fanout                 7.00
+           ------------------------------
+             Slack                 -2.00  (VIOLATED)
+
+             Design: led
+
+             max_area              30.00
+           - Current Area          36.00
+           ------------------------------
+             Slack                 -6.00  (VIOLATED)
+
+             Design: led
+
+             max_dynamic_power       1000.00
+           - Current Dynamic Power   1254.81
+           ----------------------------------
+             Slack                   -254.81  (VIOLATED)
+
+       The   following   example   displays   the  max_area,  max_delay/setup,
+       min_delay/hold, and max_leakage_power constraint information:
+
+         prompt> report_constraint -max_area -max_delay -min_delay \
+            -max_leakage_power
+
+         ****************************************
+         Report : constraint
+                  -max_area
+                  -max_delay
+                  -min_delay
+                  -max_leakage_power
+         Design : led
+         Version: v3.2a
+         Date   : Tue Jan  3 13:00:56 1995
+         ****************************************
+
+                                                            Weighted
+             Group (max_delay/setup)      Cost     Weight     Cost
+             -----------------------------------------------------
+             default                      0.32      1.00      0.32
+             -----------------------------------------------------
+             max_delay/setup                                  0.32
+
+             Constraint                                       Cost
+             -----------------------------------------------------
+             max_delay/setup                                  0.32 (VIOLATED)
+             max_area                                         6.00 (VIOLATED)
+
+         --------------------------------------------------------------------
+
+SEE ALSO
+       create_clock(2)
+       group_path(2)
+       report_clock(2)
+       report_design(2)
+       report_path_group(2)
+       report_timing(2)
+       report_timing_requirements(2)
+       report_min_pulse_width(2)
+       set_critical_range(2)
+       set_fix_multiple_port_nets(2)
+       set_max_area(2)
+       set_max_delay(2)
+       set_max_dynamic_power(2)
+       set_max_leakage_power(2)
+       set_max_net_length(2)
+
+                          Version J-2014.09-SP3
+            Copyright (c) 2015 Synopsys, Inc. All rights reserved.

Simulate/user/script/DC/rtl_20170721.upf

@@ -0,0 +1,181 @@
+######################
+set_design_top sy13
+set_scope .
+
+################################
+#######create power domain
+#################################
+# ae210_chip is power_domian 1
+# sys_top is power_domain 2
+#
+
+create_power_domain PD_TOP -include_scope
+create_power_domain PD_sys    -elements {u_mcu/u_sys_top}
+create_power_domain PD_ae210  -elements {ae210_chip/ae210_core}
+
+####################
+###create_power_supply port
+##################
+
+create_supply_port PORT_VCC -domain PD_TOP -direction in
+create_supply_port PORT_VSS -domain PD_TOP -direction in
+
+####################
+###create_power_supply net
+##################
+
+create_supply_net  NET_VCC  -domain PD_TOP
+create_supply_net  NET_VSS  -domain PD_TOP
+
+create_supply_net NET_VCC_sys -domain PD_sys
+create_supply_net NET_VSS     -domain PD_sys -reuse
+create_supply_net NET_VCC     -domain PD_sys -reuse
+
+
+create_supply_net NET_VCC_ae210 -domain PD_ae210
+create_supply_net NET_VSS       -domain PD_ae210 -reuse
+create_supply_net NET_VCC       -domain PD_ae210 -reuse
+
+#####################
+#connect power supplu net with power supply port
+#####################
+connect_supply_net NET_VCC -ports {PORT_VCC}
+connect_supply_net NET_VSS -ports {PORT_VSS}
+
+#####################
+#set domain supply net
+#####################
+
+set_domain_supply_net PD_TOP   -primary_power_net {NET_VCC}        -primary_ground_net {NET_VSS}
+set_domain_supply_net PD_sys   -primary_power_net {NET_VCC_sys}    -primary_ground_net {NET_VSS}
+set_domain_supply_net PD_ae210 -primary_power_net {NET_VCC_ae210}  -primary_ground_net {NET_VSS}
+
+##########################
+#create power switch
+##########################
+create_power_switch sw_ae210 -domain PD_ae210 \
+                             -input_supply_port  {in_port   NET_VCC } \
+                             -output_supply_port {out_port  NET_VCC_ae210  } \
+                             -control_port       {ctrl_port  u_mcu/u_aoss_wrap/N10PwrReq } \
+                             -ack_port           {ack_port   u_mcu/u_aoss_wrap/N10PwrAck {ctrl_port}} \
+                             -on_state           {ON  in_port {ctrl_port}} \
+                             -off_state          {OFF {!ctrl_port}}
+
+
+create_power_switch sw_sys -domain PD_sys  \
+                           -input_supply_port  {in_port  NET_VCC } \
+                           -output_supply_port {out_port NET_VCC_sys  } \
+                           -control_port       {ctrl_port  u_mcu/u_aoss_wrap/sp_pwroff_req } \
+                           -ack_port           {ack_port   u_mcu/u_aoss_wrap/sp_pwroff_ack {ctrl_port}} \
+                           -on_state           {ON  in_port {ctrl_port}} \
+                           -off_state          {OFF {!ctrl_port}}
+
+
+############################
+#map power switch
+##############
+
+#map_power_switch sw_sys    -domain PD_sys    -lib_cells {PEH_PGATDRV_OW_12}
+#map_power_switch sw_ae210  -domain PD_ae210  -lib_cells {PEH_PGATDRV_OW_12}
+###############################
+#creat_isolation_cell
+#######################
+################################
+
+set_isolation PD_sys_clamp_low -domain PD_sys \
+                                -clamp_value 0 \
+                                -applies_to outputs \
+                                -elements { \
+                                u_mcu/u_sys_top/rst_pmu \
+                                u_mcu/u_sys_top/HSELahb2n10 \
+                                u_mcu/u_sys_top/HADDRahb2pmu_async \
+                                u_mcu/u_sys_top/HTRANSahb2pmu_async \
+                                u_mcu/u_sys_top/HWRITEahb2pmu_async \
+                                u_mcu/u_sys_top/HSIZEahb2pmu_async \
+                                u_mcu/u_sys_top/HBURSTahb2pmu_async \
+                                u_mcu/u_sys_top/HPROTahb2pmu_async \
+                                u_mcu/u_sys_top/HMASTERahb2pmu_async \
+                                u_mcu/u_sys_top/HWDATAahb2pmu_async \
+                                u_mcu/u_sys_top/HMASTERahb2cm0_async \
+                                u_mcu/u_sys_top/test_en \
+                                u_mcu/u_sys_top/scan_en \
+                                u_mcu/u_sys_top/scan_mode \
+                                u_mcu/u_sys_top/ana_mode \
+                               } \
+                                -isolation_power_net NET_VCC \
+                                -isolation_ground_net NET_VSS
+
+
+set_isolation_control PD_sys_clamp_low -domain PD_sys \
+                                       -isolation_signal  {u_mcu/u_aoss_wrap/u_pmu/pmu_ctrl_iso_en} \
+                                       -isolation_sense   {low} \
+                                       -location {parent}
+
+map_isolation_cell PD_sys_clamp_low  -domain PD_sys -lib_cells {PEH_ISOS1CL0_W_8}
+
+################################
+
+set_isolation PD_ae210_clamp_low -domain PD_ae210 \
+                                -isolation_power_net NET_VCC \
+                                -isolation_ground_net NET_VSS \
+                                -clamp_value 0 \
+                                -applies_to outputs \
+                                -elements { \
+                                ae210_chip/ae210_core/HADDRahb2cm0_async \
+                                ae210_chip/ae210_core/HTRANSahb2cm0_async \
+                                ae210_chip/ae210_core/HWRITEahb2cm0_async \
+                                ae210_chip/ae210_core/HSIZEahb2cm0_async \
+                                ae210_chip/ae210_core/HBURSTahb2cm0_async \
+                                ae210_chip/ae210_core/HMASTERahb2cm0_async \
+                                ae210_chip/ae210_core/HWDATAahb2cm0_async \
+                                ae210_chip/ae210_core/HRDATAahb2cm0_async \
+                                ae210_chip/ae210_core/HRESPahb2cm0_async \
+				ae210_chip/ae210_core/HREADYOUTahb2cm0_async \
+                                ae210_chip/ae210_core/gpioa_padout \
+                                ae210_chip/ae210_core/gpioa_padoen \
+                                ae210_chip/ae210_core/gpioa_pull_en \
+                                ae210_chip/ae210_core/gpiob_padout \
+                                ae210_chip/ae210_core/gpiob_padoen \
+                                ae210_chip/ae210_core/gpiob_pull_en \
+                                ae210_chip/ae210_core/gpioc_padout \
+                                ae210_chip/ae210_core/gpioc_padoen \
+                                ae210_chip/ae210_core/gpioc_pull_en \
+                                ae210_chip/ae210_core/gpioc_padout \
+                                ae210_chip/ae210_core/gpiod_padoen \
+                                ae210_chip/ae210_core/gpiod_pull_en \
+                                ae210_chip/ae210_core/int_locsc0 \
+                                ae210_chip/ae210_core/int_timer7 \
+                                ae210_chip/ae210_core/int_timer6 \
+                                ae210_chip/ae210_core/int_timer5 \
+                                ae210_chip/ae210_core/int_timer4 \
+                                ae210_chip/ae210_core/int_pwm \
+                                ae210_chip/ae210_core/int_i2c1 \
+                                ae210_chip/ae210_core/int_spi1 \
+                                ae210_chip/ae210_core/int_uart2 \
+                                ae210_chip/ae210_core/int_gpio \
+                                ae210_chip/ae210_core/int_lcd \
+                                }
+
+#set_isolation PD_ae210_clamp_high -domain PD_ae210 \ 
+#                                -isolation_power_net NET_VCC \
+#                                -isolation_ground_net NET_VSS \
+#                                -clamp_value 1 \
+#                                -applies_to outputs
+#                                       -element {}
+
+set_isolation_control PD_ae210_clamp_low -domain PD_ae210 \
+                                       -isolation_signal  {u_mcu/u_aoss_wrap/N10IsoEn} \
+                                       -isolation_sense   {low} \
+                                       -location {parent}
+
+#set_isolation_control PD_ae210_clamp_high -domain PD_ae210 \
+#                                       -isolation_signal  {u_mcu/u_sys_top/SppIsoEn} \
+#                                       -isolation_sense   {low} \
+#                                       -location {parent}
+
+map_isolation_cell PD_ae210_clamp_low  -domain PD_ae210 -lib_cells {PEH_ISOS1CL0_W_8}
+#map_isolation_cell PD_ae210_clamp_high  -domain PD_ae210 -lib_cells {PEH_ISOS0CL1_W_8}
+
+################################
+#set_design_attributes -attribute SNPS_reinit TRUE
+################################

Simulate/user/script/DC/rtl_list.lst

@@ -0,0 +1,537 @@
+set search_path  [list  $search_path   \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/define \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/apc \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/include \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/scm \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/pwm \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/user_define \
+]
+
+set RTL_FILE_LIST [ list \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/ae210_core.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2Apb/AhbToApb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2Apb/peripheral.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/async_clkmux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio/n10_pad_mux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio/n10_gpio.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/nds_lib.v \
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/ip_fpga/BUFG.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/ae210_cpu_subsystem_n10.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl/n10_core.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/sqi/txdatactl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/edm/hdl/reg_jtagedm_ver.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/fcu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_arbiter.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_cctl_path.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_control_path.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_lru_policy_manager.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_random_policy_manager.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_control_unit.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_data_path.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_memory.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ilm_arbiter.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_addr_mux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_adsp_load_alignment.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_cntrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_data_mux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_dirty_mem.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_fb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_load_alignment.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_lru_mem.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_mem.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/memory/model/icache_ram.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/memory/model/dcache_ram.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_sb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_store_alignment.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_wb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/dtlb_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/hptwk_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/itlb_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mmu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mmu_gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mtlb_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mtlb_plru.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/pcu/hdl/pcu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl/reset_gen.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/b16_bnrtr_dtt.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_adu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_alu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_ctl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_mdu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_mdu_mul.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_sau.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ifu_ctl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/iiu_ctl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/iiu_iq.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/iiu_rf.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/iru_ctl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/sru_cpu_ver.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/sru_ctl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/macro/hdl/sync_l2l.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/memory/model/btb_ram.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/tr_node1.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/tr_node2.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ucore.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ucore_gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/sdp_wrapper/hdl/sdp_wrapper.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_vip/models/cpif/hdl/cop_mux.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/csa3_2.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_clk_gen.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_cpif.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_dsu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_eu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_eu_ctr.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_eu_dp.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_iiu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_mul.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_rf.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/ncesfp.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_ctrl.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_engine.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_hru.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_master.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_regs.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_slave.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_top.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/sfifo_10x10.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/sfifo_16x16.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/sfifo_4x26.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BP010_a2bm_BusMatrix_2s8m_1.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BmDefaultSlave.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_bm_decodahb2bmdiv.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_bm_decodcm02bmdiv.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_ip_stage.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_op_arbapb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_op_arbapc.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_op_arbbmdiv.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_op_arblocsc0.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_op_arblocsc1.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_op_arbsqi.v \
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+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/biu/hdl/biu_sync.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/biu/hdl/biu_sync_async_fifo.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/biu/hdl/biu_sync_fifo.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/biu/hdl/biu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/edm/hdl/edm.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/edm/hdl/edm_tap.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/macro/hdl/edm_tck_inv.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/edm/hdl/edm_bcu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/edm/hdl/edm_dimu.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/edm/hdl/edm_gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/macro/hdl/ncesfp_gck.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbSyncDn/Ahb2AhbSyncDn32.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbSyncDn/Ahb2LiteSyncDn32.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbSyncDn/ErrorCanc.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbSyncDn/IncrOverride.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbSyncDn/Lite2Ahb.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbSyncUp/Ahb2AhbSyncUp32.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbSyncUp/Ahb2LiteSyncUp32.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbAsync/Ahb2AhbAsync32.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbAsync/AsyncMaster32.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbAsync/AsyncSlave32.v \
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2AhbAsync/Sync1.v \
+]

Simulate/user/script/DC/rtl_list_2.lst

@@ -0,0 +1,20 @@
+#========================================
+# List all IPs RTL file here
+# NOTE: no blank line allowed
+#========================================
+
+set search_path [list $search_path \
+/home/xian001/SY13_DATA/RTL/sy1301_20180508/AE210P/ae210p/andes_ip/n10_core/top/hdl \
+/home/xian001/SY13_DATA/RTL/sy1301_20180508/AE210P/ae210p/andes_ip/ae210/top/hdl/include \
+/home/xian001/SY13_DATA/RTL/sy1301_20180508/AE210P/ae210p/andes_ip/peripheral_ip/gpio \
+/home/xian001/SY13_DATA/RTL/sy1301_20180508/CortexM0/integration_kit/logical/user_define \
+/home/xian001/SY13_DATA/RTL/sy1301_20180508/CortexM0/integration_kit/logical/peripheral/gpio \
+/home/xian001/SY13_DATA/RTL/sy1301_20180508/AE210P/ae210p/andes_ip/ae210/define \
+]
+set RTL_FILE_LIST [list \
+/home/xian001/SY13_DATA/RTL/sy1301_20180508/CortexM0/integration_kit/logical/interconnect/sy13.v \
+/home/xian001/SY13_DATA/RTL/sy1301_20180508/CortexM0/integration_kit/logical/cm0ikmcu/verilog/CM0IKMCU.v \
+/home/xian001/SY1301_XIAN/backend/user/cbai/dc/CMOIKMCU/sys_top/20180507_final/result/sys_top_compile1.v \
+/home/xian001/SY1301_XIAN/backend/user/cbai/dc/CMOIKMCU/aoss_wrap/20180512_final/result/aoss_wrap_compile1.v \
+/home/xian001/SY1301_XIAN/backend/user/cbai/dc/ae210_chip/20180508_final/result/ae210_chip_compile1.v \
+]

Simulate/user/script/DC/rtl_list_3.lst

@@ -0,0 +1,530 @@
+#========================================
+# List all IPs RTL file here
+# NOTE: no blank line allowed
+#========================================
+
+set search_path  [list  $search_path
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/include
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/define
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/apc
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/scm
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/locsc
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/pwm
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/user_define
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/gpio
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/tbench/verilog
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/scm
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/logical/cortexm0_dap/verilog
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/logical/ualdis/verilog
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/scm
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/hash
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/rng
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/fd
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/crc
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/vpwm
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/rsa
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/rng
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/eaag
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/user_define
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/peripheral/gpio
+]
+
+set RTL_FILE_LIST [ list
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/ae210_chip.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/ae210_core.v
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/interconnect/sy13.v
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/logical/cm0ikmcu/verilog/CM0IKMCU.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2Apb/AhbToApb.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/Ahb2Apb/peripheral.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/async_clkmux.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio/n10_pad_mux.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/gpio/n10_gpio.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/nds_lib.v
+/home/xian001/SY13_DATA/RTL/sy1301/CortexM0/integration_kit/ip_fpga/BUFG.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ae210/top/hdl/ae210_cpu_subsystem_n10.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl/n10_core.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/sqi/txdatactl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/macro/gck.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/edm/hdl/reg_jtagedm_ver.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/fcu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_arbiter.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_cctl_path.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_control_path.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_lru_policy_manager.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/icache_random_policy_manager.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_control_unit.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_data_path.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ifetch_memory.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/fcu/hdl/ilm_arbiter.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_addr_mux.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_adsp_load_alignment.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_cntrl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_data_mux.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_dirty_mem.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_fb.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_gck.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_load_alignment.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_lru_mem.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_mem.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/memory/model/icache_ram.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/memory/model/dcache_ram.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_sb.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_store_alignment.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/lsu/hdl/lsu_wb.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/dtlb_ctrl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/hptwk_ctrl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/itlb_ctrl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mmu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mmu_gck.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mtlb_ctrl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/mmu/hdl/mtlb_plru.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/pcu/hdl/pcu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/top/hdl/reset_gen.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/b16_bnrtr_dtt.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_adu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_alu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_ctl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_mdu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_mdu_mul.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ieu_sau.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ifu_ctl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/iiu_ctl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/iiu_iq.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/iiu_rf.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/iru_ctl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/sru_cpu_ver.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/sru_ctl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/macro/hdl/sync_l2l.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/memory/model/btb_ram.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/tr_node1.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/tr_node2.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ucore.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/n10_core/ucore/hdl/ucore_gck.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/sdp_wrapper/hdl/sdp_wrapper.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_vip/models/cpif/hdl/cop_mux.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/csa3_2.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_clk_gen.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_cpif.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_dsu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_eu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_eu_ctr.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_eu_dp.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_iiu.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_mul.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/fp_rf.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/ncesfp/hdl/ncesfp.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_ctrl.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_engine.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_hru.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_master.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_regs.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_slave.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/ham_top.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/sfifo_10x10.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/sfifo_16x16.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/hamming/sfifo_4x26.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BP010_a2bm_BusMatrix_2s8m_1.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BmDefaultSlave.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_bm_decodahb2bmdiv.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_bm_decodcm02bmdiv.v
+/home/xian001/SY13_DATA/RTL/sy1301/AE210P/ae210p/andes_ip/peripheral_ip/BusMatrix_2s8m/verilog/rtl_source/BusMatrix_2s8m_ip_stage.v
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Simulate/user/script/DC/run_flow.tcl

@@ -0,0 +1,9 @@
+#setting
+source ./scr/00_des.tcl
+source ./scr/common_setting.tcl
+source -verbose -echo /home/xian001/SY1301_XIAN/backend/user/cbai/datain/common/dont_use.tcl > ./rpt/dont_use.rpt
+#->source ./scr/dont_use.tcl
+
+#run DC
+source ./scr/01_read_verilog.tcl
+source ./scr/02_compile.tcl

Simulate/user/script/DC/set_false_path.tcl

@@ -0,0 +1,63 @@
+#->set_false_path -through ae210_chip/ae210_core/ae210_cpu_subsystem/n10_core/reset_gen/core_reset_n_sync2_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/ae210_cpu_subsystem/u_ncesfp/fp_clk_gen/fpu_reset_n_sync2_reg/Q
+#->set_false_path -through ae210_chip/ae210_rstgen/hresetn_sync2_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_dma_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_coa_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_locsc0_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_locsc1_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_psram_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_lcd_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_ham_reg/Q
+#->set_false_path -through ae210_chip/ae210_rstgen/presetn_sync2_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/ae210_cpu_subsystem/n10_core/reset_gen/bus_reset2_n_sync2_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/ae210_cpu_subsystem/n10_core/reset_gen/bus_reset_n_sync2_reg/Q
+#->set_false_path -through ae210_chip/ae210_rstgen/U17/X
+#->set_false_path -through ae210_chip/ae210_rstgen/por_hw_rstn_sync2_reg/Q
+#->set_false_path -through ae210_chip/ae210_rstgen/presetn_sync1_reg/RD
+#->set_false_path -through ae210_chip/ae210_rstgen/presetn_sync2_reg/RD
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_i2c1_reg/Q
+#->set_false_path -through ae210_chip/ae210_core/u_rst_gate/i_rst_uart2_reg/Q
+
+
+
+set_false_path -to [get_pins -hierarchical -filter "full_name =~ */RD"]
+set_false_path -to [get_pins -hierarchical -filter "full_name =~ */SD"]
+set_false_path -from [get_clocks OSC*] -to [get_clocks {CORECLK_* SMU_CLK_* PCLK_* PLL*}]
+set_false_path -from [get_clocks FCLK_*] -to [get_clocks {CORECLK_* HCLK_* PCLK_* SWCLK}]
+set_false_path -from [get_clocks SWCLK] -to [get_clocks FCLK_*]
+set_false_path -from [get_clocks HCLK_*] -to [get_clocks {FCLK_* OSC* HCLKDIV* rpc_rds_clk_* PCLK_*}]
+set_false_path -from [get_clocks PCLK_*] -to [get_clocks {FCLK_* OSC*}]
+#->set_false_path -from [get_clocks gpioa*] -to [get_clocks FLASH_TCK_*]
+#->set_false_path -from [get_clocks FLASH_TCK_*] -to [get_clocks gpioa*]
+set_false_path -from [get_clocks CORECLK_*] -to [get_clocks OSC*]
+set_false_path -from [get_clocks PLL*] -to [get_clocks OSC*]
+set_false_path -from [get_clocks test_clk] -to [get_clocks {OSC* FCLK_*}]
+set_false_path -from [get_clocks FCLK_*] -to [get_clocks test_clk]
+set_false_path -from [get_clocks SMU_CLK_*] -to [get_clocks OSC*]
+set_false_path -from [get_clocks rpc_rds_clk_*] -to [get_clocks HCLK_*]
+set_false_path -from [get_clocks VIR_EXT_CLK120M]
+set_false_path -to [get_clocks VIR_EXT_CLK120M]
+#->set_clock_groups  -name HCLK -physically_exclusive -group {HCLK_400M} -group {HCLK_200M} -group {HCLK_100M} -group {HCLK_50M}
+
+
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad0_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad1_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad2_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad3_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad4_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad0_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad1_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad2_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad3_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc0/u_code2d_engine/grad4_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad0_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad1_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad2_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad3_reg_*/D]
+set_multicycle_path -setup 2 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad4_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad0_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad1_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad2_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad3_reg_*/D]
+set_multicycle_path -hold  1 -to [get_pins ae210_chip/ae210_core/u_locsc1/u_code2d_engine/grad4_reg_*/D]
+

Simulate/user/script/DC/syn13.0405.upf

@@ -0,0 +1,166 @@
+# Rule:
+# Power/Ground naming start with VDD/VSS
+# next step to do:
+# 1. add all the Power/Group  . e.g PLL/
+# 2. add macro connection (/home/xian001/temp_work/upf/macro.upf)
+# 3. iso setting : /home/xian001/temp_work/upf/syn13_upf_var.tcl
+
+
+source /home/xian001/temp_work/upf/syn13_upf_var.tcl
+
+######################
+set_design_top sy13
+set_scope .
+
+################################
+#######create power domain
+#################################
+# ae210_chip is power_domian 1
+# sys_top is power_domain 2
+#
+
+create_power_domain PD_TOP    -include_scope
+create_power_domain PD_sys    -elements {u_mcu/u_sys_top}
+create_power_domain PD_ae210  -elements {ae210_chip/ae210_core}
+
+####################
+###create_power_supply port
+##################
+
+create_supply_port VDD -domain PD_TOP -direction in
+create_supply_port VSS -domain PD_TOP -direction in
+
+# 
+create_supply_port VDD_IO -domain PD_TOP -direction in
+
+
+####################
+###create_power_supply net
+##################
+
+create_supply_net  VDD     -domain PD_TOP
+create_supply_net  VSS     -domain PD_TOP
+create_supply_net  VDD_IO  -domain PD_TOP
+
+create_supply_net VDD_sys -domain PD_sys
+create_supply_net VSS     -domain PD_sys -reuse
+create_supply_net VDD     -domain PD_sys -reuse
+
+
+create_supply_net VDD_ae210     -domain PD_ae210
+create_supply_net VSS           -domain PD_ae210 -reuse
+create_supply_net VDD           -domain PD_ae210 -reuse
+
+#####################
+#connect power supplu net with power supply port
+#####################
+connect_supply_net VDD -ports {VDD}
+connect_supply_net VSS -ports {VSS}
+connect_supply_net VDD_IO -ports {VDD_IO}
+
+#####################
+#set domain supply net
+#####################
+
+set_domain_supply_net PD_TOP   -primary_power_net {VDD}        -primary_ground_net {VSS}
+set_domain_supply_net PD_sys   -primary_power_net {VDD_sys}    -primary_ground_net {VSS}
+set_domain_supply_net PD_ae210 -primary_power_net {VDD_ae210}  -primary_ground_net {VSS}
+
+##########################
+#create power switch
+##########################
+create_power_switch ps_ae210 -domain PD_ae210 \
+                             -input_supply_port  {VDDP  VDD } \
+                             -output_supply_port {VDDC  VDD_ae210  } \
+                             -control_port       {ENXB  u_mcu/u_aoss_wrap/N10PwrReq } \
+                             -control_port       {EN    u_mcu/u_aoss_wrap/N10PwrReq } \
+                             -on_state           {ON  VDDP {!ENXB & EN}} \
+                             -off_state          {OFF {ENXB & !EN}}
+
+
+create_power_switch ps_sys -domain PD_sys  \
+                           -input_supply_port  {VDDP  VDD } \
+                           -output_supply_port {VDDC  VDD_sys  } \
+                           -control_port       {ENXB  u_mcu/u_aoss_wrap/sp_pwroff_req } \
+                           -control_port       {EN    u_mcu/u_aoss_wrap/sp_pwroff_req } \
+                           -on_state           {ON  VDDP {!ENXB & EN}} \
+                           -off_state          {OFF {ENXB & !EN}}
+
+
+############################
+#map power switch
+##############
+
+map_power_switch ps_sys    -domain PD_sys    -lib_cells {ts40n7khpdt_pg_ss0p99v125c/PEH_PGATDRV_OW_12 \
+                                                         ts40n7khpdt_pg_ss0p99v125c/PEH_PGATBDRV_OW_12}
+map_power_switch ps_ae210  -domain PD_ae210  -lib_cells {ts40n7khpdt_pg_ss0p99v125c/PEH_PGATDRV_OW_12 \
+                                                         ts40n7khpdt_pg_ss0p99v125c/PEH_PGATBDRV_OW_12}
+# Warning: The library cell ts40n7khpdt_pg_ss0p99v125c/PEH_PGATDRV_OW_12 specified in the command is not found and is ignored. (UPF-126)
+# Warning: The library cell ts40n7khpdt_pg_ss0p99v125c/PEH_PGATBDRV_OW_12 specified in the command is not found and is ignored. (UPF-126)
+# Warning: Unable to find a match for some of the library cells specified. (UPF-091)
+
+###############################
+#creat_isolation_cell
+#######################
+################################
+
+set_isolation PD_sys_clamp_low -domain PD_sys \
+                                -clamp_value 0 \
+                                -applies_to outputs \
+                                -elements $PD_sys_ISO_0 \
+                                -isolation_power_net VDD \
+                                -isolation_ground_net VSS
+
+
+set_isolation_control PD_sys_clamp_low -domain PD_sys \
+                                       -isolation_signal  {u_mcu/u_aoss_wrap/u_pmu/pmu_ctrl_iso_en} \
+                                       -isolation_sense   {low} \
+                                       -location {parent}
+
+map_isolation_cell PD_sys_clamp_low  -domain PD_sys -lib_cells {PEH_ISOS1CL0_W_8}
+
+################################
+
+set_isolation PD_ae210_clamp_low -domain PD_ae210 \
+                                -isolation_power_net VDD \
+                                -isolation_ground_net VSS \
+                                -clamp_value 0 \
+                                -applies_to outputs \
+                                -elements $PD_ae120_ISO_0 
+
+#set_isolation PD_ae210_clamp_high -domain PD_ae210 \ 
+#                                -isolation_power_net VDD \
+#                                -isolation_ground_net VSS \
+#                                -clamp_value 1 \
+#                                -applies_to outputs
+#                                       -element {}
+
+set_isolation_control PD_ae210_clamp_low -domain PD_ae210 \
+                                       -isolation_signal  {u_mcu/u_aoss_wrap/N10IsoEn} \
+                                       -isolation_sense   {low} \
+                                       -location {parent}
+
+#set_isolation_control PD_ae210_clamp_high -domain PD_ae210 \
+#                                       -isolation_signal  {u_mcu/u_sys_top/SppIsoEn} \
+#                                       -isolation_sense   {low} \
+#                                       -location {parent}
+
+map_isolation_cell PD_ae210_clamp_low  -domain PD_ae210 -lib_cells {PEH_ISOS1CL0_W_8}
+#map_isolation_cell PD_ae210_clamp_high  -domain PD_ae210 -lib_cells {PEH_ISOS0CL1_W_8}
+
+################################
+#set_design_attributes -attribute SNPS_reinit TRUE
+################################
+
+# PST
+add_port_state  VDD		-state {as_fast 1.21} 		-state {as_slow 0.99} 			-state {dis off}
+add_port_state  VSS		-state {ena 0}			-state {dis off}
+add_port_state  ps_sys/VDDC     -state {as_fast 1.21}            -state {as_slow 0.99}                   -state {dis off}
+add_port_state  ps_ae210/VDDC   -state {as_fast 1.21}            -state {as_slow 0.99}                   -state {dis off}
+
+create_pst syn13_pst \
+  -supplies 						{VDD		VDD_sys		VDD_ae210	VSS}
+add_pst_state all_on  	 	-pst syn13_pst 	-state  {as_fast	as_fast		as_fast		ena}
+add_pst_state sys_off 	 	-pst syn13_pst  -state  {as_fast        dis             as_fast		ena}
+add_pst_state all_off           -pst syn13_pst  -state  {dis		dis		dis		dis}
+

Simulate/user/script/P&R.tcl

@@ -0,0 +1,43 @@
+source /home/project/ASIC/FFT_IFFT_IP/user/script/setup.tcl
+
+## ******************** 设置综合环境 ******************** ##
+set PR_PATH    /home/project/ASIC/FFT_IFFT_IP/prj/P&R
+
+set LIB_PATH    /home/project/ASIC/library/smic180/std
+set STD_NAME    SCC018UG_UHD_RVT_V0p4a
+
+#导入milkway
+set tf_path $LIB_PATH/$STD_NAME/astro/tf
+set mw_path $LIB_PATH/$STD_NAME/astro/scc018ug_uhd_rvt
+set tluplus $LIB_PATH/$STD_NAME/astro/tluplus
+
+create_mw_lib   MWlib.mw \
+    -technology $tf_path \
+    -mw_reference_library  $mw_path -open
+
+#导入网表文件
+import_designs $RES_OUT/$CURR_DESIGN.ddc  \
+    -format ddc \
+    -top $CURR_DESIGN  
+
+uniquify_fp_mw_cel
+current_design $CURR_DESIGN
+
+#导入RC参数文件和.map文件
+set_tlu_plus_files  \
+    -max_tluplus    $tluplus/smiclog018_6lm_cell_max.tluplus  \
+    -min_tluplus    $tluplus/smiclog018_6lm_cell_min.tluplus \
+    -tech2itf_map   $tluplus/smic18_6lm_lef_smic18_6lm_tf.map   
+
+report_tlu_plus_files  > $RPT_OUT/report_tlu_plus.rpt
+check_tlu_plus_files   > $RPT_OUT/check_tlu_plus.rpt
+
+remove_sdc
+read_sdc /home/project/ASIC/FFT_IFFT_IP/user/data/constraint/timing.sdc
+set_clock_uncertainty 2  [all_clocks]
+
+remove_propagated_clock  [all_clocks]
+check_timing 
+
+save_mw_cel
+start_gui

Simulate/user/script/lib2db.tcl

@@ -0,0 +1,15 @@
+# 将lib_path下的所有lib文件转换成db文件
+set lib_path user/src/utils/RAM/2048FP
+
+proc lib2db {path} {
+    set dir [file dirname $path]
+    set name [file rootname [file tail $path]]
+    read_lib $path
+    write_lib -format db ${name} -output $dir/db/${name}.db
+}
+
+foreach lib [glob $lib_path/*.lib] { 
+    lib2db $lib
+}
+
+exit

Simulate/user/script/scan.tcl

@@ -0,0 +1,50 @@
+reset_scan_configuration
+
+## ******************** 进行scan chain的插入 ******************** ##
+set_dft_insertion_configuration -preserve_design_name   true
+set_dft_insertion_configuration -synthesis_optimization none
+
+set_scan_configuration -clock_mixing mix_clocks
+
+set_dft_signal -view spec -type ScanDataIn  -port { SI0 } -hookup_pin SI0_PAD/C
+set_dft_signal -view spec -type ScanDataIn  -port { SI1 } -hookup_pin SI1_PAD/C
+set_dft_signal -view spec -type ScanDataIn  -port { SI2 } -hookup_pin SI2_PAD/C
+set_dft_signal -view spec -type ScanDataIn  -port { SI3 } -hookup_pin SI3_PAD/C
+set_dft_signal -view spec -type ScanDataIn  -port { SI4 } -hookup_pin SI4_PAD/C
+
+set_dft_signal -view spec -type ScanDataOut -port { SO0 } -hookup_pin SO0_PAD/I
+set_dft_signal -view spec -type ScanDataOut -port { SO1 } -hookup_pin SO1_PAD/I
+set_dft_signal -view spec -type ScanDataOut -port { SO2 } -hookup_pin SO2_PAD/I
+set_dft_signal -view spec -type ScanDataOut -port { SO3 } -hookup_pin SO3_PAD/I
+set_dft_signal -view spec -type ScanDataOut -port { SO4 } -hookup_pin SO4_PAD/I
+
+set_dft_signal -view spec -type ScanEnable  -port { SEN } -hookup_pin SEN_PAD/C
+
+# set_dft_signal -view existing_dft -type ScanEnable -port SEN    -hookup_pin SEN_PAD/C
+set_dft_signal -view existing_dft -type TestMode   -port SMODE  -hookup_pin SMODE_PAD/C
+set_dft_signal -view existing_dft -type Reset      -port SRESET -hookup_pin SRESET_PAD/C  -active 0
+
+set_dft_signal -view existing_dft -type ScanClock -port CLK -timing {45 55}
+
+set_dft_signal -view spec -type TestMode -port SMODE
+set_dft_signal -view spec -type TestData -port CLK
+set_dft_signal -view spec -type TestData -port SRESET
+
+set_dft_configuration -fix_clock enable
+set_dft_configuration -fix_set   enable
+set_dft_configuration -fix_reset enable
+
+set_scan_configuration -chain_count 5
+
+set_autofix_configuration -method mux -type clock -fix_data enable -control_signal SMODE
+set_autofix_configuration -method mux -type reset -fix_data enable -control_signal SMODE -test_data SRESET
+
+create_test_protocol
+
+insert_dft
+
+change_names -rules verilog -hierarchy
+#保存综合后的设计
+write -format ddc -hierarchy -output $RES_OUT/${CURR_DESIGN}.mapped.scan.ddc
+#输出网表，自动布局布线需要
+write -f verilog -hierarchy -output $RES_OUT/${CURR_DESIGN}.mapped.scan.v

Simulate/user/script/setup.tcl

@@ -0,0 +1,110 @@
+# 本脚本用于搭建设计
+# 1. 导入lib
+# 2. 导入设计
+
+## ******************** 设置全局环境 ******************** ##
+set RTL_PATH  /home/project/ASIC/FFT_IFFT_IP/user/src
+set PRJ_PATH  /home/project/ASIC/FFT_IFFT_IP/prj
+set ROOT_PATH /home/project/ASIC/FFT_IFFT_IP
+set VERSION   v0.3
+
+set F_TEMP -40
+
+## current design / top name
+set CURR_DESIGN     "top"
+
+set RPT_DIR         RPT$VERSION
+set OUT_DIR         OUT$VERSION
+
+set RPT_OUT [format "%s%s" $PRJ_PATH/ $RPT_DIR]
+set RES_OUT [format "%s%s" $PRJ_PATH/ $OUT_DIR]
+
+sh rm -rf $RPT_OUT $RES_OUT
+sh mkdir -p $RPT_OUT $RES_OUT
+
+## ******************** 指定设计库文件 ******************** ##
+# 设置library寻找的路径 优先导入std和io
+set search_path { \
+    /home/project/ASIC/library/smic180/std/SCC018UG_HD_RVT_V0p3a/syn/1.8v/liberty_ff \
+    /home/project/ASIC/library/smic180/std/SCC018UG_HD_RVT_V0p3a/syn/1.8v/liberty_tt \
+    /home/project/ASIC/library/smic180/std/SCC018UG_HD_RVT_V0p3a/syn/1.8v/liberty_ss \
+    /home/project/ASIC/library/smic180/io/SP018D18RP_V0p7/syn/1p8v \
+}
+
+# 依次导入mem library path
+foreach mem_path [glob $RTL_PATH/utils/{RAM}/*] {
+    lappend search_path $mem_path/db
+}
+
+# 设置STD library
+# SMIC180 G-MS工艺  SCC018UG_UHD_RVT ------- 1.8V
+set lib_fast     scc018ug_hd_rvt_ff_v1p98_${F_TEMP}c_basic     
+set lib_type     scc018ug_hd_rvt_tt_v1p8_25c_basic     
+set lib_slow     scc018ug_hd_rvt_ss_v1p62_125c_basic   
+
+# 设置IO library
+# SMIC180 G-MS工艺  SP018D18RP ---- 1.8V core + 1.8V IO + 2.5VT + L
+set io_fast     SP018D18RP_V0p6_max
+set io_type     SP018D18RP_V0p6_typ
+set io_slow     SP018D18RP_V0p6_min
+
+set target_library   [list ${lib_fast}.db]
+set link_library     [list "*" ${lib_fast}.db ${io_fast}.db]
+
+# 设置MEM library
+set mem_fast     _ff_1.98_${F_TEMP}
+set mem_type     _tt_1.8_25
+set mem_slow     _ss_1.62_-40
+
+# 导入MEM library 
+foreach mem_lib [glob $RTL_PATH/utils/{RAM}/*/db/*$mem_fast.db] {
+    lappend link_library [file tail $mem_lib]
+}
+
+## ******************** 指定设计源文件 ******************** ##
+# proc findFiles { path result args } {
+#     if {![file exists $path] || ![file isdirectory $path]} {
+#         return -code err "File not exits or not a directory"
+#     }
+
+#     # puts $args
+#     set paramList  [lindex $args 0 end]
+#     # puts $paramList
+
+#     # set files [glob -nocomplain -directory $path/ -tails *]
+#     set files [glob -nocomplain -directory $path/ *]
+#     foreach i_file $files {
+#         if {[file isfile $i_file]} {
+#             set fileExtName [file extension $i_file]
+#             foreach i_args $args {
+#                 # puts $fileExtName
+#                 # puts $i_args
+#                 if {$fileExtName == $i_args} {
+#                     # puts $i_file
+#                     set result [linsert [lindex $result end] end $i_file]
+#                 }
+#             } 
+#         } elseif {[file isdirectory $i_file]} {
+#             # recursion 
+#             foreach element [findFiles $i_file $result $paramList] {
+#                 set result [linsert [lindex $result end] end $element]
+#             }  
+#             # puts "once"
+#             # set result [concat $result [findFiles $i_file $result $paramList]]
+#         }
+#     }
+    
+#     foreach elem $result {
+#         puts $elem
+#     } 
+#     return $result
+# }
+
+# set res {}
+# set res [findFiles $RTL_PATH $res ".v"]
+# # foreach elem $res {
+# #     puts $elem
+# # } 
+
+# exit
+# source user/script/setup.tcl

Simulate/user/script/synth.tcl

@@ -0,0 +1,175 @@
+## ******************** 设置综合环境 ******************** ##
+source /home/project/ASIC/FFT_IFFT_IP/user/script/setup.tcl
+
+set DO_SCAN 0
+
+## ******************** common  setting ******************** ##
+#dc common setting
+set_host_options -max_cores 8
+set compile_enable_register_merging false
+set svf_file_records_change_names_changes true
+set enable_recovery_removal_arcs true
+set case_analysis_with_logic_constants true
+set timing_enable_multiple_clocks_per_reg "true"
+set compile_instance_name_prefix "U"
+set verilogout_no_tri true
+set verilogout_show_unconnected_pins true
+set bind_unused_hierarchical_pins false
+
+#CLOCK gating setting
+set compile_clock_gating_through_hierarchy false
+#->set power_cg_auto_identify true
+#->positive_edge_logic integrated
+set_clock_gating_style \
+        -sequential_cell latch \
+        -control_point before \
+        -control_signal scan_enable \
+        -observation_point false \
+        -max_fanout 16 \
+        -minimum_bitwidth 4
+#--append   --------------------------------------------
+set pwr_hdlc_split_cg_cells                 true
+set timing_scgc_override_library_setup_hold true
+set power_keep_license_after_power_commands true
+set verilogout_equation false
+set compile_seqmap_propagate_constants false
+set compile_seqmap_propagate_high_effort false
+set set_ultra_optimization "true"
+set compile_seqmap_identify_shift_registers false
+set compile_seqmap_no_scan_cell true
+set compile_seqmap_propagate_constants false
+set compile_delete_unloaded_seqential_cells false
+set timing_report_unconstrained_paths true
+set hdlin_enable_vpp                            true
+set power_keep_license_after_power_command      true
+set single_group_per_sheet                      true
+set auto_wire_load_selection false
+
+set timing_disable_recovery_removal_checks false
+set enable_recovery_removal_arcs true
+
+# 开始记录DC综合的变动
+set_svf $RES_OUT/$CURR_DESIGN.svf
+set_app_var dc_allow_rtl_pg true
+
+## ******************** 读取设计源文件 ******************** ##
+#读入设计
+analyze -format verilog { \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/top.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/FFT_FLOW.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/send.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/sum.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/utils/ram.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/utils/SPI_M2S.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/utils/math/cmult.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/utils/RAM/2048FP/RAM2048.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/top/FFT_IFFT.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/top/fft.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/stage/BF_stage.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/stage/fft_stage.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/utils/BF_op.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/utils/ftrans_I.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/utils/ftrans_II.v \
+    /home/project/ASIC/FFT_IFFT_IP/user/src/Flow_FFT_IFFT/utils/ftwiddle.v \
+}
+elaborate $CURR_DESIGN -architecture verilog
+current_design $CURR_DESIGN
+set_fix_multiple_port_nets -all -buffer_constants
+set hdlout_internal_busses true
+set bus_inference_style "%s\[%d\]"
+# define_name rules verilog -check_bus_indexing -allowed {a-XA-Z0-9_}
+link > $RPT_OUT/00_link_design.log
+set uniquify_naming_style ${CURR_DESIGN}_%s_%d
+uniquify -force
+check_design > $RPT_OUT/01_check_design.log
+report_attributes -design
+set_dont_touch u_FFT_FLOW/u_FFT_IFFT/FFT_INST.fft_ins/stagX[*].u_fft_stage/LARGER_THAN_2.BF_inst_I/u_ram/RAM_GEN.RAM*_IP.u_RAM*
+set_dont_touch *_PAD*
+set_dont_touch [get_ports CLK -filter {@port_direction == in} -quiet]
+set_dont_touch u_FFT_FLOW/u_sum/u*_RAM2048/u*_FRAM512
+set_dont_use scc018ug_hd_rvt_ff_v1p98_-40c_basic/PULLHD0 
+set_dont_use scc018ug_hd_rvt_ff_v1p98_-40c_basic/PULLHD1
+## ******************** 进行设计约束 ******************** ##
+# sdc
+read_sdc /home/project/ASIC/FFT_IFFT_IP/user/data/constraint/timing.sdc
+set_operating_conditions -max ff_v1p98_${F_TEMP}c -library $lib_fast
+set_app_var auto_wire_load_selection false
+# set_wire_load_model -name ForQA
+# set_wire_load_mode enclosed  
+
+# 设置输入transtion，注：需要将输入时钟信号去除
+set_input_transition 0.89 [remove_from_collection [all_inputs] [get_clocks clk]]
+
+echo "INFO : Defining Reset : RSTN"
+set_drive 0 [get_ports RSTN -filter {@port_direction == in} -quiet]
+set_false_path -from [get_ports RSTN -filter {@port_direction == in} -quiet]
+set_ideal_network -no_propagate [get_nets -of_object [get_ports RSTN -filter {@port_direction == in} -quiet] -quiet]
+set_ideal_network -no_propagate [get_nets -of_object [get_ports CLK -filter {@port_direction == in} -quiet] -quiet]
+
+# set_ideal_network -no_propagate [get_nets -of_object [get_ports rstn -filter {@port_direction == in} -quiet] -quiet]
+# set_ideal_network -no_propagate [get_nets -of_object [get_ports iclk -filter {@port_direction == in} -quiet] -quiet]
+# 对时序进行分组
+# set ports_clock_root [filter_collection [get_attribute [get_clocks] sources] object_class==port]
+# group_path -name reg2out -from [all_registers -clock_pins] -to [all_outputs]
+# group_path -name in2reg  -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_registers -data_pins]
+# group_path -name in2out  -from [remove_from_collection [all_inputs] $ports_clock_root] -to [all_outputs]
+
+set clock_ports [get_ports -quiet [all_fanout -clock_tree -flat]]
+set all_inputs [all_inputs]
+set all_outputs [all_outputs]
+set all_nonclk_inputs [remove_from_collection $all_inputs $clock_ports]
+set all_nonclk_outputs [remove_from_collection $all_outputs $clock_ports]
+set all_icgs [get_cells -hier -filter "is_integrated_clock_gating_cell == true"]
+set all_reg [all_registers]
+set all_reg [remove_from_collection $all_reg $all_icgs]
+
+group_path -from $all_reg -to $all_reg -name reg2reg
+group_path -from $all_reg -to $all_nonclk_outputs -name reg2out
+group_path -from $all_nonclk_inputs -to $all_reg -name in2reg
+group_path -from $all_nonclk_inputs -to $all_nonclk_outputs -name in2out
+#group_path -from $all_reg -to $all_icgs -name reg2gate
+report_path_group
+
+set_critical_range 3 [current_design]
+
+#设置在RTL代码中用上升沿沿触发的寄存器采用使用集成门控时钟单元。
+#设置该门控单元在DFT时的控制点放在门逻辑中的锁存器之前。
+#设置一个门控单元所驱动的最大负载数目，定义CG单元最大扇出的一个目的是减少CG后面的时钟延迟
+#门控时钟单元的扇出越大，它到达寄存器的延迟越长
+#此外，还有用来约束重新平衡
+#设置进行时钟门控的寄存器阵列的最小宽度（一个门控时钟至少要触发4个寄存器）
+#基于锁存器的离散门控单元
+# set_clock_gating_style \
+#         -positive_edge_logic {integrated:saed90nm_max_hth_cg_lvt/CGLPPRX8_LVT} \
+#         -control_point before \
+#         -max_fanout 32 \
+#         -no_sharing \
+#         -minimum_bitwidth 4 \
+#         -sequential_cell latch
+
+## ******************** 映射门级单元及优化 ******************** ##
+#综合并插入门控时钟单元
+compile_ultra -incremental -scan -gate_clock
+
+## ******************** 检查综合结果并输出报告 ******************** ##
+#报出所有违规，包括setup, hold check, drv, clock gating check等
+report_constraint -all_violators  > $RPT_OUT/all_vios.rpt
+check_design > $RPT_OUT/05_check_design.log
+check_timing > $RPT_OUT/06_check_timing.rpt
+
+#为formality进行停止记录数据（形式验证）
+set_svf -off
+
+#因为DC和其它的XX命名规则不同，为了避免出现问题，在产生网表之前先要定义一些命名规则。
+change_names -rules verilog -hierarchy
+uniquify -force
+
+#保存综合后的设计
+write -format ddc -hierarchy -output $RES_OUT/${CURR_DESIGN}.ddc
+#输出网表，自动布局布线需要
+write -f verilog -hierarchy -output $RES_OUT/${CURR_DESIGN}.v
+
+## ******************** 进行scan chain的插入 ******************** ##
+source /home/project/ASIC/FFT_IFFT_IP/user/script/scan.tcl
+
+exit

Simulate/user/script/template/00_des.tcl

@@ -0,0 +1,17 @@
+#common setting
+set TOP sy13
+set_svf "./result/${TOP}.svf"
+source ./scr/rtl_list_2.lst
+
+#set library
+#timing lib
+set LIB_CORNER      wc
+set USER_LIB_SET "9T_HVT_RVT_POK_SYNOPSYS"
+#->source /home/xian001/SY1301_XIAN/backend/common/lib_common_synopsys_cbai.tcl
+source /home/xian001/SY1301_XIAN/backend/common/lib_common_synopsys_cbai_update.tcl
+#dc setting
+set DW_PATH "/tools/synopsys/dc/J-2014.09-SP3/libraries/syn"
+set search_path ". $search_path $DW_PATH"
+set synthetic_library dw_foundation.sldb
+set link_library "$link_library $synthetic_library"
+define_design_lib work -path ./work

Simulate/user/script/template/01_read_verilog.tcl

@@ -0,0 +1,14 @@
+#intial setting
+#->read_verilog -netlist xxx
+set_app_var dc_allow_rtl_pg true
+lappend DEFINE_LIST ""
+analyze -format verilog -l work -define $DEFINE_LIST $RTL_FILE_LIST
+#link design
+elaborate $TOP
+current_design $TOP
+set_fix_multiple_port_nets -all -buffer_constants
+link > ./rpt/00_link_design.log
+set uniquify_naming_style ${TOP}_%s_%d
+uniquify -force
+check_design > ./rpt/01_check_design.log
+write -format ddc -h -out ./result/${TOP}_elaborate.ddc

Simulate/user/script/template/02_compile.tcl

@@ -0,0 +1,82 @@
+#read sdc constraints
+remove_sdc
+source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180502_sdc/sy13_top_con.tcl > ./rpt/02_read_sdc.log
+source -echo -verbose ./scr/sdc/get_mem.tcl >> ./rpt/02_read_sdc.log
+source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180403_sdc/update_0410/scan_dont_touch.tcl >> ./rpt/02_read_sdc.log
+#->source /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180403_sdc/sdc_update.tcl >> ./rpt/02_read_sdc.log
+#->source ./scr/group_path.tcl
+#group_path -name REG2REG -from [all_registers] -to [all_registers] -critical_range 0.5 -weight 10
+#group_path -name FROM_MEM -from [all_registers] to [all_registers] -critical_range 0.5 -weight 10
+#--dont touch   --------------------------------------------
+#set_dont_touch ae210_chip
+#set_dont_touch [get_cells * -hierarchical -filter "full_name =~ ae210_chip/ae210_core/*/*"] true
+#set_dont_touch [get_nets * -hierarchical -filter "full_name =~ ae210_chip/ae210_core/*/*"] true
+set_dont_touch ae210_chip
+set_dont_touch u_mcu/u_sys_top
+set_dont_touch u_mcu/u_aoss_wrap
+set_operating_condition SS0P99V125C
+#--add upf   --------------------------------------------
+set mv_enabke_power_domain_power_net_check false
+set upf_create_implicit_supply_sets false
+set upf_iso_filter_elements_with_applies_to ENABLE
+remove_upf
+#->load_upf /home/xian001/SY1301_XIAN/backend/user/slpeng/pr/20180326/scripts/upf/rtl_20170721.upf > ./rpt/03_read_upf.log
+#->load_upf /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180425_upf/syn13.0422.upf > ./rpt/03_read_upf.log
+source -echo -verbose ./scr/create_vddq_en_pin.tcl > ./rpt/03_read_upf.log
+load_upf /home/xian001/temp_work/upf/0423/sy13.upf >> ./rpt/03_read_upf.log
+source -echo -verbose /home/xian001/SY1301_XIAN/backend/user/cbai/datain/20180425_upf/modify/set_voltage.0429.tcl >> ./rpt/03_read_upf.log
+set mv_upf_check_pg_pins_of_target_lib_cells true
+check_mv_design > ./rpt/check_mv_design.rpt
+
+#start to compile
+#setting
+set_fix_multiple_port_nets -all -buffer_constants
+set_max_area 0
+set verilogout_equation false
+set compile_seqmap_propagate_constants false
+set compile_seqmap_propagate_high_effort false
+set set_ultra_optimization "true"
+set compile_seqmap_identify_shift_registers false
+#--dont touch false for iso   --------------------------------------------
+#->source ./scr/dont_touch_port.lst
+#->set_dont_touch [get_nets -of [get_ports $iso_ports]] false
+#compile
+check_timing  > ./rpt/03_check_timing.rpt
+#-- first compile  --------------------------------------------
+#compile_ultra -timing_high_effort_script -no_autoungroup -no_seq_output_inversion -gate_clock -scan -no_design_rule
+#compile_ultra -no_autoungroup -gate_clock -scan -no_auto_layer_optimization
+compile_ultra -gate_clock -no_seq_output_inversion -scan -no_autoungroup -timing_high_effort_script
+#->save_upf ./result/syn_done_v1.upf
+#report
+
+#change name & output verilog
+source ./scr/change_name.tcl
+write -hier -format verilog -out ./result/${TOP}.v
+write -format ddc -h -out ./result/${TOP}.ddc
+report_constraint -max_delay -nosplit -all_violators -significant_digits 3 > ./rpt/${TOP}.report_constraint.rpt
+report_constraint -max_delay -nosplit -all_violators -max_delay -verbose > ./rpt/${TOP}.report_constraint_verbose.rpt
+report_qor > ./rpt/${TOP}.qor
+
+write_sdc -nosplit ./result/${TOP}.sdc
+save_upf ./result/${TOP}.upf
+#--dont touch list   --------------------------------------------
+set_dont_touch [get_cells -hierarchical -filter "full_name =~ u_mcu/u_aoss_wrap/u_aoss_pad_ring/* && is_hierarchical == false"] true
+set_dont_touch [get_nets -of [get_cells * -hierarchical -filter "full_name =~ *DLY*"]] true
+#set_dont_touch [get_nets -of [get_cells -hierarchical -filter "full_name =~ u_mcu/u_aoss_wrap/u_aoss_pad_ring/* && is_hierarchical == false"]] true
+set dont_touch_cells [get_cells -hier * -filter {@is_hierarchical==false && @dont_touch == true}]
+foreach_in_collection cell $dont_touch_cells {
+	redirect -append ./result/dont_touch.lst {puts [get_att [get_cells $cell] full_name]}
+}
+#set dont_touch_nets [get_nets -hierarchical -filter "dont_touch == true"]
+set dont_touch_dly_nets [get_nets -of [get_cells * -hierarchical -filter "full_name =~ *DLY*"]]
+foreach_in_collection net $dont_touch_dly_nets {
+        redirect -append ./result/dont_touch.lst {puts [get_att [get_nets $net] full_name]}
+}
+
+report_clock_gating -nosplit > ./rpt/04_report_clock_gating.rpt
+check_design > ./rpt/05_check_design.log
+check_timing  > ./rpt/06_check_timing.rpt
+source ./scr/gpio_timing.tcl
+source ./scr/disconnect_net.tcl
+write -hier -format verilog -out ./result/${TOP}_disconnect.v
+set_svf -off

Simulate/user/script/template/ae210_core_sdc.tcl

@@ -0,0 +1,105 @@
+#################clock################
+set CLOCKS_LIST [ list \
+    hclk       2.5 0  1.25 \
+    hclk2      2.5 0  1.25 \
+    core_clk   2.5 0  1.25 \
+    pclk       5.0 0  2.5 \
+    uart2_clk  5.0 0  2.5 \
+    T4CLK      5.0 0  2.5 \
+    T5CLK      5.0 0  2.5 \
+    T6CLK      5.0 0  2.5 \
+    T7CLK      5.0 0  2.5 \
+]
+#->hclkdiv3   7.5 0  3.75
+set  pre_clock_margin 0.8
+
+foreach [ list CKPORT PRD R F ] $CLOCKS_LIST {
+	echo "INFO : Defining Clock: $CKPORT"
+	lappend CLOCKS_NAME_LIST $CKPORT
+        set PRD_WM  [expr $PRD * $pre_clock_margin]
+        set RW_WM   [expr $R   * $pre_clock_margin]
+        set FW_WM   [expr $F   * $pre_clock_margin]
+	create_clock -name $CKPORT [get_ports $CKPORT] -period $PRD_WM -waveform [list $RW_WM $FW_WM]
+        set_dont_touch_network $CKPORT
+        set_ideal_network $CKPORT
+        set_clock_uncertainty [ expr 0.03 * $PRD_WM] [ get_clocks $CKPORT ]
+}
+echo "INFO : Clocks Defined : $CLOCKS_NAME_LIST"
+set_clock_transition 0.2 [all_clocks]
+
+################reset##############
+set RESETS_LIST [ list \
+        hresetn \
+        hreset2_n \
+        core_resetn \
+        presetn \
+	globalresetn \
+]
+#-> WdtResetn
+if { [ llength RESETS_LIST ] > 0 } {
+    foreach RstName $RESETS_LIST {
+      #/***********************************************************************/
+      #/*   create reset
+      #/***********************************************************************/
+      echo "INFO : Defining Reset : $RstName"
+      set_drive 0 [get_ports $RstName -filter {@port_direction == in} -quiet]
+      set_false_path -from [get_ports $RstName -filter {@port_direction == in} -quiet]
+      set_ideal_network -no_propagate [get_nets -of_object [get_ports $RstName -filter {@port_direction == in} -quiet] -quiet]
+    }
+}
+
+##########input/output delay##############
+set clkname hclk
+set CLKPERIOD [ get_attribute [get_clocks $clkname] period ]
+set InputMaxDelay  [ expr $CLKPERIOD * 0.7 ]
+
+set OutputMaxDelay [ expr $CLKPERIOD * 0.7 ]
+#--Option
+set InputMinDelay  [ expr $CLKPERIOD * 0 ]
+set OutputMinDelay [ expr $CLKPERIOD * 0 ]
+set MaxDelay 0.2
+
+set AllInputNoClkRst [remove_from_collection [all_inputs] [list hresetn hreset2_n core_resetn presetn uart_rstn hclk hclk2 core_clk pclk uart2_clk T4CLK T5CLK T6CLK T7CLK scan_enable scan_test] ]
+set AllOutput [ all_outputs ]
+
+set_input_delay $InputMaxDelay -max -clock $clkname $AllInputNoClkRst
+set_input_delay $InputMinDelay -min -clock $clkname $AllInputNoClkRst
+
+set_output_delay $OutputMaxDelay -max -clock $clkname $AllOutput
+set_output_delay $OutputMinDelay -min -clock $clkname $AllOutput
+
+
+set OutputMaxDelay_0p4 [ expr $CLKPERIOD * 0.4 ]
+set_max_delay [ expr $MaxDelay + $InputMaxDelay + $OutputMaxDelay ] -from $AllInputNoClkRst -to $AllOutput
+
+########################exceptions###############
+#false path
+#->set_false_path -from [get_clock  hclkdiv3] -to [get_clocks {list uart2_clk pclk T4CLK T5CLK T6CLK T7CLK}]
+#->set_false_path -from [get_clocks {list uart2_clk pclk T4CLK T5CLK T6CLK T7CLK} ] -to [get_clock  hclkdiv3]
+#multi cycle path
+set_multicycle_path 2 -setup -end -from [get_clocks [list pclk uart2_clk]] -to [get_clocks  [list hclk hclk2 core_clk]]
+set_multicycle_path 1 -hold  -end -from [get_clocks [list pclk uart2_clk]] -to [get_clocks [list hclk hclk2 core_clk]]
+
+set_multicycle_path 2 -setup -start -to [get_clocks [list pclk uart2_clk]] -from [get_clocks [list hclk hclk2 core_clk]]
+set_multicycle_path 1 -hold  -start -to [get_clocks [list pclk uart2_clk]] -from [get_clocks [list hclk hclk2 core_clk]]
+
+
+#->set_multicycle_path 3 -setup -end -from [get_clocks hclkdiv3] -to [get_clocks {list hclk hclk2 core_clk}]
+#->set_multicycle_path 2 -hold  -end -from [get_clocks hclkdiv3] -to [get_clocks {list hclk hclk2 core_clk }]
+
+#->set_multicycle_path 3 -setup -start -to [get_clocks hclkdiv3] -from [get_clocks {list hclk hclk2 core_clk }]
+#->set_multicycle_path 2 -hold  -start -to [get_clocks hclkdiv3] -from [get_clocks {list hclk hclk2 core_clk }]
+
+set_multicycle_path 2 -setup -from [get_pins u_sram*/*u_sram8Kx64_*/CLK ] -to [get_pins  u_sram*/Q_reg*/data_in]
+set_multicycle_path 1 -hold  -from [get_pins u_sram*/*u_sram8Kx64_*/CLK ] -to [get_pins  u_sram*/Q_reg*/data_in]
+
+
+
+set mem_cells [get_cells -hierarchical -filter "ref_name == sadsls7k41p8192x64m8b4w1c0p0d0t0ss10"]
+
+foreach_in_collection mem_cell $mem_cells {
+	set mem_cell_full_name [get_attribute [get_cells $mem_cell] full_name]
+	echo "$mem_cell_full_name"
+	set_multicycle_path  2 -setup -from [get_pins $mem_cell_full_name/CLK]
+	set_multicycle_path  1 -hold  -from [get_pins $mem_cell_full_name/CLK]
+}

Simulate/user/script/template/change_name.tcl

@@ -0,0 +1,6 @@
+set_fix_multiple_port_nets -all -buffer_constants [get_designs *]
+set hdlout_internal_busses true
+set bus_inference_style "%s\[%d\]"
+set veriligout_no_tri true
+define_name_rules verilog -check_bus_indexing -allowed {a-zA-Z0-9_} -remove_internal_net_bus -flatten_multi_dimension_busses -first_restricted "\\"
+change_names -rules verilog -hier -verbose